JPH0845952A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To manufacture a bipolar transistor which is excellent in high-frequency characteristics and small in dispersion of characteristics. CONSTITUTION:An SiO2 side wall 42 is formed on an Si3N4 film 37a, and an Si3N4 film 37b is processed using the side wall 42 as a mask. An element isolating region is formed using an Si3N4 film 37 as a mask, and an emitter and a graft base are formed in regions which are corresponding to the Si3N4 films 37a and 37b. Thereafter, the graft base can be lessened in area, and a Si substrate 14 located in the emitter forming region is protected against damage and chipping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor having a graft base.

[0002]

2. Description of the Related Art FIG. 21 shows a planar type NPN bipolar transistor manufactured in a first conventional example of the present invention. In this first conventional example, a P-type S
After the N ⁺ buried layer 12 as a buried collector is selectively formed on the surface of the i substrate 11, an N type Si layer 13 is epitaxially grown on the entire surface of the Si substrate 11 to form Si.
The substrate 11 and the Si layer 13 form a Si base 14.

Thereafter, a SiO ₂ film 15 is selectively formed on the surface of the Si substrate 14 to form an element isolation region, and an N ⁺ impurity layer 16 as a collector extraction layer and a P ⁺ impurity layer 17 as a graft base are formed. And a P impurity layer 18 as an intrinsic base are formed in the element active region. Then, an insulating film such as the SiO ₂ film 21 is formed on the entire surface, and an opening 22 corresponding to the emitter formation region is formed in the SiO ₂ film 21.

After that, the polycrystalline Si film 2 containing N-type impurities
3 is formed, and the polycrystalline Si film 23 through the opening 22
N type impurities are diffused into the i base 14 to form an N ⁺ impurity layer 24 as an emitter. Then, the openings 25 and 26 for the N ⁺ impurity layer 16 and the P ⁺ impurity layer 17 are S
It is formed on the iO ₂ film 21, and the emitter wiring, the base wiring and the collector wiring are formed by the metal film 27.

However, in the above first conventional example, the opening 2
The opening 26 cannot be formed in a self-aligning manner with respect to No. 2 and a mask alignment margin is required between these openings 22 and 26. It is also necessary to secure a predetermined space between the metal films 27.

Because of these, the graft base P
⁺ Manufacture of a bipolar transistor excellent in high frequency characteristics because the area of the impurity layer 17 and the P impurity layer 18 which is the intrinsic base cannot be reduced, and the parasitic capacitance due to the base-collector junction cannot be reduced. I couldn't.

22 to 24 show a second conventional example of the present invention for manufacturing an NPN bipolar transistor called a polysilicon base type. This second
Also in the conventional example, as shown in FIG. 22, until the N ⁺ impurity layer 16 as the collector extraction layer is formed, substantially the same steps as in the first conventional example shown in FIG. 21 are performed.

However, in this second conventional example, S
an insulating film iO ₂ film 21 or the like is formed on the entire surface, the SiO ₂
The portion of the film 21 on the formation region of the base and the emitter is removed. Then, the polycrystalline Si film 3 containing P-type impurities
1 and an insulating film such as a SiO ₂ film 32 are sequentially formed, and the SiO ₂ film 32 and the polycrystalline Si film 31 are dry-etched.
Is processed into the shape of the base lead wiring, and at the same time, the opening 22 corresponding to the emitter formation region is formed in the SiO ₂ film 32 and the polycrystalline Si film 31.

Next, as shown in FIG. 23, the polycrystalline Si film 3
P-type impurities are diffused from 1 to the Si substrate 14 to form a P ⁺ impurity layer 17 as a graft base, and the opening 22 is formed.
P-type impurities are ion-implanted into the Si substrate 14 via
A P impurity layer 18 as an intrinsic base is formed. Then, an insulating film such as the SiO ₂ film 33 is deposited on the entire surface, and the entire surface of the SiO ₂ film 33 is etched back to form a side wall made of the SiO ₂ film 33 on the inner side surface of the opening 22 and inside the side wall. An opening 34 is formed in

Next, as shown in FIG. 24, a polycrystalline Si film 23 containing N-type impurities is formed, and the N-type impurities are diffused from the polycrystalline Si film 23 to the Si substrate 14 through the openings 34, An N ⁺ impurity layer 24 as an emitter is formed. Then, the openings 25 and 26 for the N ⁺ impurity layer 16 and the polycrystalline Si film 31 are formed in the SiO ₂ films 21 and 32, and the emitter wiring, the base wiring and the collector wiring are formed of the metal film 27.

In the above second conventional example, the polycrystalline Si film 31 is used.
Since the base lead-out wiring is formed by, it is not necessary for the P ⁺ impurity layer 17 to extend below the opening 26. Moreover, since the openings 34 can be formed in a self-aligned manner with respect to the polycrystalline Si film 31, no mask alignment margin is required between these openings 34 and the polycrystalline Si film 31.

Because of these, the graft base P
^{+ The area of the} impurity layer 17 and the P impurity layer 18 which is the intrinsic base can be reduced, the parasitic capacitance due to the base-collector junction can be reduced, and a bipolar transistor having excellent high frequency characteristics can be manufactured. .

[0013]

However, FIGS.
Also in the second conventional example shown in FIG. 4, since the openings 22 and 34 and the N ⁺ impurity layer 24 cannot be formed in a self-aligned manner with respect to the SiO ₂ film 15, the area of the P ⁺ impurity layer 17 which is a graft base. Cannot be made small enough. Moreover, as is clear from FIG. 24, the side of the P ⁺ impurity layer 17 in the entire circumference of the P ⁺ impurity layer 17 Si
It is in contact with layer 13. For this reason, the parasitic capacitance due to the base-collector junction cannot be sufficiently reduced, and it is difficult to manufacture a bipolar transistor having sufficiently excellent high frequency characteristics.

Further, since the polycrystalline Si film 31 is directly deposited on the Si substrate 14 in the base and emitter forming regions, it is shown in FIG. 22 by dry etching for processing the polycrystalline Si film 31. As described above, the Si substrate 14 in the emitter formation region receives the radiation damage 35.

Further, since the etching selection ratio between the Si substrate 14 and the polycrystalline Si film 31 is approximately 1, the end point of etching with respect to the polycrystalline Si film 31 cannot be detected, and variations in the manufacturing process are taken into consideration. It is necessary to over-etch. For this reason, as shown in FIG.
About 100 nm is also removed.

When the Si substrate 14 in the emitter formation region is damaged by irradiation 35, the leak current increases and the depth of the P impurity layer 18 and the collector length also vary due to fluctuations in the impurity diffusion rate. Moreover, since the P impurity layer 18 is formed after the opening 22 is formed, when the Si substrate 14 in the emitter formation region is shaved, the depth of the P impurity layer 18 and the collector length also vary due to variations in the amount of abrasion. Become.

As a result, the depth of the P impurity layer 18 varies, and the depths of the P impurity layer 18 and the P ⁺ impurity layer 17 are different from each other, so that there are many variations in the base resistance.
There are many variations in collector resistance due to variations in collector length. For these reasons, it has been difficult to manufacture a bipolar transistor having excellent characteristics and less variation in characteristics.

[0018]

According to a first aspect of the present invention, there is provided a method of manufacturing a bipolar transistor, comprising the steps of forming a first insulating film 37 on a semiconductor substrate 14 and leaving at least a portion in an emitter formation region. A step of removing the insulating film 37 to the middle of its film thickness; a step of forming a side wall 42 on at least a side surface of the first insulating film 37 left in the emitter formation region; and a mask of the side wall 42. Then, at least the portion of the first insulating film 37 other than the portion left in the emitter formation region is removed, and at least the relatively high portion 37a in the emitter formation region and the relatively low portion around it. A step of processing the first insulating film 37 into a convex shape in cross section including the portion 37b; and a step of using the first insulating film 37 having a convex cross section as a mask, The step of forming the element isolation region 15 in the body substrate 14, and after the element isolation region 15 is formed, the relatively low portion 37b of the first insulating film 37 is removed to remove the semiconductor substrate 14. After the exposing step and the removal of the relatively low portion 37b, the semiconductor substrate 14 around the relatively high portion 37a is exposed.
Forming a wiring layer for the base lead-out wiring 31 thereon; diffusing impurities from the wiring layer into the semiconductor substrate 14 to form the graft base 17; A second insulating film 52 exposing a relatively high portion 37a, removing the relatively high portion 37a exposed from the second insulating film 52, and the semiconductor substrate 1
4, the step of forming the intrinsic base 18 and the emitter 24 in the region where the relatively high portion 37a is removed.

A method for manufacturing a bipolar transistor according to a second aspect is the method for manufacturing a bipolar transistor according to the first aspect, wherein a region adjacent to a part of the relatively low portion 37b is formed after the element isolation region 15 is formed. Forming a trench 44 in the semiconductor substrate 14,
Filling the trench 44 with a third insulating film 46.

A method for manufacturing a bipolar transistor according to a third aspect is the method for manufacturing a bipolar transistor according to the first or second aspect, wherein a step of forming a fourth insulating film 61 on the semiconductor substrate 14 and the fourth insulating film are included. Forming a fifth insulating film 63 having etching selectivity with respect to at least the surface portion 62 of the film 61 on the fourth insulating film 61, and leaving the fifth insulating film 63 at least in the emitter formation region. Removing the insulating film 63, forming a side wall 42 on at least the side surface of the fifth insulating film 63 left in the emitter formation region, and forming the side wall 42.
Using as a mask, the fourth insulating film 6 except under the fifth insulating film 63 left at least in the emitter formation region.
1 is removed, and at least the fourth and fifth insulating films 61 and 63 in the emitter formation region and the fourth insulating film 61 around the first insulating film 37 have a convex cross section. And a step of forming.

[0021]

In the method of manufacturing the bipolar transistor according to the first aspect, the relatively low portion 37b is formed in a self-aligned manner with respect to the relatively high portion 37a of the first insulating film 37, and the first insulating film 37 is formed. Is used as a mask to form the element isolation region 15 and the emitter 24 is formed in the region corresponding to the relatively high portion 37a, so that the element isolation region 15 and the emitter 24 are formed in self-alignment with each other. Therefore, the area of the graft base 17 formed in the region corresponding to the relatively low portion 37b of the first insulating film 37 can be reduced, and the parasitic capacitance due to the base-collector junction can be reduced. it can.

The base lead wiring 31 is formed around the relatively high portion 37a of the first insulating film 37, the relatively high portion 37a is removed thereafter, and the emitter 24 is formed in the removed region. are doing. In addition, the insulating film 37
With the semiconductor substrate 14, the etching selection ratio can be increased. Therefore, even if the base lead wire 31 is formed, the semiconductor substrate 1 in the emitter formation region is formed.
4. In particular, the emitter-base junction on the surface of the semiconductor substrate 14 is not damaged, and the semiconductor substrate 14 in the emitter formation region is hardly scraped.

In the bipolar transistor manufacturing method of the second aspect, the trench 44 filled with the third insulating film 46 is used.
Is formed adjacent to a part of the relatively low portion 37b of the first insulating film 37, the relatively low portion 37b is formed.
Part of the side surface of the graft base 17 formed in the region corresponding to b is covered with the third insulating film 46 in the trench 44. Therefore, the parasitic capacitance due to the base-collector junction can be further reduced.

In the method of manufacturing the bipolar transistor according to the third aspect, since the fifth insulating film 63 has etching selectivity with respect to at least the surface portion 62 of the fourth insulating film 61, the fourth insulating film is formed. By etching the fifth insulating film 63 using the surface portion 62 of 61 as an etching stopper, the first insulating film 37 having a convex cross section is formed into a laminated film of the fourth and fifth insulating films 61 and 63. Can be stably formed.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention applied to the manufacture of NPN bipolar transistors will be described below with reference to FIGS.
A description will be given with reference to 20. Note that, in the embodiment, the same reference numerals as those of these conventional examples are given to the components corresponding to the first and second conventional examples shown in FIGS.

1 to 10 show the first embodiment.
In the first embodiment, as shown in FIG. 1, a P-type Si substrate 11 is thermally oxidized to form a SiO ₂ film (not shown) on its surface, and this SiO ₂ film is formed by photolithography and etching. The openings are selectively formed. And Si
An antimony glass film (not shown) is deposited on the substrate 11, and Sb is put into the Si substrate 11 from this antimony glass film.
Are diffused to selectively form an N ⁺ buried layer 12 as a buried collector on the surface of the Si substrate 11.

After that, an antimony glass film and SiO ₂
The entire surface of the film is etched to remove them, and the thickness is 1 μm.
Then, the N-type Si layer 13 having a specific resistance of 1 Ω · cm is formed on the Si substrate 11.
Of Si substrate 11 and S
A Si substrate 14 is formed with the i layer 13.

Next, as shown in FIG. 2, the Si substrate 14 is thermally oxidized to form a SiO ₂ film 3 having a film thickness of about 10 nm on the surface thereof.
6 is formed, and the Si ₃ N ₄ film 37 having a film thickness of about 550 nm is formed.
And a SiO ₂ film 41 having a film thickness of about 150 nm are sequentially deposited on the SiO ₂ film 36 by the CVD method. After that, the SiO ₂ film 41 and the Si ₂ film are formed using the photoresist in the shape of the center of the emitter formation region and the collector extraction layer as a mask.
_The 450 nm thick film of the ₃ N ₄ film 37 is continuously etched.

SiO ₂ having a film thickness of about 500 nm
A film 42 is deposited by the CVD method, the entire surface of the SiO ₂ film 42 is etched back, and the SiO ₂ film ₄ is formed on the side surfaces of the SiO ₂ film 41 and the Si ₃ N ₄ film 37 of the etched film thickness.
A side wall consisting of 2 is formed. When etching back the SiO ₂ film 42, conditions are set so that the SiO ₂ film 41 remains with a film thickness of 60 nm or more.

After that, the Si ₃ N ₄ film 37 is etched by using the SiO ₂ films 41 and 42 as a mask, and a high portion of the Si ₃ N ₄ film 37a corresponding to the center part of the emitter formation region and the collector extraction layer and the Si ₃ N ₄ film 37a are formed. Si _{3 in} the lower part of the periphery
N ₄ Si section consisting of a film 37b is in a convex shape ₃ N ₄
The film 37 is processed.

At this time, due to the over-etching, S
The SiO ₂ film 36 except under the i ₃ N ₄ film 37 is also removed.
In addition, using the side wall made of the SiO ₂ film 42 as a mask, Si
_{Since the 3} N ₄ film 37b is formed, this Si ₃ N ₄ film 37b is formed in self-alignment with the Si ₃ N ₄ film 37a.

Then, using the SiO ₂ films 41 and 42 as a mask, the Si substrate 14 is etched to a depth of about 200 nm. This etching is for the recess LOCOS method to be performed later, and it is not necessary to etch the Si substrate 14 unless the recess LOCOS method is performed.

Next, as shown in FIG. 3, the SiO ₂ films 41 and 42 are removed by anisotropic etching to use the Si ₃ N ₄ film 37 as an antioxidant film and the SiO ₂ film 36 as a buffer film. A SiO ₂ film 15 having a thickness of about 400 nm is selectively formed on the surface of the Si substrate 14 by the LOCOS method or the like to form an element isolation region.

Next, as shown in FIG. 4, the SiO ₂ film 15 and the Si ₃ N ₄ film 37 in the portion adjacent to the boundary between the bipolar transistor formation region and the surrounding element isolation region are formed.
The photoresist 43 is processed into a shape that exposes the SiO ₂ film 15, and the SiO ₂ film 15 is anisotropically etched using the photoresist 43 and the Si ₃ N ₄ film 37 as a mask.

After removing the photoresist 43, the Si substrate 14 is anisotropically etched to a depth of about 2 to 3 μm by using the SiO ₂ film 15 and the Si ₃ N ₄ film 37 as a mask, and the trench 44 is formed. To form. In addition, Si ₃ N
_{The fourth} film 37b is formed in self-alignment with the Si ₃ N ₄ film 37a corresponding to the emitter formation region, and the trench 44 is formed in contact with the Si ₃ N ₄ film 37b. It is formed in self-alignment with the emitter formation region.

Next, as shown in FIG. 5, a SiO ₂ film 45 is formed on the surface of the Si substrate 14 in the trench 44 by thermal oxidation, and then a BPSG film 46 is deposited and etched back at a temperature of 400 ° C. With this BPSG film 46, the trench 44 is formed.
Fill in.

Next, as shown in FIG. 6, the formation region of the emitter and base of the bipolar transistor is covered with a photoresist (not shown), and this photoresist is used as a mask to form the Si ₃ N ₄ film in the other regions. Remove 37. Then, this time, a region (other than the emitter and base formation region) of the bipolar transistor is covered with a photoresist (not shown), and this photoresist is used as a mask for S
The i ₃ N ₄ film 37 is etched to a film thickness of about 120 nm.

Then, the SiO ₂ film 36 is subsequently etched to remove S in the region corresponding to the Si ₃ N ₄ film 37b.
The i base 14 is exposed. At this time, the Si ₃ N ₄ film 37a remains in a thickness of about 380 to 430 nm in the emitter formation region. From this state, with the Si ₃ N ₄ film 37 as a mask, an acceleration energy of 60 keV and 1 × 10 ¹⁴ cm
BF ₂ ⁺ is obliquely ion-implanted into the Si substrate 14 at an angle of 45 ° with a dose amount of ⁻² to form a P impurity layer 47 as a link base.

Then, using a photoresist (not shown) as a mask, an acceleration energy of 50 keV and 5 × 10 ^{15 are used.}
cm ^-2 dose and 360 keV acceleration energy and 1
Phos ⁺ is ion-implanted in two steps with a dose amount of × 10 ¹⁴ cm ^-2 to form an N ⁺ impurity layer 16 as a collector extraction layer.

Then, another photoresist (not shown)
Using as a mask, acceleration energy of 360 keV and 3 ×
B ⁺ ions are implanted into the Si substrate 14 at a dose of 10 ¹³ cm ^-2 to form a P impurity layer 51 as a channel stopper for the NMOS transistor. Therefore, if an NMOS transistor is not formed on the Si substrate 14, this P
It is not necessary to form the impurity layer 51.

Next, as shown in FIG. 7, the film thickness is 250 nm.
Polycrystalline Si film 31 is deposited on the entire surface to about 50 keV
BF ₂ ⁺ is ion-implanted into the polycrystalline Si film 31 at an acceleration energy of 5 × 10 ¹⁵ cm ^{−2 and} a dose of 5 × 10 ¹⁵ cm ⁻² ,
Heat treatment is performed at the temperature. As a result, B implanted into the polycrystalline Si film 31 is activated, and the polycrystalline Si film 3 is activated.
B diffuses from 1 to the Si substrate 14 to form a P ⁺ impurity layer 17 as a graft base.

After that, a photoresist (not shown) is applied on the entire surface, and this photoresist and the polycrystalline Si film 31 are etched back under the condition that the etching selection ratio is close to 1. This etch back is performed over the film thickness of 80 nm after the Si ₃ N ₄ film 37 is exposed. Then, the polycrystalline Si film 31 is processed into the shape of the base lead-out wiring by etching using another photoresist (not shown) as a mask.

Next, as shown in FIG. 8, the film thickness is 400 nm.
A SiO ₂ film 52 is deposited on the entire surface by a CVD method, and a photoresist (not shown) is applied to the entire surface of the SiO ₂ film 52. And these photoresist and S
The surface of the Si ₃ N ₄ film 37 is exposed by etching back the iO ₂ film 52 under the condition that the etching selection ratio is close to 1.

Next, as shown in FIG. 9, a Si ₃ N ₄ film 37 is formed.
Is selectively wet-etched to form the opening 22 corresponding to the emitter formation region in the SiO ₂ film 52 and the polycrystalline Si film 31. Then, through the opening 22, Si with an acceleration energy of 60 keV and a dose amount of 3 × 10 ¹³ cm ^-2.
BF ₂ ⁺ is obliquely ion-implanted into the substrate 14 at an angle of 15 ° to form a P impurity layer 18 as an intrinsic base.

After that, SiO ₂ having a film thickness of about 200 nm is formed.
A film 33 is deposited on the entire surface by the CVD method, and the SiO ₂ film 3 is formed.
The entire surface of 3 is etched back to form a side wall made of the SiO ₂ film 33 on the inner side surface of the opening 22 and an opening 34 inside the side wall.

After that, polycrystalline S having a film thickness of about 150 nm is formed.
i film 23 is deposited on the entire surface at a temperature of 620 ° C., and 45 ke
As ⁺ is ion-implanted on the entire surface of the polycrystalline Si film 23 with an acceleration energy of V and a dose amount of 1.5 × 10 ¹⁶ cm ⁻² .
Then, the polycrystalline Si film 23 is etched by using a photoresist (not shown) in the shape of the emitter electrode as a mask.

Next, as shown in FIG. 10, a SiO ₂ film 53 is formed.
And the BPSG film 54 are sequentially deposited by the CVD method,
The BPSG film 54 is reflowed at a temperature of 0 ° C. During this reflow, As is transferred from the polycrystalline Si film 23 to the Si substrate 14.
Diffuse to form an N ⁺ impurity layer 24 as an emitter. The SiO ₂ film 53 is for preventing B from being diffused from the BPSG film 54 to the polycrystalline Si film 23.

Then, by anisotropic etching using a photoresist (not shown) as a mask, openings 25, 26, 55 for N ⁺ impurity layer 16 and polycrystalline Si films 31, 23 are formed.
Are formed on the BPSG film 54 and the SiO ₂ films 53, 52 and 36. Then, a metal film 27 such as an Al alloy film or an Al multilayer film is deposited on the entire surface by sputtering, and the emitter wiring, the base wiring, the collector wiring and the bonding pad (see the figure) are formed by etching using a photoresist (not shown) as a mask. (Not shown) or the like is formed by the metal film 27.

Then, after annealing at a temperature of 400 ° C. in a forming gas, Si having a film thickness of about 1 μm is formed.
_{A 3} N ₄ film 56 is deposited on the entire surface by plasma CVD.
Then, an opening (not shown) for the bonding pad is formed in the Si ₃ N ₄ film 56 by etching using a photoresist (not shown) as a mask to complete this bipolar transistor.

11 to 20 show a second embodiment. Also in this second embodiment, as shown in FIGS.
Until the SiO ₂ film 36 is formed on the surface of the i base 14,
The steps are carried out substantially in the same manner as the first embodiment shown in FIGS.

However, in the second embodiment, thereafter, the Si ₃ N ₄ film 61 having a film thickness of about 350 nm and the film thickness of 15 n are formed.
SiO ₂ film 62 of about m and Si having a film thickness of about 350 nm
₃ N ₄ film 63 and SiO ₂ film 41 with a film thickness of about 200 nm
And are sequentially deposited on the SiO ₂ film 36 by the CVD method. Then, using the photoresist in the shape of the center of the emitter formation region and the collector extraction layer as a mask and the SiO ₂ film 62 as a stopper, the SiO ₂ film 41 and S
The i ₃ N ₄ film 63 is continuously etched.

SiO ₂ having a film thickness of about 500 nm
The film 42 is deposited by the CVD method, and the entire surface of the SiO ₂ film 42 is etched back to form the SiO ₂ film 41 and the Si ₃ N ₄ film.
Sidewalls made of the SiO ₂ film 42 are formed on the side surfaces of the film 63. When etching back the SiO ₂ film 42,
_The conditions are set so that the _two films 41 remain with a film thickness of 150 nm or more. Thereafter, as shown in FIGS. 12 to 20, the steps substantially similar to those of the above-described first embodiment are executed again to complete this bipolar transistor.

In each of the above first and second embodiments, the base lead-out wiring and the emitter electrode are formed of the polycrystalline Si film 31 and the polycrystalline Si film 23, respectively. Alternatively, the emitter electrode may be formed of a polycide film, an amorphous Si film, or the like.

[0054]

According to the method of manufacturing a bipolar transistor of the present invention, the area of the graft base can be made small and the parasitic capacitance due to the base-collector junction can be made small, so that the bipolar transistor having excellent high frequency characteristics can be obtained. Can be manufactured.

Further, since the semiconductor substrate in the emitter formation region, especially the emitter-base junction on the surface of the semiconductor substrate is not damaged, the leak current is small, and the depth of the intrinsic base and the collector length due to the fluctuation of the impurity diffusion rate are reduced. There is little variation. Moreover, since the semiconductor substrate in the emitter formation region is rarely scraped, variations in the depth of the intrinsic base and collector length due to variations in the scraped amount are small.

As a result, variations in base resistance due to variations in the depth of the intrinsic base are small, and variations in collector resistance due to variations in collector length are also small.
Therefore, it is possible to manufacture a bipolar transistor having excellent characteristics and less variation in characteristics.

In the method of manufacturing the bipolar transistor according to the second aspect, a part of the side surface of the graft base is covered with the insulating film in the trench to further reduce the parasitic capacitance due to the base-collector junction. Further excellent bipolar transistors can be manufactured.

In the method for manufacturing a bipolar transistor according to the third aspect, since the insulating film having a convex cross section can be stably formed, the bipolar transistor having excellent high frequency characteristics and little variation in characteristics can be stably formed. It can be manufactured.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a first step of a first embodiment of the present invention.

FIG. 2 is a side sectional view showing a step that follows FIG.

FIG. 3 is a side sectional view showing a step that follows FIG.

FIG. 4 is a side sectional view showing a step that follows FIG.

FIG. 5 is a side sectional view showing a step that follows FIG.

FIG. 6 is a side sectional view showing a step that follows FIG.

7 is a side sectional view showing a step that follows FIG.

8 is a side sectional view showing a step that follows FIG. 7. FIG.

9 is a side sectional view showing a step that follows FIG.

10 is a side sectional view showing a step that follows FIG.

FIG. 11 is a side sectional view showing a first step of the second embodiment of the present invention.

12 is a side sectional view showing a step that follows FIG. 11. FIG.

13 is a side sectional view showing a step that follows FIG.

FIG. 14 is a side sectional view showing a step that follows FIG.

FIG. 15 is a sectional side view showing a step that follows FIG.

16 is a side sectional view showing a step that follows FIG.

FIG. 17 is a side sectional view showing a step that follows FIG.

FIG. 18 is a side sectional view showing a step that follows FIG.

FIG. 19 is a side sectional view showing a step that follows FIG.

FIG. 20 is a side sectional view showing a step that follows FIG.

FIG. 21 is a side sectional view of a bipolar transistor manufactured in a first conventional example of the present invention.

FIG. 22 is a side sectional view showing a first step of the second conventional example of the present invention.

23 is a side sectional view showing a step following FIG. 22. FIG.

FIG. 24 is a side sectional view showing a step that follows FIG. 23.

[Explanation of symbols]

14 Si substrate 15 SiO ₂ film 17 P ⁺ impurity layer 18 P impurity layer 24 N ⁺ impurity layer 31 Polycrystalline Si film 37 Si ₃ N ₄ film 37a Si ₃ N ₄ film 37b Si ₃ N ₄ film 42 SiO ₂ film 44 trench 46 BPSG film 52 SiO ₂ film 61 Si ₃ N ₄ film 62 SiO ₂ film 63 Si ₃ N ₄ film

Claims (3)

[Claims] 1. A step of forming a first insulating film on a semiconductor substrate, a step of removing the first insulating film to a middle of its thickness, leaving at least a portion in an emitter formation region, Forming a sidewall on a side surface of at least a portion of the insulating film left in the emitter formation region; and using the sidewall as a mask, a portion of the first insulating film left in at least the emitter formation region. Removing the portion other than the above, and processing the first insulating film into a convex cross-section having at least a relatively high portion in the emitter formation region and a relatively low portion around the emitter formation region, A step of forming an element isolation region in the semiconductor substrate using the first insulating film having a convex cross section as a mask; and a step of forming the element isolation region and then performing the relative isolation of the first insulating film. A step of removing the lower portion to expose the semiconductor substrate, and a step of forming a wiring layer for a base lead wiring on the semiconductor substrate around the relatively higher portion after removing the relatively lower portion. A step of diffusing impurities from the wiring layer into the semiconductor substrate to form a graft base, and a step of forming a second insulating film that covers the base lead wiring and exposes the relatively high portion. Removing the relatively high portion exposed from the second insulating film, and forming an intrinsic base and an emitter in a region of the semiconductor substrate from which the relatively high portion is removed. And a method for manufacturing a bipolar transistor. 2. A step of forming a trench in the semiconductor substrate in a region adjacent to a part of the relatively low portion after forming the element isolation region, and a step of filling the trench with a third insulating film. The method for manufacturing a bipolar transistor according to claim 1, further comprising: 3. A step of forming a fourth insulating film on the semiconductor substrate, a step of forming a fifth insulating film having etching selectivity with respect to at least a surface portion of the fourth insulating film, A step of forming on the insulating film, a step of removing the fifth insulating film leaving at least a portion in the emitter formation region, and a sidewall on at least a side surface of the fifth insulating film left in the emitter formation region. Forming step, and using the sidewall as a mask, removing at least the fourth insulating film except under the fifth insulating film left in the emitter forming region to remove at least the fourth and the fourth insulating films in the emitter forming region. 3. The bipolar device according to claim 1, further comprising a step of forming the first insulating film having a convex cross section with a fifth insulating film and the surrounding fourth insulating film. To Method of manufacturing a Njisuta.