JPH10233515A - Schottky barrier semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase of VF at forward voltage application while reducing a leakage current at an SBD joint part at reverse voltage application. SOLUTION: The first conductive type semiconductor substrate, the second conductive type diffusion layers arrayed on the semiconductor substrate, and a Schottky barrier metal layer 17 which is brought into contact with the semiconductor substrate and diffusion layer are provided. With the depth from the main surface of the semiconductor substrate assumed as X, the width of diffusion layer is maximum value Lpmax in X<=0.4μm. Since the width Lpn of the second conductive type diffusion layer near the surface can be narrower and the maximum width Lpnmax of the diffusion layer at depth 0.4μm or deeper can be wider, the reverse direction leakage current at an SBD joint part when a reverse voltage is applied is less while the effective area of the SBD joint part is increased, so that a forward direction voltage drop VF at application of forward voltage is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky barrier semiconductor device in which a PN junction and a Schottky barrier diode (hereinafter referred to as SBD) junction are mixed and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, by mixing a PN junction and an SBD junction, a so-called JB, which is a high-speed diode having a small reverse current, a high withstand voltage and a low forward voltage, has been developed.
S (Junction Barrier Controlled Schottky Rectifie
r) is known. SP with further improved characteristics
IN diode and MPS (Merged PIN Scho
ttky Rectifier) is being researched. These are advantageous in that a space charge region (hereinafter, referred to as a depletion layer) extending around a plurality of P ⁺ regions formed in the bulk is easily electrically connected to each other at a low voltage, that is, punch-through is facilitated. The voltage applied to the metal layer is reduced to reduce the leak current.

FIG. 10 shows a cross-sectional structure of the PIN and SBD portions of a conventional MPS. A plurality of P ⁺ regions 15 having a bowl-shaped cross section are arranged in the surface layer of the N ⁻ region 1, and a Schottky barrier metal layer 17 that makes low resistance contact with the P ⁺ region 15 is formed on these surfaces. I have. In the figure, each P
The boundary between the ⁺ region 15 and the N ⁻ region 1 is a PN junction, and the boundary between the P ⁺ regions 15 where the N ⁻ region 1 and the Schottky barrier metal layer 17 are in contact corresponds to the SBD junction.

When a reverse voltage is applied to the MPS in which the PN junction and the SBD junction coexist in such a manner that the Schottky barrier metal layer 17 has a negative potential and the N ⁻ region 1 has a positive potential, as shown by a broken line, N ^- region 1 from junction
Depletion layer 19 spreads over the depletion layer 1 around each P ⁺ region 15.
9 are combined.

Due to the coupling between the depletion layers 19, the SBD
The junction is pinched off and the Schottky barrier metal layer 1
7 is prevented from increasing, and the leakage current generated at the SBD junction is suppressed low.

[0006]

In the conventional Schottky barrier semiconductor device in which the PN junction and the SBD junction are mixed as described above, in order to further reduce the leakage current at the SBD junction, adjacent P ⁺ Interval L of region 15
Preferably, the SBD junction is pinched off by narrowing the SBD and coupling the depletion layers 19 extending around each P ⁺ region 15 with a lower reverse voltage.

However, as can be seen from FIG. 10, since the cross-sectional shape of the conventional P ⁺ region 15 is bowl-shaped, the width Lpn in the coupling direction (left-right direction in the drawing) is near the surface (depth of 0. 0).
1 μm to 0.3 μm). Therefore, LSB
When D is reduced, the effective area of the SBD junction in the entire semiconductor device decreases. Therefore, when a forward voltage is applied, the forward voltage drop VF increases, and high-speed operation is impaired.

The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a Schottky barrier semiconductor device in which a PN junction and an SBD junction are mixed, in order to reduce the VF when a forward voltage is applied. An object of the present invention is to reduce the leakage current at the SBD junction when a reverse voltage is applied without increasing the voltage.

[0009]

A first feature of the Schottky barrier semiconductor device of the present invention is that a semiconductor substrate of a first conductivity type, a plurality of diffusion layers of a second conductivity type arranged on the semiconductor substrate, When the semiconductor substrate and the Schottky barrier metal layer in contact with the diffusion layer are provided, and a depth from the main surface of the semiconductor substrate is defined as X, when X ≧ 0.4 μm, the width of the diffusion layer is a maximum value. Lpnmax.

According to the first feature, the maximum width Lpnmax of the diffusion layer of the second conductivity type is formed at a position deeper than the conventional one, that is, at a position at least 0.4 μm deeper than the main surface of the substrate. Therefore, SBD due to depletion layer coupling generated when a reverse voltage is applied
The pinch-off of the junction also occurs at a depth of 0.4 μm or more. In this structure, if the width Lpn of the diffusion layer of the second conductivity type near the substrate surface is narrowed and the maximum width Lpnmax of the diffusion layer at a depth of 0.4 μm or more is widened, the SBD junction at the time of applying a reverse voltage is formed. In addition to reducing the reverse leakage current, the SBD
It is also possible to increase the effective area of the junction and reduce the forward voltage drop VF when a forward voltage is applied.

According to a second feature of the Schottky barrier semiconductor device of the present invention, in the semiconductor device having the above-mentioned first feature, the diffusion layer is formed by forming a region having a width of Lpnmax by a predetermined thickness in a depth direction. That is what we have.

As described in the second feature, the region of the diffusion layer having the maximum width Lpnmax formed in the deep region of the substrate only needs to have a certain thickness or more. It may be narrow.

A third feature of the Schottky barrier semiconductor device of the present invention is that in the semiconductor device having the first feature, a cross-sectional shape of the diffusion layer taken in a direction perpendicular to a main surface of the semiconductor substrate. Is a polygonal shape.

A fourth feature of the Schottky barrier semiconductor device of the present invention is that, in the semiconductor device having the first feature, the diffusion layer has a sectional shape taken in a direction perpendicular to a main surface of the semiconductor substrate. In a pot shape.

As shown in the third or fourth feature,
If the cross-sectional shape of the diffusion layer is pot-shaped or polygonal,
The diffusion layer has a cross-sectional shape having a narrow width Lpn near the substrate surface and a maximum width Lpnmax in a deep region, reduces a reverse leakage current of the SBD junction when a reverse voltage is applied, and reduces an effective area of the SBD junction. And the forward voltage drop VF when a forward voltage is applied can be reduced, and a Schottky barrier semiconductor having the above-described first feature and operation can be provided.

A first feature of the method of manufacturing a Schottky barrier semiconductor device according to the present invention is that a first conductive type semiconductor substrate is provided with a plurality of second conductive type first substrates having a width equal to or more than a predetermined value.
Forming a second diffusion layer of the second conductivity type having a width equal to or less than the predetermined value on the first diffusion layer so as to be connected to the first diffusion layer. Process.

According to the first feature of the manufacturing method of the present invention, a diffusion layer of a second conductivity type having a narrow width in a shallow region and a maximum width in a deep region is provided in a semiconductor substrate of the first conductivity type. Can be formed. In a Schottky barrier semiconductor device having a diffusion layer having such a structure, the width of the diffusion layer is small in a shallow region of the substrate. Therefore, the reverse voltage can be reduced at a relatively deep position of the substrate without reducing the effective area of the SBD junction. The depletion layer can be coupled at the time of application and pinch-off of the SBD junction can be caused. Therefore, the reverse leakage current at the SBD junction when the reverse voltage is applied can be reduced without increasing the forward voltage drop VF when the forward voltage is applied.

According to a second feature of the method of manufacturing a Schottky barrier semiconductor device of the present invention, in the manufacturing method having the above-mentioned first feature, the first diffusion layer and the second diffusion layer are formed by ion acceleration. It is formed by two or more ion implantation steps having different energies.

According to the second feature of the above-mentioned manufacturing method, two or more ion implantation steps are performed by changing the ion acceleration energy which greatly affects the width and depth of the diffusion layer. The manufacturing method can be easily realized.

A third feature of the method of manufacturing a Schottky barrier semiconductor device according to the present invention is that, in the manufacturing method having the first feature, the first diffusion layer and the second diffusion layer are formed of the semiconductor. It is formed by two or more ion implantation steps at different angles with respect to a direction perpendicular to the main surface of the substrate.

According to the third feature of the manufacturing method, since the position of the region where the implanted ions reach can be changed by changing the implantation angle at the time of ion implantation, the cross-sectional shape of the diffusion region can be changed to a pot-like shape or a multiple shape. It can be various shapes such as square,
The manufacturing method having the first feature can be easily realized.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1A is a plan view of a Schottky barrier semiconductor device according to a first embodiment of the present invention. FIG. 1 (b) is a cross-sectional view of FIG.
It is sectional drawing seen along A '.

As shown in FIG. 1A, a Schottky barrier metal layer 17 is formed on the surface of the semiconductor device, and an N ⁻ layer below this Schottky barrier metal layer 17 is formed.
A plurality of P ⁺ regions 15 are formed in a stripe shape on the surface layer of region 1. The central region of each P ⁺ region 15 which is conveniently hatched indicates an upper layer portion directly in contact with Schottky barrier metal layer 17.

Looking at a cross-sectional view along AA ', FIG.
As in (b), P ⁺ region 15, than the width Lpn of the upper portion in contact with the Schottky barrier metal layer 17, the width Lpn of the bottom of the P + region 15 has become a long shape, the maximum width Lpnmax Is at the bottom. Maximum width L in P ⁺ region 15
The region having pnmax is formed below the depth Ld from the main surface of the substrate.

The specific scale is based on desired characteristics (withstand voltage,
Operating speed, IR, etc.). For example, in the first embodiment, the depth Ld is 1 μm, the width Lpn of the upper P ⁺ region 15 is 0.7 μm, and the LSBD is 2.5 μm.
And can be designed. Ld is preferably at least 0.4 μm or more.

As described above, the width Lpn of the P ⁺ region 15 is reduced in the shallow region and widened in the deep region. In particular, the maximum width Lpnmax of the P ⁺ region 15 is formed at a depth of 0.4 μm or more. For example, when a reverse potential is applied, coupling of the depletion layer 19 formed around the P ⁺ region 15 occurs in a deeper portion of the N ⁻ region 1 than in the conventional case. If the maximum width Lpnmax is increased, the depletion layer 1
9 occurs at a lower voltage, pinch-off of the SBD junction becomes possible, and the reverse leakage current can be reduced. In the vicinity of the substrate surface, the width Lp of the P ⁺ region 15
Since n is small, the effective area of the SBD joint can be relatively widened. Therefore, the current density at the time of forward voltage application decreases,
The forward voltage drop VF can be reduced.

FIGS. 2A and 2B are plan views of the applied pattern of FIG. 1A. FIG. 1A shows the P ⁺ region 1
Although the example in which the plane shape of 5 is a stripe shape is illustrated, the plane shape of the P ⁺ region 15 may be rectangular as shown in FIGS. 2 (a) and 2 (b). Also in this case,
P ⁺ region 15 in contact with Schottky barrier metal layer 17
May be formed in a strip shape as shown in FIG. 2A or a rectangular shape in the center of the P ⁺ region 15 as shown in FIG. 2B.

Next, a method of manufacturing the Schottky barrier semiconductor device according to the first embodiment will be described with reference to the drawings. 3A to 3D are cross-sectional views illustrating a method for manufacturing the Schottky barrier semiconductor device according to the first embodiment.

First, a P ⁺ region 15 having a width Lpnmax is formed at a predetermined interval in the N ^- region 1. That is, first, a resist film is applied and formed on the surface of the N ⁻ region 1, and is patterned to obtain a resist pattern 5. P-type impurities are ion-implanted using the resist pattern 5 as a mask to form an N ⁻ region. ion implantation layer underlying the P ⁺ region 15 in one of the surface layer to form a P ⁺ region 15a (Figure 3 (a)).
Unnecessary resist pattern 5 is thereafter removed.

Next, the same layer 1 'as that of the N ^- region 1 is epitaxially grown on the surface (FIG. 3B). By this step, P ⁺ region 15a is substantially buried in N ⁻ region 1.

In a region corresponding to P ⁺ region 15a on the surface of N ^- region 1, a resist pattern 5 having an opening having a width Lpn smaller than the width of P ⁺ region 15a is formed. Using this resist pattern 5 as a mask, a second ion implantation of a P-type impurity is performed to form a P ⁺ region 15b. The injection conditions are
The newly formed P ⁺ region 15b is formed by the P ⁺ formed in the previous process.
The condition is such that it is in contact with the area 15a (FIG. 3
(C)). The unnecessary resist pattern 5 is thereafter removed.

Further, annealing is performed to form a P ⁺ region 15a.
And 15b are activated to form a P ⁺ region 1 which is a continuous diffusion layer.
5 is formed (FIG. 3D). Thereafter, if a Schottky barrier metal layer 17 is formed on the surface, the Schottky barrier semiconductor device shown in FIG. 1B can be obtained.

One or both of the two ion implantation steps shown in FIGS. 3A and 3C are replaced with a step of forming a trench and a step of forming a buried layer in the trench. Thus, a similar Schottky barrier semiconductor device can be obtained. FIGS. 4A to 4C are process diagrams showing an example. Hereinafter, this step will be briefly described.

The first ion implantation is performed, the P ⁺ region 15a having the width Lpnmax is formed in the surface layer of the N ⁻ region 1, and the same epitaxial layer as the N ⁻ region is formed on the surface. The same method can be used. Thereafter, N ^- region 1 to form a resist pattern on the surface, this N as a mask ^- etched regions 1, forming a trench having a slightly narrower width than the width Lpn on a region corresponding to the central P ⁺ region 15a I do. The unnecessary resist is thereafter removed (FIG. 4A).

Next, a second ion implantation is performed without using a mask to form a P ⁺ region 15b in the surface layer of the N ⁻ region 1. The implantation condition is selected so that the P ⁺ region 15b is in contact with the P ⁺ region 15a. Thereafter, annealing is performed to activate the ion-implanted layer, so that the P ⁺ region 15a and the P ⁺ region 15b become continuous P ⁺ regions 15 (FIG. 4B).

Before or after annealing, the P ⁺ region 15b on the SBD formation region is removed by etching. Finally, a Schottky barrier metal 17 is formed on the substrate surface (FIG. 4C).

FIG. 4C shows the state of the depletion layer 19 when a reverse potential is applied to the Schottky barrier semiconductor device manufactured by the above-described method. As in the case of the Schottky barrier semiconductor device shown in FIG. 1B, the coupling of the depletion layer 19 formed around the P ⁺ region 15 occurs in a deep portion of the N ⁻ region 1, where the SBD junction is pinched off. it can. Since the width of the P ⁺ region 15 near the substrate surface is small, the effective area of the SBD junction can be relatively widened. Therefore, by applying a reverse voltage of a lower voltage than in the prior art, pinch-off of the SBD junction due to the coupling of the depletion layer is enabled, the reverse leakage current can be reduced, and the forward voltage drop VF when a forward voltage is applied is reduced. You can also.

(Second Embodiment) Next, FIGS.
A second embodiment will be described with reference to FIG.

[0040] Figure 5 and 6 showing cross-sectional process for explaining the second embodiment, FIG. 7 is an impurity ion B ⁺ N ^- region 1
6 is a logarithmic graph showing the relationship between the acceleration energy and the stop position of implanted ions when implanted in FIG.

First, as shown in FIG. 5A, an SiO ₂ layer 3 having a thickness of about 0.1 μm is formed on the surface of the N ⁻ region 1. Further, a resist film is formed on the surface, and the resist film is patterned so as to have a width of 2 μm at intervals of 2 μm. Using this resist pattern 5 as a mask, a B ⁺ impurity ion having a dose of 1 × 10 ¹⁶ cm ⁻² is implanted at an acceleration energy of 300 KeV and an implantation angle θ with respect to a vertical line viewed from the surface.
At 0 to 6 °. The stop position 9 of the implanted ions under this condition obtained from FIG. 7 is a position at a depth of about 0.71 μm from the main surface of the substrate.

Next, as shown in FIG. 5B, using the same resist pattern 5 as a mask, a dose of 1 × 10
¹⁵ cm ^-2 B ⁺ impurity ions are accelerated at an energy of 40
The implantation is performed under the conditions of KeV and an implantation angle θ of 0 to 6 °.
The stop position 13 due to this is approximately 0.13 in depth from FIG.
μm.

As shown in FIG. 5C, the unnecessary resist is removed, and then 900 ° C. is activated for activating B ^+.
As described above, the annealing treatment is preferably performed at 1000 ° C. for 30 minutes or more to form the P ⁺ region 15. The P ⁺ thus obtained
The region 15 has a maximum depth of about 1.2 μm, and has a pot-shaped cross-sectional shape having a maximum width Lpnmax of about 2.8 μm at a depth of 0.71 μm from the surface.

After arranging a plurality of pot-shaped P ⁺ regions 15 inside the surface of N ^- region 1 as described above, the SiO ₂ film 3 is removed, and a Schottky barrier metal layer which makes low resistance contact with P ⁺ region 15 is formed. 17 is formed on the surface. The Schottky barrier metal layer 17 is made of Al, Mo, Au, Ti, N
It is composed of a single layer containing i, V, etc., but may be composed of multiple layers. Through the above steps, a Schottky barrier semiconductor device in which a PN junction and an SBD junction are mixed as shown in FIG. 6 is realized.

As shown in FIG. 6, according to the Schottky barrier semiconductor device of the second embodiment, the width of the cross section of the P ⁺ region 15 in the coupling direction (the left-right direction in the drawing) has a depth of 0.1 mm. When the reverse voltage is applied as shown in the figure, the depletion layer 19 extending from each P ⁺ region 15 is coupled to pinch off the SBD junction when the reverse voltage is applied as shown in the figure.

FIG. 8 shows current-voltage characteristics (IR-VR) of the Schottky barrier semiconductor device according to the second embodiment and the conventional Schottky barrier semiconductor device shown in FIG.
6 is a graph comparing characteristics (Ta = 25 ° C.). Both values are for the case where chips of the same size are used. In the figure, the white circles are the IR-VR characteristics of the Schottky barrier semiconductor device according to the second embodiment, and the black circles are those according to the prior art. In the conventional Schottky barrier semiconductor device, pinch-off occurs when VR is about 0.5 V (in FIG.
(Marked), and the leak current IR does not increase. On the other hand, in the second embodiment, the pinch-off occurs when VR is about 0.2 V.

As described above, the Schottky barrier semiconductor device according to the second embodiment has a clearly lower leak current IR than the conventional device. VR = 10
Comparing the IR at V, it is 4.5 in the conventional semiconductor device.
In contrast to μA, in the second embodiment, 1.A.
5 μA, which is reduced to 1/3.

On the other hand, the LSBD at the SBD junction can have the same size as the conventional one, so that the VF when the forward voltage is applied can be made substantially the same. Comparing the VF at 100 μA, the conventional semiconductor device is 0.11 V,
The voltage according to the second embodiment is 0.12V.

(Third Embodiment) FIG. 9 is a sectional structural view for explaining a third embodiment of the present invention. The difference from the second embodiment is that, during the two ion implantation steps, the implantation angle θ is changed once from + 30 ° to the perpendicular, and −3.
Once from 0 °, B ⁺ impurity ions with a dose of 1 × 10 ¹⁶ cm ⁻² are implanted at an acceleration energy of 300 KeV in both cases, and the subsequent steps are the same as in the second embodiment.

As shown in FIG. 9, according to the third embodiment, the line between the implantation ion stop position 9 in the first ion implantation step and the implantation ion stop position 13 in the second ion implantation step is shown. , Becomes oblique depending on the implantation angle, and as a result, the sectional structure of the P ⁺ region 15 becomes a star-shaped polygonal shape as shown in FIG. P ⁺ region 15 has a depth of 0.5 μm
At this point, Lpnmax is obtained, and the width of Lpnmax is about 12% longer than in the second embodiment, so that the pinch-off effect can be further enhanced.

As described above, the Schottky barrier semiconductor device of the present invention has been described in accordance with the embodiments. However, the present invention is not limited to these, and the cross-sectional width Lpn is 0.4 μm or more from the surface. What is necessary is that the P ⁺ region 15 having the maximum cross-sectional structure be formed. For example, the number of times of ion implantation for forming the P ⁺ region 15 may be three or more. Further, the implantation angle at the time of ion implantation is not limited to the above-described angle, and various angles from + 60 ° to −60 ° can be combined. Further, P ⁺ region 1
The cross-sectional shape of 5 is not limited to a pot shape, a star shape, etc.
Various polygonal shapes can be taken.

[0052]

As described above, according to the Schottky barrier semiconductor device of the present invention, a semiconductor substrate of a first conductivity type, a diffusion layer of a second conductivity type arranged in a plurality on the semiconductor substrate, the semiconductor substrate and The semiconductor device has a Schottky barrier metal layer in contact with the diffusion layer, and when the depth from the main surface of the semiconductor substrate is defined as X, the width of the diffusion layer takes a maximum value Lpmax when X ≧ 0.4 μm. Therefore, since the effective area of the SBD junction does not decrease, it is possible to prevent an increase in VF when a forward voltage is applied, and it is possible to pinch off the SBD junction by a depletion layer by applying a lower reverse voltage. Directional leakage current can be further reduced.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view of a Schottky barrier semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the Schottky barrier semiconductor device according to the first embodiment of the present invention, showing an application pattern example of the device.

3A to 3C are cross-sectional views of the Schottky barrier semiconductor device according to the first embodiment of the present invention in respective steps for explaining the method of manufacturing the device.

FIGS. 4A to 4C are cross-sectional views of the Schottky barrier semiconductor device according to the first embodiment of the present invention in respective steps for describing an example of the device.

FIGS. 5A to 5C are cross-sectional views of a Schottky barrier semiconductor device according to a second embodiment of the present invention in respective steps for describing a method of manufacturing the device.

FIG. 6 is a sectional view of a Schottky barrier semiconductor device according to a second embodiment of the present invention.

FIG. 7 shows acceleration energy and B ⁺ in the ion implantation process.
6 is a logarithmic graph showing the relationship between the ion and the implantation stop position in the bulk.

FIG. 8 is a graph showing IR-VR characteristics of the Schottky barrier semiconductor device according to the second embodiment and a conventional device.

FIG. 9 is a sectional view of a Schottky barrier semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a cross-sectional view of a conventional Schottky barrier semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 N ⁻ region 3 SiO ₂ film 5 resist pattern 9, 13 Stopped position of implanted ions 15 P ⁺ region 17 Schottky barrier metal layer 19 depletion layer

Claims (7)

[Claims] A semiconductor substrate of a first conductivity type; a plurality of diffusion layers of a second conductivity type arranged on the semiconductor substrate; and a Schottky barrier metal layer in contact with the semiconductor substrate and the diffusion layer. Assuming that the depth from the main surface of the semiconductor substrate is X, when X ≧ 0.4 μm, the width of the diffusion layer is the maximum value Lpn
A Schottky barrier semiconductor device having a maximum value. 2. The Schottky barrier semiconductor device according to claim 1, wherein the diffusion layer has a region having a width of Lpnmax having a predetermined thickness or more in a depth direction. 3. The Schottky barrier semiconductor device according to claim 1, wherein the diffusion layer has a polygonal cross section taken in a direction perpendicular to the main surface of the semiconductor substrate. 4. The Schottky barrier semiconductor device according to claim 1, wherein the diffusion layer has a pot-like cross section taken in a direction perpendicular to a main surface of the semiconductor substrate. 5. A step of forming a plurality of first diffusion layers of a second conductivity type having a width equal to or more than a predetermined value on a semiconductor substrate of the first conductivity type, and a step of connecting to the first diffusion layers. Forming a second diffusion layer of a second conductivity type having a width equal to or less than the predetermined value on the first diffusion layer. 6. The Schottky barrier semiconductor according to claim 5, wherein the first diffusion layer and the second diffusion layer are formed by two or more ion implantation processes having different ion acceleration energies. Device manufacturing method. 7. The semiconductor device according to claim 1, wherein the first diffusion layer and the second diffusion layer are formed by two or more ion implantation steps at different angles with respect to a direction perpendicular to a main surface of the semiconductor substrate. A method for manufacturing a Schottky barrier semiconductor device.