JPS60241249A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the titled device with a surface MOS type capacitor connected to a buried diffused layer in a short time with a small area by a method wherein a hole deep enough to reach the buried diffused layer is bored previously from the surface of the epitaxial grown layer, and diffusion is carried out via said hole. CONSTITUTION:A diffusion mask layer 4 having an aperture serving as the diffusion window is formed above the buried diffused layer 2, and an etching hole 9 is bored to the degree of reaching the diffused layer 2 from this aperture. Next, an impurity-mixed layer 10 is formed. The impurity of the layer 10 diffuses into the epitaxial layer 3 by heat-treatment and formed into an impurity diffused layer 5A. Then, the impurity-mixed layer 10 in the surface is etched over the whole, and the diffusion mask layer 4 is removed by etching. Finally, a gate dielectric layer 6 is formed by thermal oxidation, and a gate electrode layer 8 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, particularly an MO8 type capacitor used in a MO8m memory device.

[Prior art]

Conventionally, there have been devices of this type as shown in FIGS. 1(a) to 1(d). In FIG. 1, 1 is a semiconductor substrate such as silicon, 2 is a buried diffusion layer, 3 is an epitaxial growth layer, 4 is a diffusion mask layer such as an oxide film, 5 is a diffusion layer, 6 is a gate dielectric layer, and 7 is a field oxidation layer. The film 8 is a gate electrode layer.

Next, the structure of a conventional MO8 type capacitor will be explained. After forming a buried diffusion layer 2 in a predetermined shape in a semiconductor substrate 1 as shown in FIG. 1(a), an epitaxial growth layer 3 is formed. Next, as shown in FIG. 1(b), a diffusion mask layer 4, such as a silicon oxide film, is formed using a conventional planar diffusion technique, and an opening serving as a diffusion window is formed in a portion of the diffusion mask layer 4. Then, as shown in FIG. 1(C), impurities (when the semiconductor substrate 1 is p-type, p-type phosphorus, arsenic,
When the conductive substrate 1 is p-type, at least the p-type boron) is diffused I? Thermal diffusion is performed to a depth greater than that at which the tip of 45 reaches the buried diffusion layer 2. After that, the diffusion mask Jf&
After removing the field oxide film 1.4 by etching, the field oxide film 1.4 is removed according to a normal MOS process as shown in FIG. After forming the gate layer 6, a gate layer 8 is formed to form an MO8 type capacitor. The capacitance of this MO8 type capacitor is mainly due to the epitaxial growth layer 3.
and the MO8 capacitance between the gate electrode layer 8 and the buried diffusion layer 2
Needless to say, it is the sum of the junction capacitance between and the half-core substrate 10 (・.

As mentioned above, the conventional MO8 type capacitor is diffused 1+45
Since it is configured to connect the MUSm capacitor and the buried diffusion layer 2, it takes a very long time to diffuse to the bottom of the epitaxial growth layer 3, which is usually 5 to 10 μm, and the diffusion layer 5 is Since the pattern size also expands to more than twice the thickness of the epitaxially grown layer 3, it has a fatal drawback that it cannot be used for an integrated MOS memory due to the small pattern size.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above. Prior to diffusion, a hole is made in advance from the surface of the epitaxial growth layer to the extent that it reaches the buried diffusion layer. The object of the present invention is to provide a semiconductor device in which a buried diffusion layer and a surface MO8 type capacitor are connected in a short time and in a small occupied area by diffusion through the oxide layer. An embodiment of the present invention will be explained below with reference to drawing 9.

[Embodiments of the invention]

FIGS. 2(a) to 2(e) are cross-sectional views of the manufacturing process for explaining one embodiment of the present invention, in which 9 is a pre-formed etching hole, 10 is polysilicon or Sin mixed with impurities; and Si3N (hereinafter referred to as an impurity-mixed layer), 5A is an impurity diffusion layer diffused from this impurity-mixed layer 10.

The device of the present invention can be made, for example, as follows. Figure 2(a) is almost the same as Figure 1(b),
A diffusion mask layer 4 having an opening serving as a diffusion window has been formed above the buried diffusion layer 2. This opening is then etched by anisotropic plasma etching (which can be done using C2C12F4 or CCI gas) as shown in Figure 2 (b).
), an etching hole 9 is made to reach the buried diffusion layer 2.

Next, as shown in Figure 2 (C), excessive impurities (impurity J
For example, CV
When formed by the porDeposition method and subjected to heat treatment, the impurities in the impurity doped layer 10 are also diffused into the epitaxial growth layer 3, forming impurity diffusion JH5A on the surface of the etching hole 90. Next, the impurity-containing layer 10 on the surface is etched by an appropriate amount over the entire surface, and the diffusion mask layer 4 is also etched away, thereby easily obtaining the structure shown in FIG. 2(d). Thereafter, a gate dielectric layer 6 is formed by, for example, a thermal oxidation method, and a gate electrode layer 8 is formed in the same manner as in the conventional method, thereby completing an MO8 type capacitor as shown in FIG. 2(e).

In the MO8 type capacitor according to the present invention, the upper MO8 structure and the internal buried diffusion N are connected via the impurity diffusion layer 5A.
2 are electrically connected, the basic operation is exactly the same as the conventional method, but in this invention, holes for diffusion are made by etching, so long-term diffusion as in the conventional method is not necessary. Even using current lithography technology, a buried diffusion layer 2 with an occupied area of 2 μm or less and a depth of 5 μm or more can be created.
Large-scale MO of 1Mbit class or more
It is also easily applicable to S memory.

In the above embodiment, the case was described in which the impurity diffusion Ji 5 A was formed using the solid diffusion of the impurity in which the impurity-diffusion Ji 5 A was contained in the impurity-mixed RF41G. It goes without saying that the same effect can be obtained by first diffusing impurities into the circumferential surface of the etching hole 90 by vapor phase diffusion to form the impurity diffusion layer 5A. Furthermore, if the formation of the impurity diffusion layer 5 is completed after forming the etching hole 9 in this way, the gate electric layer 6 is formed before filling the hole with the impurity mixed layer 10 as shown in FIG. The side trap of etching hole 9 is also MO.
Even if eight structures are formed, the same effects as in the above embodiment can be obtained.

[Effects of the Invention] As explained above, this invention connects the surface MO8 structure and the buried diffusion layer after forming the etching holes in the epitaxial growth layer. This has the advantage that an 8-member MO8 type capacitor can be constructed.

44. Brief description of the drawings FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process for explaining a conventional semiconductor device, and FIGS. 2(a) to (e) are one embodiment of the present invention. FIG. 3 is a cross-sectional view showing a manufacturing process for explaining a semiconductor device according to an example, and FIG. 3 is a cross-sectional view of a semiconductor device showing another embodiment of the present invention.

In the figure, 1 is a semiconductor substrate, 2 is a buried diffusion layer, 3 is an epitaxial growth layer, 5A is an impurity diffusion layer, 6 is a gate dielectric layer, 8 is a gate dielectric layer, 9 is an etching hole, and 10 is an impurity mixed layer. be.

Note that the same symbols in the figures indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1 (a) (b) Figure 1 (c) and others (d) Figure 2 (a) (b) Figure 2 (c) 0 (cl) 0 Figure 2 (e) Figure 3

Claims (1)

[Claims] In an MO8 type capacitor having a buried diffusion layer and an epitaxial growth layer on a semiconductor substrate, an etching hole is formed in the epitaxial growth layer to reach the buried diffusion layer, and then a trapping impurity diffusion layer is formed around the etched hole. A semiconductor device characterized in that an MO8 type capacitor is constructed by forming an impurity doped layer directly or via a gate dielectric layer on the impurity diffusion layer, connected to the buried diffusion node.