JPS63244762A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the generation of leak currents by a method wherein a single-crystal semiconductor layer, higher in impurity concentration than and same in conductivity type as a semiconductor substrate, is formed on the surface of a groove formed in the semiconductor substrate and, on said single-crystal semiconductor layer, an impurity layer opposite in conductivity type to said semiconductor substrate and an insulating film are formed in that order. CONSTITUTION:An element-isolating region 22 is formed on a p-type semiconductor substrate 21 and, on the two, an insulating film 23 is formed. Next, with a patterned resist 24 serving as a mask, the insulating film 23 is subjected to etching for the exposure of the semiconductor substrate 21. The resist 24 is removed, and then a groove 25 is formed, with the insulating film 23 serving as a mask. A process follows wherein a single-crystal semiconductor layer 26 is formed, same as the semiconductor substrate 21 in conductivity type and higher than the same in impurity concentration, on the surface of the groove 25. A single-crystal semiconductor layer 27 is formed, opposite to the semiconductor substrate 21 in conductivity type, on the single-crystal semiconductor layer 26. The insulating film 23 is removed, an n<->-layer 28 is formed on the surface region of the semiconductor substrate 21, a gate insulating film 29 is formed on the single-crystal semiconductor layer 27 and n<->-layer 28, and then a capacitor electrode 30 is built on the insulating film 29 and element-isolating region 22. In this way, inter-capacitor leak currents and soft errors may be prevented with ease.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a semiconductor device and a method for manufacturing the same, and in particular, a semiconductor Ift suitable for a trench type capacitor and a method for manufacturing the same, and a method for manufacturing the same. Regarding.

(Prior art) In recent years, with the increasing integration of semiconductor integrated circuits, various attempts have been made to reduce the dimensions of semiconductor elements.
S capacitors are no exception.

As a MOS capacitor in which the amount of stored charge is increased without increasing the chip area, a trench type capacitor as shown in FIG. 4, for example, is known.

In the figure, 11 is a P-type semiconductor substrate.

Reference numeral 12 denotes an element isolation region formed on this semiconductor substrate 11. Grooves 13 are formed on the substrate surface on both sides of this element isolation region 12.
is formed. On the inner surface of this groove 13 and on the substrate 11, an n-layer 14 is formed. Also, n one layer 14
An insulating film 15 is formed on top of the insulating film 15 . This insulating film 1
5 and the element isolation region 12, a capacitor electrode 16 made of polycrystalline silicon is formed so as to fill the groove 13.

In the above configuration, the n-layer 14 and the capacitor electrode 16
A trench capacitor is formed having the opposite electrode as the opposing electrode. In the diagram,
Two trench capacitors 171 and 172 formed on both sides of the element isolation region 12 are shown.

By the way, the trench type capacitor 171.1 having such a configuration
In 72, by appropriately setting the depth and shape of the groove 13, the effective area of the groove capacitors 171 and 172 can be arbitrarily selected. Thereby, the amount of accumulated charge in the trench capacitors 171 and 172 can be set appropriately, and it is possible to obtain a large amount of accumulated charge without increasing the chip area.

However, in the case of the above configuration, the trench capacitors 171.17
2, the adjacent trench capacitor 171
, 172. This leakage current includes a leakage current flowing directly under the element isolation region 12 and a bunch-through current due to the extension of the n-[114 depletion layer.

Therefore, in order to prevent the occurrence of the leakage current, it is necessary to prevent the two types of currents described above. Methods for preventing punch-through current include increasing the substrate concentration and adding 10
A method of forming a single layer of P with a diameter of about 7α°3 is conceivable.

However, the method of increasing the impurity concentration of the substrate 11 is
This is not practical because it causes deterioration of the characteristics of the transistor.

Furthermore, the method of providing a P'' layer with a concentration of about 101 cm-3 inside the substrate 11 is technically difficult and therefore impractical.

Therefore, a method of increasing the distance between the trench capacitors 171 and 172 can be considered, but this method goes against the trend of increasing density and cannot be adopted.

In addition to this, there is also a trench type capacitor 171 having the configuration shown in FIG.
172 is a barrier layer (for example, P″
Since there is no layer), there is a problem in that soft errors are likely to occur.

(Problems to be Solved by the Invention) As described above, in trench capacitors used as MOS capacitors, conventionally, as the density increases, leakage current occurs between capacitors, and soft errors occur. The problem was that it was easy.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can easily prevent leakage current between capacitors and soft errors in a trench type capacitor.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a structure in which a conductive material having the same conductivity type as the semiconductor substrate and having a higher conductivity than the semiconductor substrate is provided on the inner surface of a groove formed in a semiconductor substrate. A single crystal semiconductor layer containing impurities at a high concentration is formed, and an impurity layer of a conductivity type opposite to that of the semiconductor substrate and an insulating film are sequentially formed on the single crystal semiconductor layer.

(Function) When such an invention is applied to a trench type capacitor and its manufacturing method, the single crystal semiconductor layer prevents leakage current between the capacitors and acts as a barrier layer for injected electrons, thereby preventing the occurrence of soft errors. suppress.

Further, since the single crystal semiconductor layer is formed on the inner surface of the groove, in other words, on the outside of the semiconductor substrate, it can be formed more easily than when it is formed on the inside of the semiconductor substrate.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that the following description will be made assuming that the present invention is applied to a trench type capacitor.

FIGS. 1(a) to 1(e) show an embodiment of the present invention, and show the manufacturing process of a trench type capacitor in order.

Now, with reference to FIGS. 1(a) to 1(e), the structure of a trench type capacitor according to an embodiment and its manufacturing method will be described.

(1) In FIG. 1(a), first, element isolation regions 22 are formed on a P-type semiconductor substrate 21 by selective oxidation. Next, an insulating film 23 is formed on the element isolation region 22 and the substrate 21 to a thickness of, for example, about 3000 Å. Next, the resist 24 is patterned by photolithography. Next, using the resist 24 as a mask, the anti-fiW7i 23 is etched by reactive ion etching to expose the substrate 21. FIG. 1(a) shows the state after the above processing has been completed.

(2) Next, in FIG. 1(b), first, resist 2
Remove 4. This excellent, using the insulating film 23 as a mask,
The substrate 21 is etched by reactive ion etching to form grooves 25. FIG. 1(b) shows the state after this process has been completed.

(3) Next, in FIG. 1C, a single crystal semiconductor layer 26 having the same conductivity type as the substrate 21 and having a higher impurity concentration than the substrate 21 is formed on the inner surface of the groove 25 by selective epitaxial growth. Here, the concentration of this single crystal semiconductor layer 26 is set to about 1017c11-3, and the film thickness is 0.3
It is set to μm. FIG. 1C shows a state in which the single crystal semiconductor layer 26 has been formed.

(4) Next, in FIG. 1(d), the single crystal semiconductor layer 26
A single crystal semiconductor layer 27 of a conductivity type opposite to that of the substrate 21 is formed thereon by selective epitaxial growth. The concentration of this single crystal semiconductor 1i127 is set to, for example, about 10190"3, and the thickness is set to about 0.1 μm, for example. FIG. 1(d) shows the state after the formation of this single crystal semiconductor layer 27. At the upper end of this single crystal semiconductor layer 27, the n-layer 27 is in contact with the semiconductor substrate 21, and the n-layer 18, which will be explained next in FIG. It is designed to be electrically connected to the area.

(5) Next, in FIG. 1(e), first, the insulating film 23
is removed, and an n-type layer 18 is selectively formed on the surface region of the substrate 21 to serve as the source/drain region of the MOS transistor. As described above, this n layer 28 is the single crystal semiconductor layer 2.
Connected to 7. Next, on the single crystal semiconductor layer 27 and on the n
A gate insulating film 29 is formed on the first layer 28 . next,
A capacitor electrode 30 is formed on the gate insulating film 29 and the element isolation region 22. In this case, the inside of the groove 25 is filled with the capacitor electrode 30.

As described above, the lN crystal semiconductor M27 and the capacitor electrode 3
A trench type capacitor is formed with 0 and 0 as opposing electrodes. FIG. 1(a) shows a case where trench type capacitors 311 and 312 are formed on both sides of the element isolation region 22.

As described above, in this embodiment, the substrate 2 is placed on the groove 25.
A single crystal semiconductor layer 26 of the same conductivity type as 1 is formed, and a capacitor body is formed thereon.

With such a configuration, the single crystal semiconductor layer 26 can prevent leakage current from flowing between the trench capacitors 311 and 312.

Furthermore, since the single crystal semiconductor layer 26 serves as a barrier layer against injected electrons, it is possible to suppress the occurrence of soft errors.

Furthermore, the single crystal semiconductor 26 is formed not outside the trench 25, that is, inside the substrate 21, but inside the trench 25, that is, outside the substrate 21, and therefore can be easily formed.

Figures 2 (a) to (e) show other embodiments of the present invention, and similarly to Figures 1 (a) to (θ), they show the manufacturing process of a trench type capacitor in order. It is.

(1) FIG. 2(a) corresponds to the state shown in FIG. 1 fb). That is, using the insulating film 23 as a mask,
The substrate 21 is etched by the reactive ion etching method to form grooves 25.

(2) From this state, as shown in FIG. 2B, a single-crystal semiconductor filling portion 41 is formed using a single-crystal semiconductor of the same conductivity type as the substrate 21 so as to fill the groove 25 by selective epitaxial growth. The concentration of this single crystal semiconductor filling portion 41 is set to, for example, about 1017 cm-3.

(3) Next, in FIG. 2(C), the single crystal semiconductor layer 4
A resist 42 is patterned on all areas on the substrate 21 except for the center part 1 by photolithography. Next, using this resist 42 as a mask, the single-crystal semiconductor filling portion 41 is etched by reactive ion etching to form a groove 43, thereby forming a single-crystal semiconductor as described above in FIG. 1(C). A semiconductor layer 26 is formed.

(4) After that, as shown in FIGS. 2(d) and 2(e), the resist 42 is removed, and the semi-crystalline semiconductor 29, the gate insulating film 30, and the capacitor electrode 31 are sequentially formed as in the previous embodiment. trench type capacitors 321 and 322 are obtained.

Of course, the same effects as in the previous embodiment can also be achieved by the manufacturing method as described above.

Although two embodiments of this invention have been described above, this invention
Of course, the present invention is not limited to this embodiment.

For example, in the previous embodiment, a case was described in which the single crystal semiconductor layer 27 of the opposite conductivity type to the substrate 21 is formed entirely on the single crystal semiconductor layer 26 of the same conductivity type as the substrate 21. It goes without saying that the grooves 25 may be formed only in portions corresponding to the side surfaces of the grooves 25 as shown in the figure.

According to such a configuration, the single crystal semiconductor layer 26 of the same conductivity type as the substrate 21 also serves as an element isolation region, so that the MO
S capacitor can be used.

In addition, in the previous embodiment, the case where the second conductivity type impurity layer was formed using a single crystal semiconductor was explained, but ASSG
Of course, it may be formed using solid phase diffusion such as , PSG, ASdOped Poly, or implantation.

Moreover, it goes without saying that the present invention is applicable to other than trench type capacitors and their manufacturing method.

It goes without saying that this invention can be modified in many other ways without departing from the gist of the invention.

[Effects of the Invention] As described above, according to the present invention, leakage current between capacitors and soft errors in a trench type capacitor can be reduced by 1 lJ.
It is possible to provide a semiconductor device and a method for manufacturing the same that can prevent lIt.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the invention, FIG. 2 is a cross-sectional view showing the second embodiment, FIG. 3 is a cross-sectional view showing the third embodiment, and FIG. 1 is a cross-sectional view showing the structure and manufacturing method of a conventional trench type capacitor. 21... Semiconductor substrate, 22... Element isolation region, 23
...Insulating film, 24...Resist, 25...Groove, 2
6゜27...single crystal semiconductor layer, 28...n'''' layer,
29...Ge Applicant's Representative Patent Attorney Takehiko Suzuej11Figure 1Figure 2Figure 3

Claims (6)

[Claims] (1) a groove formed in a semiconductor substrate of a first conductivity type; a single crystal semiconductor layer having the same conductivity type as the semiconductor substrate and containing a higher concentration of impurities than the semiconductor substrate, and formed on the inner surface of the groove; A semiconductor device comprising: a second conductivity type impurity layer formed on the single crystal semiconductor layer; and an insulating film formed on the second conductivity type impurity layer. (2) The semiconductor device according to claim 1, wherein the second conductivity type impurity layer is formed on the single crystal semiconductor layer in a portion corresponding to the side surface of the groove. . (3) Forming a groove in a semiconductor substrate of a first conductivity type, and forming a single crystal semiconductor layer on the inner surface of the groove that has the same conductivity type as the semiconductor substrate and contains impurities at a higher concentration than the semiconductor substrate. a second step of forming an impurity layer of a second conductivity type on the single crystal semiconductor layer; and a fourth step of forming an insulating film on the impurity layer. A method for manufacturing a semiconductor device, characterized in that: (4) The first step includes: forming a film on the semiconductor substrate of the first conductivity type; selectively removing the film to expose the semiconductor substrate; 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming a groove in the semiconductor substrate by etching using the removed film as a mask. (5) The method of manufacturing a semiconductor device according to claim 3, wherein in the second step, the single crystal semiconductor layer is formed by selective epitaxial growth. (6) The second step is a step of forming a single crystal semiconductor filling portion by filling the groove with a single crystal semiconductor of the same conductivity type as the semiconductor substrate and containing a higher concentration of impurities than the semiconductor substrate; A method for manufacturing a semiconductor device according to claim 3, comprising: forming the single crystal semiconductor layer by etching the single crystal semiconductor filling part to form a groove. .