JPH09512139A - 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 - Google Patents
半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法Info
- Publication number
- JPH09512139A JPH09512139A JP8516323A JP51632396A JPH09512139A JP H09512139 A JPH09512139 A JP H09512139A JP 8516323 A JP8516323 A JP 8516323A JP 51632396 A JP51632396 A JP 51632396A JP H09512139 A JPH09512139 A JP H09512139A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- die
- contact structure
- layer
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
- H05K7/10—Plug-in assemblages of components, e.g. IC sockets
- H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
- H05K7/1061—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by abutting
- H05K7/1069—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by abutting with spring contact pieces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
- B23K20/004—Wire welding
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
- H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67138—Apparatus for wiring semiconductor or solid state device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10909—Materials of terminal, e.g. of leads or electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10946—Leads attached onto leadless component after manufacturing the component
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 半導体ダイが半導体ウエハから単一化される前に、半導体ダイをテストす る方法であって、前記方法が、 それぞれが、頂上を有し、ダイの表面から延びる複数の弾性接触構造を直接、 半導体ダイの表面上の複数のターミナルに取り付けるステップ、 複数のターミナルを有する基板を、ダイの表面に向かって押しつけ、弾性接触 構造のそれぞれのターミナルと頂上の問で複数の圧縮接続を実現するステップ、 及び 半導体ダイをテストするために、基板のターミナルに信号を提供するステップ を含むことを特徴とする、前記方法。 2. 弾性接触構造が複合相互接続要素であることを特徴とする、請求項1に記 載の方法。 3. 弾性接触構造が、めっきによって半導体ダイのターミナルに取り付けられ ることを特徴とする、請求項1に記載の方法。 4. 弾性接触構造が、連続的な上塗りによって半導体ダイのターミナルに保持 されることを特徴とする、請求項1に記載の方法。 5. 半導体ダイをテストし、取り付ける方法が、 複数の半導体ダイが半導体ウエハから単一化される前に: それぞれが、頂上を有し、ダイの表面から延びる複数の弾性接触構造を直接 、複数の半導体ダイのうち少なくとも1つダイの表面上の複数のターミナルに取 り付けるステップ、 複数のターミナルを有する基板を、ダイの表面に向かって押しつけ、弾性接 触構造のそれぞれのターミナルと頂上の間で複数の圧縮接続を実現するステップ 、及び 半導体ダイをテストするために、基板のターミナルに信号を提供するステッ プを含み、 半導体ダイをテストした後に: ダイをウエハから単一化するステップ、及び ダイを電子素子に取り付け、ダイの弾性接触構造と電子素子のターミナルの 間の接続を行うステップを含む、前記方法。 6. 弾性接触構造が複合相互接続要素であることを特徴とする、請求項5に記 載の方法。 7. 電子素子がワイヤ基板であることを特徴とする、請求項5に記載の方法。 8. 複数の半導体ダイが半導体ウエハから単一化される前に: それぞれが、頂上を有し、ダイの表面から延びる複数の弾性接触構造を直接 、複数の半導体ダイの表面上の複数のターミナルに取り付けるステップ、 複数のターミナルを有する基板を、ダイの表面に向かって押しつけ、弾性接 触構造のそれぞれのターミナルと頂上の間で複数の圧縮接続を実現するステップ 、及び 複数の半導体ダイをテストするために、基板のターミナルに信号を提供する ステップを含み、 半導体ダイをテストした後に: ダイをウエハから単一化するステップ、及び ダイを電子素子に取り付け、ダイの弾性接触構造と電子素子のターミナルの 間の接続を行うステップを含む、請求項5に記載の方法。 9. 2つ以上のダイを電子素子の1つに取り付けることを更に含むことを特徴 とする、請求項8に記載の方法。 10. 弾性接触構造を直接半導体デバイスに取り付ける方法が、 半導体ダイの表面上にパターン化された金属層の上に絶縁層を提供するステッ プ、 複数の開口を前記絶縁層に提供するステップ、 ブランケット導電層を絶縁層の頂部に提供するステップ、 前記ブランケット導電層の上に、前記絶縁層内の複数の開口と調整された複数 の開口を有する、マスキング材料からなるパターン化された層を提供するステッ プ、 マスキング材料からなるパターン化された層内の開口の少なくとも一部のそれ ぞれにあるブランケット導電層に、ワイヤを接続するステップ、 各接続されたワイヤを、半導体ダイの表面から延ばすステップ、 各接続されたワイヤを、半導体ダイの表面からのある距離で分離するステップ 、及び 各分離されたワイヤとブランケット導電層の露出された部分を上塗りするステ ップを含むことを特徴とする、前記方法。 11. 分離されたワイヤを上塗りした後で、マスキング材料を除去 し、ブランケット導電層の以前に露出されていた部分の他は全て選択的に除去す るステップを更に含むことを特徴とする、請求項10に記載の方法。 12. マスキング材料がフォトレジストであることを特徴とする、請求項10に記 載の方法。 13. マスキング材料からなるパターン化された層の開口が、絶縁層の開口より 大きいことを特徴とする、請求項10に記載の方法。 14. 半導体デバイスに対するテスト、及びバーンインからなるグループから選 択されたテストを実行する方法が、 弾性接触構造を直接半導体デバイスに取り付けるステップ、 接触領域を有するテスト・ボードに向けて、半導体デバイスを押しつけ、弾性 接触構造の頂上が電気的に前記テスト・ボードの接触領域に接続されるようにす るステップ、 半導体デバイスに関するテストを実施するステップ、及び 最終的に半導体デバイスを、接触領域を有するシステム・ボードに取り付け、 前記システム・ボード上の接触領域に、弾性接触構造の頂上が電気的に接続され るようにするステップを含むことを特徴とする、前記方法。 15. 永久に半導体デバイスをシステム・ボードに接続させるステップを更に含 むことを特徴とする、請求項14に記載の方法。 16. 半導体デバイスを半導体ウエハから単一化する前に、弾性接触構造を半導 体デバイスに取り付けるステップを更に含むことを特徴とする、請求項14に記載 の方法。 17. 半導体デバイスを半導体ウエハから単一化した後に、弾性接触構造を半導 体デバイスに取り付けるステップを更に含むことを特徴とする、請求項14に記載 の方法。 18. 半導体デバイスを永久に接続する前に、半導体デバイスを一時的に接続す る方法が、 複数の電子接触構造をむき出しの半導体デバイスに取り付けるステップ、 半導体デバイスを第1の電子素子に押しつけ、半導体デバイスと第1の電子素 子の間の電子相互接続として機能する電子接触構造で、半導体デバイスと第1の 電子素子との間の一時的な接続を行うステップ、及び 半導体デバイスに取り付けられた同じ電子接触構造を用いて、半導体デバイス と第2の電子素子との間の永久接続を行うステップを含むことを特徴とする、前 記方法。 19. 半導体デバイスを第2の電子素子に対して機械的にバイアスすることによ って、永久接続を行うステップを更に含むことを特徴とする、請求項18に記載の 方法。 20. 半導体デバイスを第2の電子素子に永久的に接続するステップを更に含む ことを特徴とする、請求項18に記載の方法。 21. 電子接触構造が弾性であることを特徴とする、請求項18に記載の方法。 22. 電子接触構造が柔軟(compliant)であることを特徴とする、請求項18に記 載の方法。 23. 第1の電子素子と第2の電子素子の間に一時的な接続を行い、次に第1の 電子素子と第3の電子素子の間に永久的な接続を行う方法が、 複数の弾性接触構造を第1の電子素子の表面に取り付けるステップ、 第1の電子素子を第2の電子素子に対して押しつけ、第1の電子素子と第2の 電子素子の間に一時的な接続を行うステップ、 第2の電子素子を除去するステップ、及び 第1の電子素子を第3の電子素子に取り付けるステップを含むことを特徴とす る、前記方法。 24. 第1及び第2の電子素子が一時的に接続されている間に、第1の電子素子 のバーンイン及びテストからなるグループから選択された少なくとも1つの機能 を実行するステップを更に含むことを特徴とする、請求項23に記載の方法。 25. 直接半導体ダイに取り付けられた弾性接触構造が、 半導体ダイに取り付けられた端部を有し、半導体ダイの表面から延びる複合相 互接続要素、及び 前記複合相互接続要素の端部に接続された事前製造された頂上構造を含むこと を特徴とする、前記弾性接触構造。 26. 前記弾性接触構造が複合相互接続要素であることを特徴とする、請求項25 に記載の弾性接触構造。 27. 半導体ダイから延びる接触構造の端部に関する頂上構造を事前に製造する 方法が、 少なくとも1つの導電材料からなる少なくとも1つの層を、シリコン・ウエハ の表面上に配置するステップ、 少なくとも1つの導電層の上にマスキング材料からなる層を配置するステップ 、 前記マスキング材料に開口をパターン化するステップ、 少なくとも1つの導電材料からなる少なくとも1つの層を、前記開口に配置す るステップ、及び マスキング材料を除去するステップを含むことを特徴とする、前記方法。 28. 開口内で以前配置された少なくとも1つの導電材料からなる少なくとも1 つの層の上に、接続層を配置するステップを更に含むことを特徴とする、請求項 27に記載の方法。 29. 頂上構造を接触構造の端部に接続するステップを更に含むことを特徴とす る、請求項28に記載の方法。 30. 接触構造が弾性接触構造であることを特徴とする、請求項29に記載の方法 。 31. 接触構造が複合相互接続要素であることを特徴とする、請求項29に記載の 方法。 32. 接触構造が、単一化されていない半導体デバイスの上に配置された弾性接 触構造であることを特徴とする、請求項29に記載の方法。 33. 半導体デバイスの訓練(テスト及び/またはバーンイン)する方法が、 半導体ウエハ上の複数の単一化されていない半導体ダイ上に、複数の複合相互 接続要素を製造するステップ、 単一化されていない半導体ダイの少なくとも一部で訓練を行うステップ、及び 半導体ダイを半導体ウエハから単一化するステップを含むことを特徴とする、 前記方法。 34. 複数の複合相互接続要素を製造する前に、ウエハのプローブを実行するス テップを更に含むことを特徴とする、請求項33に記載の方法。 35. 単一化されていない半導体ダイを訓練する前に、ウエハのプローブを実行 するステップを更に含むことを特徴とする、請求項33に記載の方法。 36. 複数の複合相互接続要素を製造するステップが、 半導体ダイの上にブランケット導電層を配置し、前記ブランケット導電層の上 にパターン化されたマスキング層を提供するステップ、 細長い要素をブランケット導電層に取り付けるステップ、及び 前記細長い要素を金属材料で上塗りするステップを含むことを特徴とする、請 求項33に記載の方法。 37. 細長い要素を取り付ける前に、ウエハのプローブを実行するステップを更 に含むことを特徴とする、請求項36に記載の方法。 38. 細長い要素を上塗りする前に、ウエハのプローブを実行するステップを更 に含むことを特徴とする、請求項36に記載の方法。 39. ウエハから半導体ダイを単一化するステップを更に含むこと を特徴とする、請求項33に記載の方法。 40. 単一化された半導体ダイの最終組立を実行するステップを更に含むことを 特徴とする、請求項39に記載の方法。 41. 半導体デバイスの訓練(テスト及び/またはバーンイン)する方法が、 半導体ウエハ上の複数の単一化されていない半導体ダイ上に、複数の弾性接触 構造を取り付けるステップ、 単一化されていない半導体ダイの少なくとも一部で訓練を行うステップ、及び 半導体ダイを半導体ウエハから単一化するステップを含むことを特徴とする、 前記方法。 42. 半導体デバイスをバーンインする方法が、 半導体ウエハ上の複数の単一化されていない半導体ダイ上に、複数の弾性接触 構造を取り付けるステップ、 単一化されていない半導体ダイの一部の上の弾性接触構造に圧縮接続を行うこ とによって、単一化されていない半導体ダイの少なくとも一部でパワーアップを 行うステップ、及び 半導体デバイスを少なくとも150℃で60分未満の間、加熱するステップを含む ことを特徴とする、前記方法。 43. 半導体デバイスを製造する方法が、 半導体デバイスの表面上にターミナルを提供するステップ、及び 前記ターミナルに独立弾性接触構造を取り付けるステップを含むことを特徴と する、前記方法。 44. 弾性接触構造が、ターミナルに対して空気遮断シールされることを特徴と する、請求項43に記載の方法。 45. 前記ターミナルが、 マスキング層をブランケット導電層の上に配置し、及び 各ターミナルの所望の位置でマスキング層に開口を設けることによって形成さ れることを特徴とする、請求項43に記載の方法。 46. 2つ以上のターミナルの相互接続からなるグループから選択された機能を 実行する、ブランケット導電層の一部を定義する追加の開口をマスキング層に提 供するステップ、 接地、及び/またはパワー・プレーンを提供するステップ、及び 半導体デバイスの上に直接1つ、または複数のコンデンサを提供するステップ を更に含むことを特徴とする、請求項45に記載の方法。
Applications Claiming Priority (18)
Application Number | Priority Date | Filing Date | Title |
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US08/340,144 | 1994-11-15 | ||
US08/340,144 US5917707A (en) | 1993-11-16 | 1994-11-15 | Flexible contact structure with an electrically conductive shell |
PCT/US1994/013373 WO1995014314A1 (en) | 1993-11-16 | 1994-11-16 | Contact structure for interconnections, interposer, semiconductor assembly and method |
AT94/13373 | 1994-11-16 | ||
US08/452,255 | 1995-05-26 | ||
US08/452,255 US6336269B1 (en) | 1993-11-16 | 1995-05-26 | Method of fabricating an interconnection element |
US08/457,479 US6049976A (en) | 1993-11-16 | 1995-06-01 | Method of mounting free-standing resilient electrical contact structures to electronic components |
US08/457,479 | 1995-06-01 | ||
US52624695A | 1995-09-21 | 1995-09-21 | |
US08/526,246 | 1995-09-21 | ||
US08/533,584 | 1995-10-18 | ||
US08/533,584 US5772451A (en) | 1993-11-16 | 1995-10-18 | Sockets for electronic components and methods of connecting to electronic components |
US08/554,902 US5974662A (en) | 1993-11-16 | 1995-11-09 | Method of planarizing tips of probe elements of a probe card assembly |
US08/554,902 | 1995-11-09 | ||
US08/558,332 | 1995-11-15 | ||
US08/558,332 US5829128A (en) | 1993-11-16 | 1995-11-15 | Method of mounting resilient contact structures to semiconductor devices |
US94/13373 | 1995-11-15 | ||
PCT/US1995/014885 WO1996015459A1 (en) | 1994-11-15 | 1995-11-15 | Mounting spring elements on semiconductor devices, and wafer-level testing methodology |
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Application Number | Title | Priority Date | Filing Date |
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JP2002063664A Division JP2002359269A (ja) | 1994-11-15 | 2002-03-08 | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
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JPH09512139A true JPH09512139A (ja) | 1997-12-02 |
JP3387930B2 JP3387930B2 (ja) | 2003-03-17 |
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ID=32601250
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51632396A Expired - Fee Related JP3387930B2 (ja) | 1994-11-15 | 1995-11-15 | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
JP2002063664A Withdrawn JP2002359269A (ja) | 1994-11-15 | 2002-03-08 | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
JP2006277615A Pending JP2007059931A (ja) | 1994-11-15 | 2006-10-11 | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002063664A Withdrawn JP2002359269A (ja) | 1994-11-15 | 2002-03-08 | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
JP2006277615A Pending JP2007059931A (ja) | 1994-11-15 | 2006-10-11 | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
Country Status (6)
Country | Link |
---|---|
EP (4) | EP1439397A3 (ja) |
JP (3) | JP3387930B2 (ja) |
KR (7) | KR100335166B1 (ja) |
AU (1) | AU4237696A (ja) |
DE (1) | DE69533041T2 (ja) |
WO (1) | WO1996015459A1 (ja) |
Cited By (6)
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JP2005514627A (ja) * | 2001-12-27 | 2005-05-19 | フォームファクター,インコーポレイテッド | 能動電子部品の直接冷却をともなう冷却アセンブリ |
JP2007059931A (ja) * | 1994-11-15 | 2007-03-08 | Formfactor Inc | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
US7618281B2 (en) | 1998-07-13 | 2009-11-17 | Formfactor, Inc. | Interconnect assemblies and methods |
US7681309B2 (en) | 2001-10-03 | 2010-03-23 | Formfactor, Inc. | Method for interconnecting an integrated circuit multiple die assembly |
KR20190061366A (ko) * | 2017-11-27 | 2019-06-05 | 삼성전자주식회사 | 반도체 패키지의 신호 속도 테스트 장치 |
KR102179457B1 (ko) * | 2020-03-25 | 2020-11-16 | (주)티에스이 | 테스트 소켓 및 이를 포함하는 테스트 장치와, 테스트 소켓의 제조방법 |
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KR100214545B1 (ko) * | 1996-12-28 | 1999-08-02 | 구본준 | 칩 사이즈 반도체 패키지의 제조 방법 |
US7714235B1 (en) | 1997-05-06 | 2010-05-11 | Formfactor, Inc. | Lithographically defined microelectronic contact structures |
US5973394A (en) * | 1998-01-23 | 1999-10-26 | Kinetrix, Inc. | Small contactor for test probes, chip packaging and the like |
US6497581B2 (en) * | 1998-01-23 | 2002-12-24 | Teradyne, Inc. | Robust, small scale electrical contactor |
US6078500A (en) * | 1998-05-12 | 2000-06-20 | International Business Machines Inc. | Pluggable chip scale package |
US6664628B2 (en) | 1998-07-13 | 2003-12-16 | Formfactor, Inc. | Electronic component overlapping dice of unsingulated semiconductor wafer |
US6799976B1 (en) | 1999-07-28 | 2004-10-05 | Nanonexus, Inc. | Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies |
US6812718B1 (en) | 1999-05-27 | 2004-11-02 | Nanonexus, Inc. | Massively parallel interface for electronic circuits |
US7382142B2 (en) | 2000-05-23 | 2008-06-03 | Nanonexus, Inc. | High density interconnect system having rapid fabrication cycle |
US6468098B1 (en) | 1999-08-17 | 2002-10-22 | Formfactor, Inc. | Electrical contactor especially wafer level contactor using fluid pressure |
DE19946497C2 (de) * | 1999-09-28 | 2002-06-06 | Tyco Electronics Logistics Ag | Verfahren zur Herstellung einer Verbindung zweier Gegenstände |
US7952373B2 (en) | 2000-05-23 | 2011-05-31 | Verigy (Singapore) Pte. Ltd. | Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies |
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US7977959B2 (en) | 2007-09-27 | 2011-07-12 | Formfactor, Inc. | Method and apparatus for testing devices using serially controlled intelligent switches |
US8122309B2 (en) | 2008-03-11 | 2012-02-21 | Formfactor, Inc. | Method and apparatus for processing failures during semiconductor device testing |
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JP6071613B2 (ja) * | 2013-02-14 | 2017-02-01 | オリンパス株式会社 | 半導体基板、半導体装置、撮像素子、および撮像装置 |
KR102063508B1 (ko) * | 2013-06-13 | 2020-01-08 | 엘지이노텍 주식회사 | 발광 소자 및 이를 구비한 조명 시스템 |
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-
1995
- 1995-11-15 JP JP51632396A patent/JP3387930B2/ja not_active Expired - Fee Related
- 1995-11-15 KR KR1020007003267A patent/KR100335166B1/ko not_active IP Right Cessation
- 1995-11-15 EP EP04005888A patent/EP1439397A3/en not_active Withdrawn
- 1995-11-15 EP EP02014918A patent/EP1262782A3/en not_active Withdrawn
- 1995-11-15 KR KR1020007003266A patent/KR100335167B1/ko not_active IP Right Cessation
- 1995-11-15 AU AU42376/96A patent/AU4237696A/en not_active Abandoned
- 1995-11-15 KR KR1020007003268A patent/KR100355972B1/ko not_active IP Right Cessation
- 1995-11-15 KR KR10-2000-7003269A patent/KR100366747B1/ko not_active IP Right Cessation
- 1995-11-15 KR KR1020007003263A patent/KR100335165B1/ko not_active IP Right Cessation
- 1995-11-15 EP EP04005887A patent/EP1441232A3/en not_active Withdrawn
- 1995-11-15 KR KR1020007003264A patent/KR100335168B1/ko not_active IP Right Cessation
- 1995-11-15 KR KR10-2000-7003265A patent/KR100366746B1/ko not_active IP Right Cessation
- 1995-11-15 EP EP95940718A patent/EP0792463B1/en not_active Expired - Lifetime
- 1995-11-15 WO PCT/US1995/014885 patent/WO1996015459A1/en active IP Right Grant
- 1995-11-15 DE DE69533041T patent/DE69533041T2/de not_active Expired - Lifetime
-
2002
- 2002-03-08 JP JP2002063664A patent/JP2002359269A/ja not_active Withdrawn
-
2006
- 2006-10-11 JP JP2006277615A patent/JP2007059931A/ja active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007059931A (ja) * | 1994-11-15 | 2007-03-08 | Formfactor Inc | 半導体デバイス上へのばね要素の取り付け、及びウエハレベルのテストを行う方法 |
US7618281B2 (en) | 1998-07-13 | 2009-11-17 | Formfactor, Inc. | Interconnect assemblies and methods |
US7681309B2 (en) | 2001-10-03 | 2010-03-23 | Formfactor, Inc. | Method for interconnecting an integrated circuit multiple die assembly |
JP2005514627A (ja) * | 2001-12-27 | 2005-05-19 | フォームファクター,インコーポレイテッド | 能動電子部品の直接冷却をともなう冷却アセンブリ |
KR20190061366A (ko) * | 2017-11-27 | 2019-06-05 | 삼성전자주식회사 | 반도체 패키지의 신호 속도 테스트 장치 |
KR102179457B1 (ko) * | 2020-03-25 | 2020-11-16 | (주)티에스이 | 테스트 소켓 및 이를 포함하는 테스트 장치와, 테스트 소켓의 제조방법 |
US11131707B1 (en) | 2020-03-25 | 2021-09-28 | Tse Co., Ltd. | Test socket and test apparatus having the same, manufacturing method for the test socket |
Also Published As
Publication number | Publication date |
---|---|
JP3387930B2 (ja) | 2003-03-17 |
EP1439397A3 (en) | 2009-09-02 |
JP2007059931A (ja) | 2007-03-08 |
EP1262782A3 (en) | 2009-06-17 |
KR100366746B1 (ko) | 2003-01-09 |
KR100335168B1 (ko) | 2002-05-04 |
EP1441232A2 (en) | 2004-07-28 |
EP0792463A4 (en) | 1998-06-24 |
JP2002359269A (ja) | 2002-12-13 |
WO1996015459A1 (en) | 1996-05-23 |
KR100335167B1 (ko) | 2002-05-04 |
KR100335166B1 (ko) | 2002-05-04 |
DE69533041T2 (de) | 2004-09-16 |
KR100335165B1 (ko) | 2002-05-04 |
DE69533041D1 (de) | 2004-06-17 |
KR100355972B1 (ko) | 2002-10-12 |
AU4237696A (en) | 1996-06-06 |
EP1262782A2 (en) | 2002-12-04 |
EP0792463B1 (en) | 2004-05-12 |
EP1439397A2 (en) | 2004-07-21 |
EP1441232A3 (en) | 2009-11-04 |
EP0792463A1 (en) | 1997-09-03 |
KR100366747B1 (ko) | 2003-01-09 |
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