JPH09506459A - 不揮発性半導体メモリのためのセンス増幅器 - Google Patents
不揮発性半導体メモリのためのセンス増幅器Info
- Publication number
- JPH09506459A JPH09506459A JP8510030A JP51003096A JPH09506459A JP H09506459 A JPH09506459 A JP H09506459A JP 8510030 A JP8510030 A JP 8510030A JP 51003096 A JP51003096 A JP 51003096A JP H09506459 A JPH09506459 A JP H09506459A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- cell
- load
- current
- electronic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
Landscapes
- Read Only Memory (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.2つの論理状態のうちの特定の1つの状態を想定するメモリセル(40)と 、該セルの特定の論理状態を決定する検知手段(20,14,41,48)とを 具えた電子回路において、 高い供給電圧の感度よりも低い供給電圧の感度を与えるように該回路に印加 される供給電圧に依存する検知手段の感度を制御するために動作するバイアス手 段(24,25)を具えたことを特徴とする電子回路。 2.検知手段は、 検知電圧(AMPIN1)を発生するためメモリセルに検知電流(Isense )を供給する検知負荷(20)と、 基準電流(Iref)から基準電圧(AMPIN2)を発生する基準手段(1 4,41)と、 メモリセルに結合された入力と、検知電圧と基準電圧とを比較して、特定の 論理状態の出力信号を発生する基準手段とを具えた比較器(48)と を具え、 バイアス手段は、少なくとも検知負荷或いは検知電流と基準電流の比を制御 する基準手段に制御信号を供給するように動作することを特徴とする請求の範囲 1記載の電子回路。 3.基準手段は、特定の論理状態を有する基準セル(41)と、基準電流を供給 するとともに、接続点において基準電圧を形成する基準接続点を介して、基準セ ルに結合される基準負荷(14)とを具えたことを特徴とする請求の範囲2に記 載された電子回路。 4.基準負荷と検知負荷は、入力端と出力端との間の電流増幅率を有するカーレ ントミラーのそれぞれの入力端及び出力端を形成し、該バイアス手段は、供給電 圧に依存する該増幅率を制御するように動作することを特徴とする請求の範囲3 記載の電子回路。 5.基準負荷は、並列接続され、一端と基準接続点に接続された制御電極を有す る第1の複数のトランジスタ(15)を具え、 検知負荷は、第1トランジスタ(22)と、少なくとも、メモリセルに並列 接続された導電チャネルと、一端と基準接続点に接続された制御電極とを有する 第2トランジスタ(21)とを具え、 検知負荷は、第2トランジスタの導電チャネルとメモリセルとの間の導電チ ャネルと、バイアス手段に接続された制御電極とを具えた第3トランジスタ(2 4)とを具えたことを特徴とする請求の範囲4記載の電子回路。 6.2つの論理状態のうちの特定1つの状態を想定するメモリセル(40)と、 該メモリセルを横切る検知電圧(AMPIN1)を形成する検知電流 (Isense)を供給するための検知負荷(20)と、 特定の論理状態を有する基準セル(41)と、 該基準セルを横切る基準電圧を形成する基準電流(Iref)を供給する基準 負荷(14)と、 該メモリセルと該検知電圧と該基準電圧を受信する該基準セルに結合された 差動増幅器(48)と を具えた電子回路において、 該電子回路に印加される供給電圧に依存する基準電流に対する検知電流の比 を制御するように動作する手段(24,25)を具えたことを特徴とする電子回 路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/308,047 | 1994-09-16 | ||
US08/308,047 US5487045A (en) | 1994-09-16 | 1994-09-16 | Sense amplifier having variable sensing load for non-volatile memory |
PCT/IB1995/000702 WO1996008822A2 (en) | 1994-09-16 | 1995-08-28 | Sense amplifier for non-volatile semiconductor memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09506459A true JPH09506459A (ja) | 1997-06-24 |
JP3706135B2 JP3706135B2 (ja) | 2005-10-12 |
Family
ID=23192310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51003096A Expired - Fee Related JP3706135B2 (ja) | 1994-09-16 | 1995-08-28 | 不揮発性半導体メモリのためのセンス増幅器 |
Country Status (7)
Country | Link |
---|---|
US (1) | US5487045A (ja) |
EP (1) | EP0729633B1 (ja) |
JP (1) | JP3706135B2 (ja) |
KR (1) | KR100373196B1 (ja) |
DE (1) | DE69524200T2 (ja) |
MY (1) | MY113198A (ja) |
WO (1) | WO1996008822A2 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9423034D0 (en) * | 1994-11-15 | 1995-01-04 | Sgs Thomson Microelectronics | A reference circuit |
GB9423032D0 (en) * | 1994-11-15 | 1995-01-04 | Sgs Thomson Microelectronics | Bit line sensing in a memory array |
US5726934A (en) * | 1996-04-09 | 1998-03-10 | Information Storage Devices, Inc. | Method and apparatus for analog reading values stored in floating gate structures |
US5694366A (en) * | 1996-05-01 | 1997-12-02 | Micron Quantum Devices, Inc. | OP amp circuit with variable resistance and memory system including same |
EP0814480B1 (en) * | 1996-06-18 | 2003-12-17 | STMicroelectronics S.r.l. | Method and circuit for reading low-supply-voltage nonvolatile memory cells |
US5872739A (en) * | 1997-04-17 | 1999-02-16 | Radiant Technologies | Sense amplifier for low read-voltage memory cells |
KR100422814B1 (ko) * | 1997-06-30 | 2004-05-24 | 주식회사 하이닉스반도체 | 반도체 메모리 셀의 전원 측정 장치 |
EP1031991B1 (en) * | 1999-02-26 | 2004-04-28 | STMicroelectronics S.r.l. | Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory |
JP3620992B2 (ja) * | 1999-04-23 | 2005-02-16 | 株式会社 沖マイクロデザイン | 半導体記憶装置 |
DE69905699T2 (de) | 1999-06-21 | 2003-10-16 | St Microelectronics Srl | Lesevorgang für nichtflüchtige Speicher mit einem mit der Lesespannung variablen Abtaststrom, und Anordnung zur Verwirkligung dieses Vorgangs |
US6219279B1 (en) * | 1999-10-29 | 2001-04-17 | Zilog, Inc. | Non-volatile memory program driver and read reference circuits |
DE19955779A1 (de) * | 1999-11-19 | 2001-05-31 | Infineon Technologies Ag | Speichereinrichtung |
US6285615B1 (en) | 2000-06-09 | 2001-09-04 | Sandisk Corporation | Multiple output current mirror with improved accuracy |
DE10038383C1 (de) * | 2000-08-07 | 2002-03-14 | Infineon Technologies Ag | Hochgeschwindigkeits-Lese-Stromverstärker |
JP2003346484A (ja) * | 2002-05-23 | 2003-12-05 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
DE102004055464B4 (de) * | 2004-11-17 | 2012-07-12 | Infineon Technologies Ag | Vorrichtung und Verfahren zum Bereitstellen von Referenzströmen |
WO2007063264A1 (en) * | 2005-12-02 | 2007-06-07 | Arm Limited | Data processing system |
US9859000B1 (en) * | 2016-06-17 | 2018-01-02 | Winbond Electronics Corp. | Apparatus for providing adjustable reference voltage for sensing read-out data for memory |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1221780B (it) * | 1988-01-29 | 1990-07-12 | Sgs Thomson Microelectronics | Circuito di rilevamento dello stato di celle di matrice in memorie eprom in tecnologia mos |
JPH01220295A (ja) * | 1988-02-29 | 1989-09-01 | Nec Corp | 半導体記憶装置 |
US5142495A (en) * | 1989-03-10 | 1992-08-25 | Intel Corporation | Variable load for margin mode |
US5132576A (en) * | 1990-11-05 | 1992-07-21 | Ict International Cmos Technology, Inc. | Sense amplifier having load device providing improved access time |
US5142496A (en) * | 1991-06-03 | 1992-08-25 | Advanced Micro Devices, Inc. | Method for measuring VT 's less than zero without applying negative voltages |
KR100264425B1 (ko) * | 1991-10-16 | 2000-08-16 | 사토 게니치로 | 피롬 아이씨 |
EP0676768B1 (en) * | 1994-03-28 | 2000-12-27 | STMicroelectronics S.r.l. | Reference signal generating method and circuit for differential evaluation of the content of non-volatile memory cells |
-
1994
- 1994-09-16 US US08/308,047 patent/US5487045A/en not_active Expired - Lifetime
-
1995
- 1995-08-28 WO PCT/IB1995/000702 patent/WO1996008822A2/en active IP Right Grant
- 1995-08-28 KR KR1019960702535A patent/KR100373196B1/ko not_active IP Right Cessation
- 1995-08-28 JP JP51003096A patent/JP3706135B2/ja not_active Expired - Fee Related
- 1995-08-28 DE DE69524200T patent/DE69524200T2/de not_active Expired - Lifetime
- 1995-08-28 EP EP95927927A patent/EP0729633B1/en not_active Expired - Lifetime
- 1995-09-14 MY MYPI95002721A patent/MY113198A/en unknown
Also Published As
Publication number | Publication date |
---|---|
DE69524200T2 (de) | 2002-08-14 |
KR960706173A (ko) | 1996-11-08 |
WO1996008822A3 (en) | 2000-11-30 |
WO1996008822A2 (en) | 1996-03-21 |
EP0729633A1 (en) | 1996-09-04 |
DE69524200D1 (de) | 2002-01-10 |
EP0729633B1 (en) | 2001-11-28 |
US5487045A (en) | 1996-01-23 |
JP3706135B2 (ja) | 2005-10-12 |
MY113198A (en) | 2001-12-31 |
KR100373196B1 (ko) | 2003-05-12 |
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