JPH09186324A5 - - Google Patents

Info

Publication number
JPH09186324A5
JPH09186324A5 JP1996342250A JP34225096A JPH09186324A5 JP H09186324 A5 JPH09186324 A5 JP H09186324A5 JP 1996342250 A JP1996342250 A JP 1996342250A JP 34225096 A JP34225096 A JP 34225096A JP H09186324 A5 JPH09186324 A5 JP H09186324A5
Authority
JP
Japan
Prior art keywords
layer
gate
gate body
disposed
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1996342250A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09186324A (ja
Filing date
Publication date
Application filed filed Critical
Publication of JPH09186324A publication Critical patent/JPH09186324A/ja
Publication of JPH09186324A5 publication Critical patent/JPH09186324A5/ja
Pending legal-status Critical Current

Links

JP8342250A 1995-12-21 1996-12-20 ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ Pending JPH09186324A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US898695P 1995-12-21 1995-12-21
US008986 1995-12-21

Publications (2)

Publication Number Publication Date
JPH09186324A JPH09186324A (ja) 1997-07-15
JPH09186324A5 true JPH09186324A5 (enExample) 2004-10-21

Family

ID=21734873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8342250A Pending JPH09186324A (ja) 1995-12-21 1996-12-20 ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ

Country Status (2)

Country Link
US (1) US6284669B1 (enExample)
JP (1) JPH09186324A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004516652A (ja) * 2000-12-11 2004-06-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電界効果型トランジスタを備えた半導体装置の製造方法
US6987061B2 (en) * 2003-08-19 2006-01-17 Texas Instruments Incorporated Dual salicide process for optimum performance
FR2871294A1 (fr) * 2004-06-07 2005-12-09 St Microelectronics Sa Procede de realisation d'un transistor dmos de taille reduite, et transistor dmos en resultant
US7180132B2 (en) * 2004-09-16 2007-02-20 Fairchild Semiconductor Corporation Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region
US7531426B2 (en) * 2005-08-19 2009-05-12 Honeywell International Inc. Approach to high temperature wafer processing
US7504309B2 (en) * 2006-10-12 2009-03-17 International Business Machines Corporation Pre-silicide spacer removal
US7393746B2 (en) * 2006-10-12 2008-07-01 International Business Machines Corporation Post-silicide spacer removal
JP5200399B2 (ja) * 2007-03-26 2013-06-05 富士通セミコンダクター株式会社 Ｍｏｓトランジスタの製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910006249B1 (ko) * 1983-04-01 1991-08-17 가부시기가이샤 히다찌세이사꾸쇼 반도체 장치
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US4908688A (en) * 1986-03-14 1990-03-13 Motorola, Inc. Means and method for providing contact separation in silicided devices
JPH07106570A (ja) * 1993-10-05 1995-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5728619A (en) * 1996-03-20 1998-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer

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