JPH09186324A - ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ - Google Patents

ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ

Info

Publication number
JPH09186324A
JPH09186324A JP8342250A JP34225096A JPH09186324A JP H09186324 A JPH09186324 A JP H09186324A JP 8342250 A JP8342250 A JP 8342250A JP 34225096 A JP34225096 A JP 34225096A JP H09186324 A JPH09186324 A JP H09186324A
Authority
JP
Japan
Prior art keywords
gate
layer
silicide
drain
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8342250A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09186324A5 (enExample
Inventor
P Elderjack John
ピー．エルデルジャク ジョン
N Hatter Louis
エヌ．ハッター ルイス
P Smith Jeffrey
ピー．スミス ジェフリー
Tsuon Yuan Han
− ツオン ユアン ハン
Yuan Yan Yua
− ユアン ヤン ユア
R Ephland Taylor
アール．エフランド テイラー
Mathew Thompson C
トンプソン シー．マシュー
K Arch John
ケイ．アーチ ジョン
Murphy Maryann
アン マーフィ メアリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH09186324A publication Critical patent/JPH09186324A/ja
Publication of JPH09186324A5 publication Critical patent/JPH09186324A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP8342250A 1995-12-21 1996-12-20 ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ Pending JPH09186324A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US898695P 1995-12-21 1995-12-21
US008986 1995-12-21

Publications (2)

Publication Number Publication Date
JPH09186324A true JPH09186324A (ja) 1997-07-15
JPH09186324A5 JPH09186324A5 (enExample) 2004-10-21

Family

ID=21734873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8342250A Pending JPH09186324A (ja) 1995-12-21 1996-12-20 ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ

Country Status (2)

Country Link
US (1) US6284669B1 (enExample)
JP (1) JPH09186324A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002049092A1 (en) * 2000-12-11 2002-06-20 Koninklijke Philips Electronics N.V. Method for the manufacture of a semiconductor device with a field-effect transistor
JP2008244008A (ja) * 2007-03-26 2008-10-09 Fujitsu Microelectronics Ltd 高耐圧ｍｏｓトランジスタの製造方法、及び高耐圧ｍｏｓトランジスタ

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6987061B2 (en) * 2003-08-19 2006-01-17 Texas Instruments Incorporated Dual salicide process for optimum performance
FR2871294A1 (fr) * 2004-06-07 2005-12-09 St Microelectronics Sa Procede de realisation d'un transistor dmos de taille reduite, et transistor dmos en resultant
US7180132B2 (en) * 2004-09-16 2007-02-20 Fairchild Semiconductor Corporation Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region
US7531426B2 (en) * 2005-08-19 2009-05-12 Honeywell International Inc. Approach to high temperature wafer processing
US7504309B2 (en) * 2006-10-12 2009-03-17 International Business Machines Corporation Pre-silicide spacer removal
US7393746B2 (en) * 2006-10-12 2008-07-01 International Business Machines Corporation Post-silicide spacer removal

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910006249B1 (ko) * 1983-04-01 1991-08-17 가부시기가이샤 히다찌세이사꾸쇼 반도체 장치
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US4908688A (en) * 1986-03-14 1990-03-13 Motorola, Inc. Means and method for providing contact separation in silicided devices
JPH07106570A (ja) * 1993-10-05 1995-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5728619A (en) * 1996-03-20 1998-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002049092A1 (en) * 2000-12-11 2002-06-20 Koninklijke Philips Electronics N.V. Method for the manufacture of a semiconductor device with a field-effect transistor
JP2008244008A (ja) * 2007-03-26 2008-10-09 Fujitsu Microelectronics Ltd 高耐圧ｍｏｓトランジスタの製造方法、及び高耐圧ｍｏｓトランジスタ

Also Published As

Publication number Publication date
US6284669B1 (en) 2001-09-04

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