JPH09120679A - ２ポートタイプの高密度メモリセル - Google Patents
２ポートタイプの高密度メモリセルInfo
- Publication number
- JPH09120679A JPH09120679A JP8198063A JP19806396A JPH09120679A JP H09120679 A JPH09120679 A JP H09120679A JP 8198063 A JP8198063 A JP 8198063A JP 19806396 A JP19806396 A JP 19806396A JP H09120679 A JPH09120679 A JP H09120679A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- write
- line
- gate
- gate array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 abstract description 7
- 238000012512 characterization method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US159495P | 1995-07-27 | 1995-07-27 | |
| US001594 | 1995-07-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09120679A true JPH09120679A (ja) | 1997-05-06 |
| JPH09120679A5 JPH09120679A5 (enExample) | 2004-08-12 |
Family
ID=21696870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8198063A Pending JPH09120679A (ja) | 1995-07-27 | 1996-07-26 | ２ポートタイプの高密度メモリセル |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0756284B1 (enExample) |
| JP (1) | JPH09120679A (enExample) |
| KR (1) | KR100431478B1 (enExample) |
| DE (1) | DE69620688T2 (enExample) |
| TW (1) | TW304265B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008541333A (ja) * | 2005-05-19 | 2008-11-20 | フリースケール セミコンダクター インコーポレイテッド | 記憶回路及びその方法 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4377856A (en) * | 1980-08-15 | 1983-03-22 | Burroughs Corporation | Static semiconductor memory with reduced components and interconnections |
| US4613958A (en) * | 1984-06-28 | 1986-09-23 | International Business Machines Corporation | Gate array chip |
| JP2837682B2 (ja) * | 1989-01-13 | 1998-12-16 | 株式会社日立製作所 | 半導体記憶装置 |
| EP0434852B1 (en) * | 1989-12-23 | 1995-05-17 | International Business Machines Corporation | Highly integrated multi-port semiconductor storage |
| EP0473819A1 (en) * | 1990-09-05 | 1992-03-11 | International Business Machines Corporation | Multiport memory cell |
| US5289432A (en) * | 1991-04-24 | 1994-02-22 | International Business Machines Corporation | Dual-port static random access memory cell |
-
1996
- 1996-07-25 KR KR1019960030245A patent/KR100431478B1/ko not_active Expired - Lifetime
- 1996-07-26 JP JP8198063A patent/JPH09120679A/ja active Pending
- 1996-07-29 EP EP96305546A patent/EP0756284B1/en not_active Expired - Lifetime
- 1996-07-29 DE DE69620688T patent/DE69620688T2/de not_active Expired - Lifetime
- 1996-10-04 TW TW085112122A patent/TW304265B/zh not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008541333A (ja) * | 2005-05-19 | 2008-11-20 | フリースケール セミコンダクター インコーポレイテッド | 記憶回路及びその方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW304265B (enExample) | 1997-05-01 |
| DE69620688T2 (de) | 2002-08-14 |
| KR100431478B1 (ko) | 2004-08-25 |
| DE69620688D1 (de) | 2002-05-23 |
| EP0756284B1 (en) | 2002-04-17 |
| EP0756284A3 (en) | 1997-02-12 |
| KR980011461A (ko) | 1998-04-30 |
| EP0756284A2 (en) | 1997-01-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051227 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060104 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20060404 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20060407 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20061106 |