JPH08330444A - グラウンドポテンシャルに接続されていないソース又はドレーンを有するHVp−チャンネル及びn−チャンネルデバイスを含む薄いエピタキシャルRESURF集積回路 - Google Patents
グラウンドポテンシャルに接続されていないソース又はドレーンを有するHVp−チャンネル及びn−チャンネルデバイスを含む薄いエピタキシャルRESURF集積回路Info
- Publication number
- JPH08330444A JPH08330444A JP8134380A JP13438096A JPH08330444A JP H08330444 A JPH08330444 A JP H08330444A JP 8134380 A JP8134380 A JP 8134380A JP 13438096 A JP13438096 A JP 13438096A JP H08330444 A JPH08330444 A JP H08330444A
- Authority
- JP
- Japan
- Prior art keywords
- region
- integrated circuit
- channel
- source
- high voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 210000000746 body region Anatomy 0.000 claims abstract description 16
- 239000002019 doping agent Substances 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 239000007943 implant Substances 0.000 abstract description 11
- 230000000295 complement effect Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 9
- 230000005669 field effect Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002028 premature Effects 0.000 description 2
- 101150068246 V-MOS gene Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
ンドポテンシャルに接続されずに動作するときに、比較
的高電圧に耐えられるようにした集積回路を提供する。 【構成】 ボディ領域(pBODY)の下の投影された箇所
に少なくとも存在し、エピタキシャル層(N−EPI)
の濃度及びウェル領域(NWELL)の中間のドーパント濃
度を有する第1のタイプの導電性(n)の埋設層(SO
FT−N)を含む集積回路。
Description
duced SURface Field 、減少した表面電界)条件を使用
しこれによりパワーデバイスが、特にn−チャンネルL
DMOSトランジスタ及び/又は横型のp−チャンネル
トランジスタがそれらのいずれかのソース又はドレーン
がグラウンドポテンシャルに接続されずに動作するとき
に、比較的高電圧に耐えられるようにした集積回路に関
する。本発明はブレークダウン電圧特性を改良し、導電
抵抗を減少させることと、臨界条件下で動作する際にも
ソース(ドレーン)フォロワコンフィギュレーションで
前記横型RESURFトランジスタを使用することを可
能にする。
同じチップ上に高密度集積され低電圧で動作する1又は
2以上のパワートランジスタと単一のプロセシング及び
コントロール回路を含んでいる。通常混合技術(BiC
MOS)デバイスと呼ばれるこのタイプの集積回路の使
用は、多くの用途における複数の(個々の)デバイスの
使用の代替としてより頻繁に考えられるようになって来
ている。例えばn−チャンネルLDMOS及びp−チャ
ンネルMOSである横型の相補電界効果パワートランジ
スタCMOSの高電圧に耐える能力を改良するための技
術は所謂RESURF技術である。この技術はJ・アペ
ルスらによりPhilips Journal Res., の第35巻 (1980
年) の1 〜13頁に記載されている。この記事を本明細書
で参照できる。
トを正確にコントロールすることにより、薄いエピタキ
シャル層中に集積回路を形成するために開発されてい
る。これは、例外的に高い電圧に耐えうる横型CMOS
トランジスタの集積を可能にする。RESURF技術は
インプラントドースのコントロールを高い正確性で行な
うことを前提とし、従来のHVトランジスタの集積度で
通常要求されるものより薄いエピタキシャル層で動作す
るHV横型トランジスタの実現を可能にする。従って、
例えばn−導電タイプを有するエピタキシャル層とp−
導電性の基板間の接合に関する空乏域の底部は、例えば
このタイプのデバイス中の出力パワートランジスタとし
て通常使用されるようなn−チャンネルLDMOSトラ
ンジスタの場合に、高電圧に耐えるRESURF集積構
造の能力に決定的な役割を有する。
ダウン機構を、ソースがグラウンドポテンシャルに結合
された標準的なコンフィギュレーションに関して及び、
ドレーン電圧が所謂「ピンチオフ」電圧より高い、同
じ、及び低いのそれぞれ異なった動作条件で十分に検討
した。1994年2月24日付の本出願人による特願平6−52
749 号はRESURF−LDMOSトランジスタの改良
された構造を記述している。この場合、ドレーン電圧が
「ピンチオフ」より低く維持される場合でも、ブレーク
ダウン電圧は、ドリフト領域の完全な空乏に関して有利
になるように十分に高められる。これは、ドレーン領域
の下の基板半導体のドーパント濃度を局所的に増加させ
るために「富化」埋設層を形成することにより達成され
る。この先行特許出願の関連する記載は本明細書中に組
み入れられる。
ウンドポテンシャルに結合されていないこれらの用途、
つまり部分的又は完全なソースフォロワLDMOS段の
場合には、集積構造は「パンチ−スルー」現象に関して
高い重要性を有していることは周知である。これは一般
に、LDMOSのボディ領域の下ではボディと基板間に
正味電荷が残り、大きさは限定されていても、これが10
〜60Vのオーダーの「パンチ−スルー」電圧を決定でき
るからである。一般にRESURF条件を確保するため
の要件に関係がないと、BiCMOS混合プロセスで通
常意図されるインプラントステップを通してn+ 埋設層
を形成することによりボディ領域の下の電荷を増加させ
ることは米国特許第4,639,761号から公知である。これ
が構造の早過ぎるブレークダウン(表面近くのブレーク
ダウン)を促進するかもしれないため、ボディ領域下の
n−埋設層の利用はRESURF構造(典型的には特別
に薄いエピタキシャル層を必要とする)では適用された
ことがなく、かつ適用できると考えられたこともない。
RF条件の開発に起因して高電圧で動作するよう意図さ
れた、従って薄いエピタキシャル層内に集積できる横型
の電界効果相補デバイスは極度に高いブレークダウン電
圧に達することができる。これは、ウェル領域の導電性
及びエピタキシャル層の導電性と同じタイプの導電性で
ありかつ上述した領域と比較して中間のドーパント濃度
を有する層つまり埋設領域を前記ウェル領域に隣接して
かつボディ領域の下の投影領域に形成することにより達
成される。LDMOS構造では、中間のドーパント濃度
を有する埋設層の効率性は電界分離拡散部の存在により
高められる。これは一般に、本出願人により1993年2月
18日に出願された特願平5−55235 号に述べられている
ように、ソース及びチャンネルエリアを限定する電界酸
化物の端部の下に位置する。
ジスタの実現を許容し、該トランジスタは、250 Vのオ
ーダーか、中間のドーピングレベルを有する埋設領域の
ない従来技術の同等のLDMOS−RESURF構造に
より耐えられる最大電圧より高い耐久電圧の能力を有す
るソースフォロワとして設計される。同様に、上述のn
−チャンネルLDMOS構造のそれを参考にできるよう
に、相補MOS構造のドレーン領域を含む対応するボデ
ィ領域の下に位置する中程度のドーパント濃度の埋設領
域の存在を意図している。この相補構造でも、中程度の
ドーパント濃度の埋設領域は、デバイスのソース/ドレ
ーン及び基板間の「パンチスルー」特性を改良する。実
際に、本発明は、例えばソースフォロワとして形成でき
るp−チャンネルLDMOSトランジスタ及び高電圧で
動作できるp−チャンネルMOSトランジスタであるH
V−MOSデバイスの実現を許容し、これによりエピタ
キシャル層の厚さの増加の必要性を無くす。これによ
り、比較的低いサプライ電圧用に名目的に設計されるB
iCMOSデバイスの生産の際の高電圧素子の集積の良
好な整合性を確保することが可能になる。全てが、集積
の密度特性に関する妥協がなく、高電圧に耐えるパワー
トランジスタ用に必要なエピタキシャル層の厚さを増加
させる必要性により悪影響を及ぼされることがない。
参照しながら行なう引き続く重要な態様の説明を通して
明らかになるであろう。図1は集積回路の部分断面図で
あり、より詳細には混合技術で集積された回路(BiC
MOS)中でHV−RESURFパワーデバイスとして
通常使用される2個の相補電界効果デバイスの部分断面
図である。純粋に例示の目的であるが、図1はHVn−
チャンネルLDMOSの構造及びHVp−チャンネルM
OSの構造を示している。両構造はp−基板(P−SU
B)上に成長した比較的薄い厚さのn−エピタキシャル
層(N−EPI)中に形成され、比較的高い電圧で機能
するトランジスタを許容する構造条件を実現する。一般
に集積回路は、通常シグナルプロセシング及びコントロ
ール回路を含んで成る集積回路の出力パワー段を実現す
るために、前記一方又は他方あるいは両方の構造を含む
ことがある。この回路は、BiCMOSプロセスにより
提供される機会に従って、低サプライ電圧用として意図
される高集積密度のバイポーラ又はMOS(CMOS)
トランジスタを使用することがある。このタイプのプロ
セスでは、構造に関する互換性の要件が互いに技術的に
異なっていることは非常に重要である。
照すると、対応するウェル領域(NWELL)に隣接するn
−チャンネルLDMOS構造のボディ領域の及び相補p
−チャンネルMOSトランジスタのボディ領域の下の投
影ゾーンには、エピタキシャル層(N−EPI)のドー
パント濃度とNWELL領域のドーパント濃度と比較すると
その中間のドーパント濃度を有するn−タイプの埋設層
(SOFT−N)が形成されている。中間のドーピング
レベルを有するこの埋設層(SOFT−N)は専用ステ
ップにより基板の限定されたエリアをインプラントする
ことにより、又はプロセスの他の特定の目的用に既に限
定された(かつ製造プロセスの異なった段で実行される
べき)インプラント条件を使用することにより形成でき
る。埋設領域SOFT−Nの横方向の広がりであるイン
プラントエリアは、要求されるデバイスの電子的挙動に
関連して調節できる。図中に代替プロフィールa)及びb)
により例示したように、埋設領域SOFT−Nの横方向
の広がりは、n−チャンネルLDMOS構造のドレーン
領域の下まで(ケースb)、又はp−チャンネルMOS
トランジスタ構造のソース領域の下まで(ケースb)広
げることができる。
で広げることはデバイスの導電抵抗(Ron)を最小に
するために有利である。しかしデバイスのpBODY領域に
より範囲限定される周縁を越えて埋設領域SOFT−N
が横方向に広がることは、さもなければ得られるであろ
う最大値と比較してブレークダウン電圧を僅かに減少さ
せる傾向がある。埋設領域SOFT−Nの横方向の広が
りがボディ領域(pBODY)の投影エリアと少なくとも同
じか僅かに広い場合でさえも、実際的な条件では、埋設
領域SOFT−Nの存在により決定される電荷の増加に
より達成される「パンチ−スルー」電圧の増加の効果は
とにかく達成される。図示の例ではソース及びチャンネ
ルエリアを限定する電界酸化物(FIELDOX.)の
端部の真下にp−タイプ拡散(p−field )である電界
分離物が組み合わされて存在することによってさえも、
HVn−チャンネルLDMOS構造の場合のブレークダ
ウン電圧は決定的に改良される。
ラウンドポテンシャルに結合されていない場合(ソース
フォロワ段)の条件下で動作する場合、高電圧に耐える
構造的な能力は、電界分離拡散物(p−field )及び、
ボディ領域の下に投影された埋設層SOFT−Nの存在
により決定されるボディ領域と基板間の正味の残りの電
荷の増加の間の相乗効果に起因する。同様に図面に例示
されたようなHVp−チャンネルMOSトランジスタ構
造のブレークダウン電圧は、ドレーン−ボディ領域中に
小さい電界を確立するために僅かにドープされたドレー
ン領域を使用することにより増加することができ、これ
は1986年12月12日のIEEE Trans. on Electron Dev.
第ED-33 巻、第12号のA.W.ルディクイッツェによる
「アナログ及びスイッチング用途用の多様な250/300 V
ICプロセス」に記載されている。この条件は、前記記事
に述べられているように、n−チャンネルLDMOS用
に使用されるp−電界インプラントステップを開発する
ことにより達成できる。このp−タイプドレーンの広が
り領域は、電界酸化物(FIELD OX.)により被
覆され、従って外部電荷により(つまりパラシチックな
効果により)僅かに影響される。しかしこれらの特性を
有するデバイスは、ソース/ドレーン及び基板間の「パ
ンチスルー」電圧に関して制限されたままである。
SURF構造中でさえも、NWELL領域の下のSOFT−
N領域の形成は「パンチスルー」特性を決定的に改良す
る。相補MOSトランジスタ構造及びLDMOS構造で
は、中間のドーパント濃度の埋設層SOFT−Nのイン
プラントを注意深く調整しなければならない。過度のイ
ンプラントドースは「パンチスルー」電圧の要件を満足
するが、抵抗の減少に起因して、半導体表面に強度が増
加した電界を生成する傾向があり、従って所謂早過ぎる
ブレークダウン現象を生じさせるために有利になる。逆
にドースが過度に低いと「パンチスルー」電圧の所望の
増加を生じさせない。一般に、SOFT−N領域用の最
適なインプラントドースは絶縁層中にキャリアの注入を
実質的に行なわせることなく、ブレークダウンが半導体
の表面から離れた箇所で起こるようにし、従ってその動
作寿命の間のデバイスの大きな信頼性を確保する。図示
の例は、5V、20V及び200 VのBiCMOSプロセス
に関するもので、種々の特性を下記の通り纏める。
n−チャンネルLDMOS構造の横方向の広がりは必要
とする電気的性能に依存する。
の相補電界効果デバイスの部分断面図。
ャル層 SOFT−N・・・埋設層
Claims (6)
- 【請求項1】 シグナルプロセシング用のバイポーラ及
びCMOSデバイスとともに高電圧用のn−チャンネル
LDMOS及びp−チャンネルMOSデバイスを含む、
第2のタイプの導電性の基板上に成長した第1のタイプ
の導電性の比較的薄いエピタキシャル層中に形成された
BiCMOS集積回路において、これらの高電圧デバイ
スが、デバイスのボディ領域の下の投影された箇所に少
なくとも存在し、かつ前記エピタキシャル層の濃度及
び、前記ボディ領域内のデバイスのソース又はドレーン
領域の濃度の間の中間のドーパント濃度を有する前記第
1のタイプの埋設層を含んで成ることを特徴とする集積
回路。 - 【請求項2】 前記埋設領域が前記ボディ領域の投影さ
れた周縁部を越えて横方向に広がっている請求項1に記
載の集積回路。 - 【請求項3】 前記高電圧n−チャンネルMOSデバイ
スが厚い電界酸化物層により囲まれたソース及びチャン
ネルエリアを有し、その端部を限定する前記エリア上に
ゲート電極が存在し、前記端部の下には第2のタイプの
導電性の拡散領域が存在する請求項1に記載の集積回
路。 - 【請求項4】 前記第2のタイプの導電性の拡散領域の
拡散プロフィールが、高電圧MOSデバイス中に広がっ
たドレーン及びソースエリアを形成するために使用され
た拡散プロフィールと同一である請求項3に記載の集積
回路。 - 【請求項5】 前記第2のタイプの導電性の拡散領域が
前記電界酸化物の端部と自己整列している請求項3又は
4に記載の集積回路。 - 【請求項6】 第1の導電性の前記埋設領域のドーパン
ト濃度を、高電圧n−チャンネルデバイスのボディ領域
の下及び高電圧p−チャンネルデバイスのソース及びド
レーン領域の下のウェル領域中の完全な空乏条件を満足
するように調節した請求項1に記載の集積回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP95830176A EP0741416B1 (en) | 1995-05-02 | 1995-05-02 | Thin epitaxy RESURF ic containing HV p-ch and n-ch devices with source or drain not tied to grounds potential |
IT95830176.4 | 1995-05-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08330444A true JPH08330444A (ja) | 1996-12-13 |
JP4037472B2 JP4037472B2 (ja) | 2008-01-23 |
Family
ID=8221913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13438096A Expired - Fee Related JP4037472B2 (ja) | 1995-05-02 | 1996-05-01 | グラウンドポテンシャルに接続されていないソース又はドレーンを有するHVp−チャンネル及びn−チャンネルデバイスを含む薄いエピタキシャルRESURF集積回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5852314A (ja) |
EP (1) | EP0741416B1 (ja) |
JP (1) | JP4037472B2 (ja) |
DE (1) | DE69522926T2 (ja) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197908A (ja) * | 2001-09-12 | 2003-07-11 | Seiko Instruments Inc | 半導体素子及びその製造方法 |
JP2005116651A (ja) * | 2003-10-06 | 2005-04-28 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2005236142A (ja) * | 2004-02-20 | 2005-09-02 | Shindengen Electric Mfg Co Ltd | 横型短チャネルdmos及びその製造方法並びに半導体装置 |
JP2006041533A (ja) * | 2004-07-27 | 2006-02-09 | Robert Bosch Gmbh | 高電圧mosトランジスタおよび相応の製造方法 |
JP2008066508A (ja) * | 2006-09-07 | 2008-03-21 | New Japan Radio Co Ltd | 半導体装置 |
KR100832719B1 (ko) * | 2006-12-27 | 2008-05-28 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
JP2011181694A (ja) * | 2010-03-01 | 2011-09-15 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
CN102479720A (zh) * | 2010-11-29 | 2012-05-30 | 联华电子股份有限公司 | 抗击穿漏电流的金属氧化物半导体晶体管及其制造方法 |
JP2013187521A (ja) * | 2012-03-12 | 2013-09-19 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2018018977A (ja) * | 2016-07-28 | 2018-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3315356B2 (ja) * | 1997-10-15 | 2002-08-19 | 株式会社東芝 | 高耐圧半導体装置 |
US6225673B1 (en) * | 1998-03-03 | 2001-05-01 | Texas Instruments Incorporated | Integrated circuit which minimizes parasitic action in a switching transistor pair |
US6313482B1 (en) | 1999-05-17 | 2001-11-06 | North Carolina State University | Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein |
US6291304B1 (en) | 1999-09-15 | 2001-09-18 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a high voltage transistor using P+ buried layer |
KR100336562B1 (ko) * | 1999-12-10 | 2002-05-11 | 박종섭 | 모스 형성방법 |
US6236100B1 (en) * | 2000-01-28 | 2001-05-22 | General Electronics Applications, Inc. | Semiconductor with high-voltage components and low-voltage components on a shared die |
EP1148555A1 (en) * | 2000-04-21 | 2001-10-24 | STMicroelectronics S.r.l. | RESURF LDMOS field-effect transistor |
KR100377130B1 (ko) * | 2000-11-22 | 2003-03-19 | 페어차일드코리아반도체 주식회사 | 반도체 소자 및 그 제조 방법 |
US6818494B1 (en) * | 2001-03-26 | 2004-11-16 | Hewlett-Packard Development Company, L.P. | LDMOS and CMOS integrated circuit and method of making |
US6541819B2 (en) | 2001-05-24 | 2003-04-01 | Agere Systems Inc. | Semiconductor device having non-power enhanced and power enhanced metal oxide semiconductor devices and a method of manufacture therefor |
US20030001216A1 (en) | 2001-06-27 | 2003-01-02 | Motorola, Inc. | Semiconductor component and method of manufacturing |
US6486034B1 (en) | 2001-07-20 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method of forming LDMOS device with double N-layering |
US6475870B1 (en) | 2001-07-23 | 2002-11-05 | Taiwan Semiconductor Manufacturing Company | P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture |
EP1482560A4 (en) * | 2002-03-01 | 2008-02-27 | Sanken Electric Co Ltd | SEMICONDUCTOR DEVICE |
KR100867574B1 (ko) * | 2002-05-09 | 2008-11-10 | 페어차일드코리아반도체 주식회사 | 고전압 디바이스 및 그 제조방법 |
US7173308B2 (en) * | 2002-10-25 | 2007-02-06 | Shindengen Electric Manufacturing Co., Ltd. | Lateral short-channel DMOS, method for manufacturing same and semiconductor device |
US6870218B2 (en) * | 2002-12-10 | 2005-03-22 | Fairchild Semiconductor Corporation | Integrated circuit structure with improved LDMOS design |
US7427795B2 (en) * | 2004-06-30 | 2008-09-23 | Texas Instruments Incorporated | Drain-extended MOS transistors and methods for making the same |
US7187033B2 (en) * | 2004-07-14 | 2007-03-06 | Texas Instruments Incorporated | Drain-extended MOS transistors with diode clamp and methods for making the same |
DE102004043284A1 (de) * | 2004-09-08 | 2006-03-23 | X-Fab Semiconductor Foundries Ag | DMOS-Transistor für hohe Drain- und Sourcespannungen |
US7468537B2 (en) * | 2004-12-15 | 2008-12-23 | Texas Instruments Incorporated | Drain extended PMOS transistors and methods for making the same |
US7262471B2 (en) * | 2005-01-31 | 2007-08-28 | Texas Instruments Incorporated | Drain extended PMOS transistor with increased breakdown voltage |
US20060220170A1 (en) * | 2005-03-31 | 2006-10-05 | Chih-Feng Huang | High-voltage field effect transistor having isolation structure |
CN100449782C (zh) * | 2005-04-29 | 2009-01-07 | 崇贸科技股份有限公司 | 具隔离结构的金属氧化物半导体场效晶体管及其制作方法 |
CN1866542B (zh) * | 2005-05-18 | 2010-04-28 | 崇贸科技股份有限公司 | 具有隔离结构的mos场效应晶体管及其制作方法 |
US20070290261A1 (en) * | 2006-06-15 | 2007-12-20 | System General Corp. | Self-driven ldmos transistor |
US7781843B1 (en) | 2007-01-11 | 2010-08-24 | Hewlett-Packard Development Company, L.P. | Integrating high-voltage CMOS devices with low-voltage CMOS |
US7602017B2 (en) * | 2007-03-13 | 2009-10-13 | Fairchild Semiconductor Corporation | Short channel LV, MV, and HV CMOS devices |
DE102007034800A1 (de) | 2007-03-26 | 2008-10-02 | X-Fab Dresden Gmbh & Co. Kg | Maskensparende Herstellung komplementärer lateraler Hochvolttransistoren mit RESURF-Struktur |
US7906810B2 (en) * | 2008-08-06 | 2011-03-15 | United Microelectronics Corp. | LDMOS device for ESD protection circuit |
US9184097B2 (en) * | 2009-03-12 | 2015-11-10 | System General Corporation | Semiconductor devices and formation methods thereof |
US8941188B2 (en) * | 2012-03-26 | 2015-01-27 | Infineon Technologies Austria Ag | Semiconductor arrangement with a superjunction transistor and a further device integrated in a common semiconductor body |
US9087707B2 (en) | 2012-03-26 | 2015-07-21 | Infineon Technologies Austria Ag | Semiconductor arrangement with a power transistor and a high voltage device integrated in a common semiconductor body |
US8916440B2 (en) | 2012-08-03 | 2014-12-23 | International Business Machines Corporation | Semiconductor structures and methods of manufacture |
DE102016101679B4 (de) * | 2016-01-29 | 2019-03-28 | Infineon Technologies Austria Ag | Halbleitervorrichtung mit einem lateralen Transistor |
US10153366B2 (en) | 2016-03-09 | 2018-12-11 | Polar Semiconductor, Llc | LDMOS transistor with lightly-doped annular RESURF periphery |
US20170292047A1 (en) | 2016-04-12 | 2017-10-12 | Rextac Llc | Hexene-1 Containing Amorphous Polyalphaolefins For Improved Hot Melt Adhesives |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4300150A (en) * | 1980-06-16 | 1981-11-10 | North American Philips Corporation | Lateral double-diffused MOS transistor device |
NL8103218A (nl) * | 1981-07-06 | 1983-02-01 | Philips Nv | Veldeffekttransistor met geisoleerde stuurelektrode. |
US5043788A (en) * | 1988-08-26 | 1991-08-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with functional portions having different operating voltages on one semiconductor substrate |
EP0500233A2 (en) * | 1991-02-14 | 1992-08-26 | National Semiconductor Corporation | Bipolar transistor structure & BICMOS IC fabrication process |
-
1995
- 1995-05-02 DE DE69522926T patent/DE69522926T2/de not_active Expired - Fee Related
- 1995-05-02 EP EP95830176A patent/EP0741416B1/en not_active Expired - Lifetime
-
1996
- 1996-04-30 US US08/643,152 patent/US5852314A/en not_active Expired - Lifetime
- 1996-05-01 JP JP13438096A patent/JP4037472B2/ja not_active Expired - Fee Related
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003197908A (ja) * | 2001-09-12 | 2003-07-11 | Seiko Instruments Inc | 半導体素子及びその製造方法 |
JP2005116651A (ja) * | 2003-10-06 | 2005-04-28 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2005236142A (ja) * | 2004-02-20 | 2005-09-02 | Shindengen Electric Mfg Co Ltd | 横型短チャネルdmos及びその製造方法並びに半導体装置 |
JP2006041533A (ja) * | 2004-07-27 | 2006-02-09 | Robert Bosch Gmbh | 高電圧mosトランジスタおよび相応の製造方法 |
JP2008066508A (ja) * | 2006-09-07 | 2008-03-21 | New Japan Radio Co Ltd | 半導体装置 |
KR100832719B1 (ko) * | 2006-12-27 | 2008-05-28 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
JP2011181694A (ja) * | 2010-03-01 | 2011-09-15 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
CN102479720A (zh) * | 2010-11-29 | 2012-05-30 | 联华电子股份有限公司 | 抗击穿漏电流的金属氧化物半导体晶体管及其制造方法 |
JP2013187521A (ja) * | 2012-03-12 | 2013-09-19 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2018018977A (ja) * | 2016-07-28 | 2018-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0741416B1 (en) | 2001-09-26 |
US5852314A (en) | 1998-12-22 |
DE69522926D1 (de) | 2001-10-31 |
DE69522926T2 (de) | 2002-03-28 |
JP4037472B2 (ja) | 2008-01-23 |
EP0741416A1 (en) | 1996-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4037472B2 (ja) | グラウンドポテンシャルに接続されていないソース又はドレーンを有するHVp−チャンネル及びn−チャンネルデバイスを含む薄いエピタキシャルRESURF集積回路 | |
JP3425967B2 (ja) | 低濃度にドープされたドレインを有するラテラルmos電界効果トランジスタ及びその製造方法 | |
US6825531B1 (en) | Lateral DMOS transistor with a self-aligned drain region | |
US8652930B2 (en) | Semiconductor device with self-biased isolation | |
US6858500B2 (en) | Semiconductor device and its manufacturing method | |
US6833586B2 (en) | LDMOS transistor with high voltage source and drain terminals | |
JP3523056B2 (ja) | 半導体装置 | |
US6864533B2 (en) | MOS field effect transistor with reduced on-resistance | |
US9390983B1 (en) | Semiconductor device and method for fabricating the same | |
US8022506B2 (en) | SOI device with more immunity from substrate voltage | |
JPH09266248A (ja) | 半導体装置 | |
US20100163990A1 (en) | Lateral Double Diffused Metal Oxide Semiconductor Device | |
US7173308B2 (en) | Lateral short-channel DMOS, method for manufacturing same and semiconductor device | |
US7180158B2 (en) | Semiconductor device and method of manufacture | |
US8115273B2 (en) | Deep trench isolation structures in integrated semiconductor devices | |
JP2002158353A (ja) | Mos電界効果トランジスタ | |
US10217828B1 (en) | Transistors with field plates on fully depleted silicon-on-insulator platform and method of making the same | |
US20070090454A1 (en) | Transistor device | |
US5604369A (en) | ESD protection device for high voltage CMOS applications | |
US7244989B2 (en) | Semiconductor device and method of manufacture | |
US20230246068A1 (en) | Field effect transistor having a dielectric structure | |
US11735657B2 (en) | Method for fabricating transistor structure | |
JP3191285B2 (ja) | 半導体装置及びその製造方法 | |
JP3821799B2 (ja) | 閾値制御装置およびその動作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051102 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051122 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060222 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060509 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20060808 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20060811 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061101 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20071002 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20071101 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101109 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101109 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111109 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111109 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121109 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |