JPH0830548A - Data collision preventing device - Google Patents

Abstract

PURPOSE:To provide a data collision preventing device capable of preventing the collision of data even at the time of CPU runaway and having simple constitution. CONSTITUTION:The data collision preventing device in a system connecting plural I/O devices to a data bus and executing data transfer based upon a transfer setting signal and a transfer start signal outputted from a CPU 5 is provided with an identification(ID) signal output means for outputting I/O setting ID signals F1 to F4 for setting up outputs or inputs in respective I/O devices 1 to 4 based upon the transfer setting signal from the CPU 5 and transfer start signal invalidating means 11, 12 for judging whether two output settings or more exist or not based upon the signals F1 to F4 to all the I/U devices 1 to 4, and when two output settings or more exist, invalidating the transfer start signal outputted from the CPU 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data collision preventing device in a system in which a plurality of input / output devices are connected to a data bus.

[0002]

2. Description of the Related Art In a system in which a plurality of input / output devices are connected to a data bus such as an image processing device,
The data bus is controlled by hardware or software.

When the data bus is controlled by software, the CPU 100 manages the data bus as shown in FIG. The input / output control of data of the input / output device 200 connected to the data bus is performed by the CPU 1
00 to the input / output device 200 by a data transfer command.

When the data bus is controlled by hardware, a bus control section 301 is provided in the input / output device 300 connected to the data bus, as shown in FIG. Bus control unit 30 provided in the input / output device 300
When outputting data from the input / output device 300 to the data bus, 1 determines whether or not the data bus is currently used, and if not, outputs the data to the data bus.

[0005]

In the method of controlling the data bus by software as described above, the CP
At the time of U runaway, data collision may occur due to the data being output from the plurality of input / output devices to the data bus.

In the method of controlling the data bus by hardware as described above, data collision can be prevented even when the CPU runs out of control, but the configuration of the bus controller becomes complicated and the circuit scale increases as the number of data buses increases. There is a problem that becomes large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data collision prevention device which can prevent data collision even when the CPU runs out of control and has a simple structure.

[0008]

A data collision preventing device according to the present invention has a plurality of input / output devices connected to a data bus and performs data transfer based on a transfer setting signal and a transfer start signal from a CPU. A data collision prevention device in a system, which outputs an input / output setting identification signal indicating whether the transfer setting is an output setting or an input setting for each input / output device based on a transfer setting signal from a CPU. Based on the identification signal output means and the input / output setting identification signals of all the input / output devices, it is determined whether or not there are two or more output settings. When there are two or more output settings,
A transfer start signal invalidating means for invalidating the transfer start signal output from the CPU is provided.

[0009]

According to the transfer setting signal from the CPU, the input / output setting identification signal indicating whether the transfer setting is output setting or input setting is output for each input / output device. Then, based on the input / output setting identification signals of all the input / output devices, it is determined whether or not the output setting is 2 or more. When the output setting is 2 or more, the transfer start signal output from the CPU is invalidated. It

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the configuration of a system provided with a data collision prevention circuit.

In this system, four input / output devices 1, 2, 3, 4 are connected to the data bus 10. These four input / output devices 1, 2, 3, 4 are controlled by the CPU 5. This system has a carry determination circuit 1
A data collision prevention circuit including 1 and a three-state buffer 12 is provided.

When data is transferred from one input / output device to another one, the CPU 5 sends a transfer setting signal to both the input / output devices, and then the transfer start signal from the CPU 5 is three-stated. It is output via the buffer 12. When the transfer start signal from the CPU 5 is sent to the input / output device on the data output side, the data transfer is started.

Each of the input / output devices 1 to 4 outputs data (output setting) or inputs data (input setting).
I / O setting flags F1 to F4 for identifying Each of the input / output setting flags F1 to F4 is in the reset state when the transfer setting signal is the transfer setting signal of the input setting.
When the transfer setting command is the output setting transfer setting signal, the set state is "1". The input / output setting flags F1 to F4 are normally in the reset state "0".

Input / output setting flag F of each of the input / output devices 1 to 4
Information about 1 to F4 is input to the carry determination circuit 11. As a result of adding the information on the input / output setting flags F1 to F4, the carry determination circuit 11 outputs a signal "0" when there is no carry, and adds the information on the input / output setting flags F1 to F4. As a result, when there is a carry, the signal "1" is output.

That is, the four input / output setting flags F1 to F
In combinations of four states, when two or more flags are in the set state "1", the output of the carry determination circuit 11 is "1", and in other combinations, the output of the carry determination circuit 11 is "1". It becomes 0 ".

The output of the carry determination circuit 11 is sent to the three-state buffer 12 as a transfer start enable signal. Therefore, the transfer start signal from the CPU 5 is
Only when the output of the carry determination circuit 11 is “0”, it is sent to the input / output devices 1 to 4 through the three-state buffer 12. On the contrary, when the output of the carry determination circuit 11 is "1", even if the transfer start signal is output from the CPU 5,
The transfer start signal is not sent to the input / output devices 1 to 4.

In the configuration as described above, the input / output device 1
The operation when data is transferred from the input / output device 2 will be described.

All the input / output setting flags F1 to F4 are "
It is assumed that the transfer setting signal for output setting is sent from the CPU 5 to the input / output device 1, and the CPU 5 sends input / output device 2 to the input / output device 2 for input setting. The transfer setting signal is sent, whereby the input / output setting flag F1 of the input / output device 1 is set to "1", and the input / output device 2 releases the input port. Of the input / output setting flags F1 to F4,
Since only one input / output setting flag F1 is set to "1", the output of the carry determination circuit 11 is "0".

Thereafter, the CPU 5 outputs a transfer start signal. This transfer start signal is sent to the input / output device 1 via the three-state buffer 12. When the transfer start signal is sent to the input / output device 1, the data is output from the input / output device 1 to the data bus 10 and transferred to the input / output device 2 via the data bus 10. When the data transfer is completed, the input / output device 1 resets the input / output setting flag F1 to "0", and the input / output device 2 closes the input port.

It is assumed that the CPU 5 runs away during the data transfer from the input / output device 1 to the input / output device 2 and a transfer setting signal for output setting is sent to the input / output device 3. In this case, the input / output setting flag F3 of the input / output device 3 is set to "1". Then, the two input / output setting flags F1 and F3 become "1", and the output of the carry determination circuit 11 becomes "1". Therefore, even if the CPU 5 outputs the transfer start signal thereafter, the transfer start signal is locked by the three-state buffer 12, and the transfer start signal is not sent to the input / output device 3. As a result, data collision is prevented in advance.

FIG. 2 shows a concrete example of the carry determination circuit 11 when there are four input / output devices. In the specific example of FIG. 2, the carry determination circuit 11 includes two exclusive OR circuits 21, 22 and three AND circuits 23, 24, 25.
It is composed of one OR circuit 26. When both the input / output setting flags F1 and F2 are "1", the output of the AND circuit 23 becomes "1" and the output of the OR circuit 26 becomes "1". When both the input / output setting flags F3 and F4 are "1", the output of the AND circuit 25 becomes "1" and the output of the OR circuit 26 becomes "1".

When only one of the input / output setting flags F1 and F2 is "1" and only one of the input / output setting flags F3 and F4 is "1", both exclusive ORs are performed. The outputs of the circuits 21 and 22 are both "1".
Therefore, the output of the logical product circuit 24 becomes "1" and the output of the logical sum circuit 26 becomes "1". Therefore, if two or more of the input / output setting flags F1 to F4 are "1", the output of the OR circuit 26 is "1". When all the input / output setting flags F1 to F4 are "0" or when only one of the input / output setting flags F1 to F4 is "1", the output of the OR circuit 25 becomes "0".

In the above embodiment, the case where there are four input / output devices connected to the data bus has been described. However, in the case of a system in which a plurality of input / output devices are connected to the data bus, the number of input / output devices is increased. This invention can be applied regardless of.

According to the above embodiment, by providing the data collision prevention circuit having a simple structure, it is possible to prevent the data collision even when the CPU is out of control.

[0025]

According to the present invention, it is possible to obtain a data collision preventing device which can prevent data collision even when the CPU is out of control and has a simple structure.

[Brief description of drawings]

FIG. 1 is an electrical block diagram showing a configuration of a system provided with a data collision prevention circuit.

FIG. 2 is an electric circuit diagram showing a specific example of the carry determination circuit of FIG.

FIG. 3 is an electric block diagram showing a conventional example in which a data bus is controlled by software.

FIG. 4 is an electrical block diagram showing a conventional example in which a data bus is controlled by hardware.

[Explanation of symbols]

 1, 2, 3, 4 Input / output device 5 CPU 10 Data bus 11 Carry determination circuit 12 Three-state buffer

Claims (1)

[Claims] 1. A data collision prevention device in a system in which a plurality of input / output devices are connected to a data bus, and data is transferred based on a transfer setting signal and a transfer start signal from the CPU. Identification signal output means for outputting an input / output setting identification signal indicating whether the transfer setting is output setting or input setting for each input / output device based on the transfer setting signal of A transfer start signal invalidating unit that determines whether or not the output setting is 2 or more based on the output setting identification signal, and invalidates the transfer start signal output from the CPU when the output setting is 2 or more. Data collision prevention device.