JPH05173949A - Microprocessor device - Google Patents

Abstract

PURPOSE:To reduce the device scale by eliminating a need of a buffer and an external input terminal for input of a signal BFLT which are conventionally required among a microprocessor and data and address buses. CONSTITUTION:A bus use request arbitrating circuit 38 receives bus use request signals BRQ0 to BRQ3 from peripheral devices 31, 32, and 33 and a microprocessor 39 and arbitrates the bus use requests in accordance with arbitrarily set priority levels to determines, the bus use right. Thereafter, one of bus use right permission signals BAK0 to BAK3 is outputted. The peripheral device which receives this outputted bus use right permission signal uses a data bus 35 and an address bus 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor device used in a computer or the like to release a micro data bus and an address bus to peripheral devices.

[0002]

2. Description of the Related Art In a conventional microprocessor device, a processing of a control unit enables a connected peripheral device to use a data bus and an address bus. In this case, when a hold request signal (hereinafter referred to as a HOLD signal as necessary), which is a request signal for the microprocessor to release the data bus and the address bus, is input, a break in the machine cycle causes the microprocessor to fail. The processing operation is suspended, and the data bus and address bus are put in the floating state. Further, a hold acknowledge signal (hereinafter, referred to as a HOLDA signal as necessary) is output as a response signal to the HOLD signal input, and the peripheral device recognizes the validity of the HOLDA signal and then releases the released data bus and address bus. I have been using it for the required time. After that, the HOLD signal is invalidated and the data bus and address bus are released to the microprocessor.

When the data bus and the address bus are released in this manner, the machine cycle after the operation arbitration control inside the microprocessor is carried out after the HOLD signal is inputted and the condition for the proper internal operation end is satisfied. The data and address buses are not released until the break. Therefore, in the connected peripheral device, the time from when the bus release request is sent to when the bus is actually released is not constant, but changes depending on the internal operation of the microprocessor.

By the way, it is necessary to minimize the bus acquisition waiting time in the connection peripheral device which processes the acquisition of the bus at a constant cycle and in the connection peripheral device which has the processing priority over the microprocessor. Furthermore, regardless of the operating state inside the microprocessor, a system design that takes into consideration the maximum value of the bus acquisition wait time in each peripheral device calculated from the processing priority among a plurality of connected peripheral devices is required.

Therefore, as shown in FIG. 5, the bus use request from the microprocessor 30 and the peripheral devices 31, 3 are provided.
A bus use request arbitration circuit 38 arbitrates the bus use request from the busses 2 and 33 to determine the bus use right. in this case,
While the peripherals 31, 32 and 33 have acquired the bus, the data bus 35 and the address bus 34 are not in the floating state. Therefore, the microprocessor 3
Between 0 and the data bus 35 and address bus 34,
Drive buffer 36, drive / receive buffer 3
7 is provided to control the drive buffer 36 and the drive / receive buffer 37 to be in a floating state.

[0006]

As described above, in the conventional microprocessor device, the drive buffer 36 for the data bus and the address bus and the drive / receiver buffer 37 are required outside the microprocessor 30, and the bus floating is required. It is necessary to provide an external input terminal for inputting a request signal (hereinafter referred to as a BFLT signal, if necessary), which has a disadvantage of increasing the device scale.

An object of the present invention is to solve such problems and to provide a buffer and a BFL which are conventionally required between a microprocessor and a data bus and an address bus.
An object of the present invention is to provide a microprocessor device capable of reducing the device scale by eliminating the need for an external input terminal for inputting a T signal.

[0008]

In order to achieve this object, the present invention has at least an arithmetic unit, a register unit and a control unit, and separates a data bus and an address bus from a microprocessor, and In response to the input of the hold request signal for requesting disconnection of the address bus, the operation of the microprocessor is interrupted at the break of the machine cycle to make the data bus and address bus floating, and as a response signal to the hold request signal. In a microprocessor device which outputs a hold acknowledge signal, in addition to a hold request signal to be input, a bus floating request signal input means and a bus floating request signal input means for immediately setting a data bus and an address bus into a floating state independently of the operation of the microprocessor. It is characterized in further comprising a floating control means.

Further, there is provided a bidirectional signal input processing means and a bus floating control means for carrying out the hold acknowledge signal output processing and the bus floating request signal input processing together.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a microprocessor device of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the first embodiment. The first embodiment corresponds to claim 1.

In FIG. 1, this example has an arithmetic unit 1, a control unit 2, and a register unit 3. The arithmetic unit 1, the control unit 2, and the register unit 3 are connected by an internal data bus 4, and are connected by a data bus 6 to an external device (not shown).
A bus floating control circuit 7 is provided inside the control unit 2.

Next, the operation of the configuration of the first embodiment will be described.

An address is output from the register unit 3, and this address is output to the outside through the address bus 5. The bus floating control circuit 7 of the control unit 2 has a HO
Address bus driver enable signal (enable by 1 and disable by 0) which is a control signal for inputting the LDA signal S8 and the BFLT signal S9 to make the data bus 6 and the address bus 5 in a floating state.
It outputs S14 and a data bus driver enable signal (1 is enabled, 0 is disabled) S20.
Further, a data bus / receiver enable signal (1 is enabled, 0 is disabled) S25 is output.

FIG. 2 shows in detail the processing contents of the control unit 2.

1 and 2, the timing control unit 1
As one process of No. 2, the HOLD signal is received to arbitrate the internal operation, the internal operation is interrupted at the break of the machine cycle, and the HOLD signal is output. The bus floating control circuit 7 sets the output of the 2-input AND gate 13 to the low (L) level when the HOLDA signal S8 is at the effective polarity low (L) level. The output enable signals of the data bus 6 and the address bus 5 are set to the low (L) level to be in the floating state. In addition, the BFLT signal S
Similarly, when 9 has the effective polarity low (L) level, the data bus 6 and the address bus 5 are in the floating state.

FIG. 3 shows the configuration of the second embodiment. The second embodiment corresponds to claim 2.

In FIGS. 1, 2 and 3, when the HOLDA signal S8 output from the timing control section 12 in FIG. 3 is at the effective polarity low (L) level, the output enable signal of the driver 16 is output by the inverter 15. Becomes effective,
A low (L) level signal is output to the terminal 19. This signal is received by the receiver 17, and the output enable signal of the data bus 6 and the address bus 5 is added to the output signal S14,
By outputting S20 and S25, the data bus 6 and the address bus 5 are brought into a floating state. Further, even if the BFLT signal S9 input from the terminal 19 is in the effective polarity low (L) level, the data bus 6 and the address bus 5 are also in the floating state.

FIG. 4 shows a system configuration using the microprocessor 39 based on the above configuration.

In FIG. 4, peripheral devices 31, 32, 33
Is a bus master that acquires the data bus 35 and the address bus 34, and is a competing partner for acquiring the bus with the microprocessor 39.

The bus use request arbitration circuit 38 is used by the peripheral device 3
1, 32, 33 and bus use request signals BRQ0, BRQ1, BRQ2, BRQ from the microprocessor 39
In response to 3, the bus use request is arbitrated according to the priority order arbitrarily set, and the bus use right is determined. After this, the bus use right permission signals BAK0, BAK1, BAK2, BA
Any one of K3 is output. The peripheral device receiving the bus use right permission signal (BAK0, BAK1, BAK2, BAK3) receives the data bus 35 and the address bus 34.
To use. In the bus use request arbitration circuit 38, after the ADS (Address Strobe) signal of the start trigger of the machine cycle is received from the microprocessor 39, the bus use right is acquired and the bus use right permission signal BAK3 is set to the valid polarity high (H). ) Leave the RDY signal to the microprocessor 39 disabled until it goes to level. Further, after the machine cycle in the microprocessor 39 is set in the wait state, the bus use right permission signal BAK3 becomes the effective polarity high (H) level, and after the values on the data bus 35 and the address bus 34 are fixed, the bus access defined by the system is performed. The RDY signal is output to the microprocessor 39 at a timing suitable for the cycle.

[0022]

As is apparent from the above description, in the microprocessor device of the present invention, the data bus and address bus of the microprocessor are immediately set to the floating state regardless of the operation inside the microprocessor. The buffer and B required between the microprocessor and the data bus and address bus
An external input terminal for inputting the FLT signal is not required, and the device scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microprocessor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing details of processing contents of a control unit in FIG.

FIG. 3 is a circuit diagram showing a configuration of a second exemplary embodiment.

FIG. 4 is a block diagram showing a configuration of a microprocessor system using a microprocessor to which the first and second embodiments are applied.

FIG. 5 is a block diagram showing a configuration of a conventional microprocessor device.

[Explanation of symbols]

 1 arithmetic unit 2 control unit 3 register unit 4 internal data bus 5 address bus 6 data bus 7 bus floating control circuit 31, 32, 33 peripheral device 34 address bus 35 data bus 38 bus use request arbitration circuit 39 microprocessor

Claims (2)

[Claims] 1. A hold request signal for inputting a hold request signal for disconnecting a data bus and an address bus from a microprocessor, which has at least an arithmetic unit, a register unit, and a control unit. On the other hand, in the microprocessor device which suspends the operation of the microprocessor at the break of the machine cycle to make the data bus and the address bus in a floating state and outputs a hold acknowledge signal as a response signal to the hold request signal, In addition to the hold request signal, a bus floating request signal input means and a bus floating control means for immediately setting the data bus and the address bus into a floating state independently of the operation of the microprocessor are provided. A microprocessor device. 2. A microprocessor device according to claim 1, further comprising a bidirectional signal input processing means and a bus floating control means for performing both a hold acknowledge signal output processing and a bus floating request signal input processing.