JP2893033B2 - DMA channel identification control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a DMA channel identification control method for identifying a channel of transfer data by DMA, even in a case where data of a plurality of channels is DMA-corresponding to a channel, identification of a channel correspondence in the DMA. To facilitate character detection, DMA transfers data between the memory and the communication control unit with multiple channels without using a processor.
In a method of controlling by a control unit and detecting a specific character in transfer data by a character detection unit, data is controlled by a channel corresponding address in which the memory area is allocated to each channel and controlled by the DMA control unit. An address comparing unit for comparing an address of the memory on the bus to be transferred; and identifying a channel during data transfer based on an address comparison result by the address comparing unit.
It is configured to notify the character detection unit.

[Industrial applications]

The present invention relates to a DMA channel identification control method for identifying a channel of transfer data by DMA.

In communication between personal computers (usually abbreviated as “PC”; this abbreviation is used hereinafter),
For example, line feed (LF) included in transmitted / received data
The transmission / reception data is processed by detecting a specific character indicating a control code such as a carriage return (CR) or the like. Therefore, if the processor reads every character in the transmission / reception data and identifies whether the character is a specific character or not, the burden on the firmware increases. Therefore,
A configuration in which relatively simple hardware is provided to detect a specific character has been proposed.

Also, in a DMA transfer for transferring data between a communication control unit having a plurality of channels and a memory without the intervention of a processor, it is necessary to detect a specific character corresponding to a channel. Need to identify the channel.

[Conventional technology]

In order to detect a specific character such as a line feed (LF) and a carriage return (CR), for example, a configuration shown in FIG. 4 has been proposed. In the figure, 31, 32 are registers for setting specific characters, 33 is a comparison circuit, 34
Is a latch circuit, and 35 is a data bus.

A processor, a communication controller, a memory, and the like (not shown) are connected via a data bus 35, and registers 31, 3
In 2, specific 1-byte character data to be detected under the control of the processor is set, and the data set in the registers 31 and 32 and the data transferred via the data bus 35 are compared in the comparison circuit 33. The specific character is detected by the comparison and the comparison match, and the detection signal is latched by the latch circuit 34 to be an interrupt signal to the processor.

It is also possible to detect not only a specific character of one byte but also a specific character of two bytes in which different specific characters are continuous.

Therefore, the processor does not need to identify whether the character is a specific character or not for each character, so that the burden on the firmware is reduced.

[Problems to be solved by the invention]

As described above, when transmitting and receiving data of a single channel, by providing the specific character detection unit shown in FIG. 4, the burden on the firmware is increased without increasing the load on the firmware.
A specific character can be detected. Also, when transmitting and receiving data of a plurality of channels, a specific character detection unit may be provided for each channel. However, when data is transferred between the communication control device and the memory without the intervention of the processor, even if the processor can identify which channel is used for the communication, the data being DMA-transferred is transmitted to which channel. It is something that cannot be identified.

Therefore, even if a specific character can be detected by relatively simple hardware, it is difficult to detect a specific character corresponding to a channel when transmitting and receiving data of a plurality of channels.

The present invention is designed to convert data of multiple channels
Even when A is performed, it is intended to easily detect a specific character corresponding to a channel in DMA.

[Means for solving the problem]

The DMA channel identification control method of the present invention identifies a channel using an address at the time of DMA transfer.
This will be described with reference to the drawings.

The data transfer via the bus 7 between the memory 2 and the communication control unit 3 having a plurality of channels is controlled by the DMA control unit 4 without the intervention of the processor 1, and the line feed (LF) and the carriage in the transfer data are controlled. In a method in which a specific character such as a return (CR) is detected by the character detection unit 5, an area of the memory 2 is allocated corresponding to each channel, and the address of the area corresponding to this channel and the control of the DMA control unit 4 are used. An address comparing unit 6 for comparing an address of the memory 2 on a bus 7 for transferring data is provided, a channel during data transfer is identified based on a comparison result in the address comparing unit 6, and the identified channel is detected by a character. It has a configuration for notifying the unit 5.

[Action]

The memory 2 is allocated an area corresponding to the channel,
The communication control unit 3 has a configuration capable of transmitting and receiving data of a plurality of channels, and the DMA control unit 4 transfers data between the communication control unit 3 and the memory 2 without using the processor 1. Is performed via

The character detection unit 5 has a configuration capable of detecting a specific character corresponding to a channel, and the address comparison unit 6
A configuration for comparing upper bits of an address capable of identifying an area of the memory 2 assigned to each channel,
The control unit 4 compares the address of the memory 2 in the DMA with the address of a preset area of the memory 2 corresponding to the channel, and identifies the channel in the DMA. The result is notified to the character detection unit 5. Thereby, the character detection unit 5 can easily detect the specific character corresponding to the channel.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a processor such as a microprocessor, 12 is a memory, 13 is a communication control unit, 13A and 13B are channel correspondence units, 14 is a DMA control unit,
Reference numeral 15 denotes a character detection unit, 15A and 15B denote detection units corresponding to channels, 16 denotes an address comparison unit, 17 denotes a bus, 18 and 19 denote registers for setting addresses, and 20 denotes a comparison circuit.

This embodiment shows a case where transmission and reception of two channels of data are enabled. Therefore, areas A and B are allocated to the memory 12, a channel controller 13A and 13B are provided in the communication controller 13, and a character detector 15 is provided. Are provided with detection units 15A and 15B corresponding to channels. In addition, when the address of the memory 12 has a 24-bit configuration, and the areas A and B are each 64 Kbytes in hexadecimal notation, the start address of the area A is "200000" and the start address of the area B is "210000". Show the case. In this case, under the control of the processor 11, the upper 8 bits of the head address of the areas A and B are transmitted via the bus 17 to the address comparing section 16.
Are set as "20" and "21" in hexadecimal notation in registers 18 and 19, respectively.

From the communication control unit 13 to the processor 11, the channel handling unit 13
When the data is received by A and 13B, the processor 11 activates the DMA controller 14 from the processor 11. Thereby, DMA
The DMA signal dma is added from the control unit 14 to the comparison circuit 20 of the address comparison unit 16, and the comparison circuit 20 compares the upper 8 bits of the address set in the registers 18 and 19 with the upper 8 bits on the bus 17.
Start comparing bit with address add.

For example, when the address on the bus 17 specified by the DMA control unit 14 is “20 ××××”, the upper 8 bits of the address become equal to the upper 8 bits of the address set in the register 18. Identification signal of channel A from 20
cha is output and added to the detection unit 15A corresponding to channel A of the character detection unit 15, and this detection unit 15A
A specific character in the above data is detected, and the detection signal caa is applied to the processor 11 as an interrupt signal. Similarly, when the address on the bus 17 is “21 × xxx”, it becomes equal to the upper 8 bits of the address set in the register 19, so that the comparison circuit 20 outputs the channel B identification signal chb. Is applied to a detection unit 15B corresponding to channel A of the character detection unit 15. The detection unit 15B detects a specific character in the data on the bus 17, and the detection signal cab is applied to the processor 11 as an interrupt signal. Can be

FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention.
Is the data of channel A, the data of channel B in (b),
(C) is the DMA signal dma, and (d) is the channel A identification signal.
cha and (e) show the identification signal chb of channel B.

In the DMA transfer mode, the in-DMA signal dma is applied from the DMA control unit 14 to the address comparison unit 16 as shown in (c), and the address comparison is performed by the comparison circuit 20 of the address comparison unit 16 ( The identification signals cha and chb of the channels A and B shown in d) and (e) are applied to the detection units 15A and 15B corresponding to the channels of the character detection unit 15, and the specific characters corresponding to the channels are detected. MPU (microprocessor)
In the transfer mode, the data is transferred via the bus 17 under the control of the processor 11 and the DMA control unit 14 does not operate, so that the in-DMA signal dma is not transmitted. Accordingly, the operation of the comparison circuit 20 of the address comparison unit 14 is also stopped.

The above-described embodiment shows the case of the DMA transfer of two channels. However, the number of channels can be further increased, and the area of the memory 12 is divided according to the number of channels, and the divided area is divided corresponding to the channel. Is assigned, and the upper bits of the address that can identify each area are set in the register of the address comparison unit 16 corresponding to the channel.

〔The invention's effect〕

As described above, according to the present invention, the address of the channel corresponding to the channel 2
The address comparison unit 6 compares the address of the memory 2 on the bus 7 when data is transferred under the control of the control unit 4, and the channel identification signal is obtained when the comparison is made. Notify to
A specific character can be detected for each channel. Therefore, there is an advantage that the channel identification by software becomes unnecessary, the processing load on the processor 1 is reduced, and a specific character can be easily detected when transmitting and receiving data of an arbitrary number of channels.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG.
FIG. 4 is a main block diagram of the specific character detection unit. 1 is a processor, 2 is a memory, 3 is a communication control unit, 4 is a DM
A control unit, 5 is a character detection unit, 6 is an address comparison unit, and 7 is a bus.

Continuation of front page (56) References JP-A-57-90745 (JP, A) JP-A-63-308657 (JP, A) JP-A-60-29862 (JP, A) JP-A-51-101432 (JP, A) , A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 13/00 G06F 13/12-13/14 G06F 13/28 G06F 13/38

Claims (1)

(57) [Claims] A data transfer via a bus (7) between a memory (2) and a communication control unit (3) having a plurality of channels without the intervention of a processor (1) is performed by a DMA control unit (4).
And an address corresponding to a channel in which an area of the memory (2) is allocated corresponding to each channel, and wherein the DMA is used to detect a specific character in transfer data by a character detection unit (5). An address comparison unit (6) for comparing an address of the memory (2) on the bus (7) for transferring data under the control of the control unit (4) is provided, and an address comparison result by the address comparison unit (6) A channel for which data is being transferred, and notifies the character detection unit (5) of the channel.