JP3211267B2 - Access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access control system for controlling a main storage device by generating an access request according to an access command in a vector processing device or the like. In the case of a vector processing device used for supercomputers,
In order to speed up access to the main storage device by a vector instruction, two access request generators of port A and port B are used.

With respect to these two access request generation units, in a block access for accessing a plurality of continuous elements (the vector length may be 1) in the main memory, a load access request is made from a port A, and a store access request is made from a port. I have decided to start from B. On the other hand, for random access for accessing a plurality of elements distributed in the main memory, both of the ports A and B can be used for both the load access and the store access, and the elements are alternately used by using the ports A and B. Access requests are generated in ascending order.

Further, for random access, for example, a rule for determining the order in which access requests are sent to the access request processing unit in the order of ports A to B is determined, and even if two random access requests occur at the same time, the order of instructions is changed. So that they can be maintained. However, if the final signal F indicating the last element is added to the access request of port A, the access request of port A is given priority regardless of the random access request of port B.

However, when a block access request is generated at port B by a preceding store access instruction, and a random access request for accessing a single element at port A is generated by a subsequent store instruction having a vector length = 1, Final signal F indicating that it is the last element because it is an access of one element
Is added, and the random access request of the A port by the subsequent instruction is prioritized, and the execution order of the instructions cannot be guaranteed.

Therefore, even if a specific condition for generating a random access request having a vector length of 1 at port A occurs, it is desired to perform processing that does not give priority to a preceding block access request.

[0006]

2. Description of the Related Art FIG. 9 shows a conventional vector processing apparatus, which comprises an access request generating unit 10, an access request rank determining unit 12, a load access request processing unit 14, and a store access processing unit 16. Note that the load access request processing unit 14 and the store access processing unit 16 are integrated into an access control unit 18.

The access request generator 10 includes a port A access request generator 10A and a port B access request generator 10 which function as first and second access request generators.
B is provided. First, there are two types of access methods for the vector instruction executed by the vector processing device of FIG. 9, that is, block access and random access.

[0008] The block access is a process of accessing a plurality of elements existing at consecutive addresses in the main storage device. On the other hand, in random access, the vector length =
This is a process for sequentially accessing a plurality of elements existing at distributed addresses in the main storage device by two or more access instructions. The random access includes a process of accessing only one element existing at a single address in the main storage device by an access instruction having a vector length = 1.

The rules for using ports that generate access requests for performing such block access and random access are determined as follows. When performing a block access, the port A access request generator 10A is used for a load instruction, and the port B access request generator 10B is used for a store instruction.

When random access is performed, both the port A and port B access request generators 10A and 10B are used regardless of the load instruction and the store instruction, and the port A to the port B are used in ascending order of the element. Access requests are generated alternately as described above. The access request order determination unit 12 generates an access request when a random access request is received from both the access request generation units 10A and 10B of the port A and the port B in order to guarantee the order of elements at the time of random access. Parts 10A, 10B
Access request processing unit 18 (load access processing unit 14 or store access processing unit 16)
Send to

However, if an access request is issued to both the port A and the port B and the final request F indicating the last element is added to the access request on the port A side, the access by the access request generator 10A of the port B is performed. Regardless of the request, the access request of port A is sent to the access request processing unit 18 with priority.

[0012]

However, in such an access control method in a conventional vector processing apparatus, a preceding instruction; a block access request by a store access instruction B having a plurality of vector lengths; a subsequent instruction; If the request is a random access request by the store access instruction A, the access request order determination unit 12 cannot distinguish the access request of the preceding store access instruction B from the access request of the subsequent store access instruction A, and cannot guarantee the execution order of the instructions. There is fear.

FIG. 10 is specifically explained. First, in the case of a preceding block access, eight pieces of vector data are handled for one access. Therefore, in this case, the port B
The access request generator 10B receives two access requests “S ^B
_1, ^F S ^B ₂ "was generated, the vector length to be followed at the same time =
It is generated an access request added with the final signal F ^"F S ^A _1" indicating that the port A access request generating section 10A is the last element by one of the store access instruction A.

In this case, the port A access request generator 1
Since 0A is not set the access request ^"F S ^A _1" and priority rules by adding a final signal F generated,
Access request subsequent instructions A ^"F S ^A _1" is would be sent first to the store access request processing section 16, the order of execution of the access instruction can not be guaranteed. In order to guarantee the execution order of the instructions in this case, the port A access request generation unit 1
It is necessary to prevent an access request subsequent vector length = 1 store access instruction A ^"F S ^A _1" in 0A. However, in order to prevent the access request ^"F S ^A _1", the port A access request generating section 10A is need to monitor the status of the port B access request generating unit 10B, the control becomes complex high-speed processing Is no longer possible.

The present invention has been made in view of such a conventional problem, and when a specific instruction condition in which the execution order of an access instruction cannot be guaranteed occurs, the execution order is assured by a simple control to achieve high speed. An object of the present invention is to provide an access control method capable of performing processing.

[0016]

FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention provides at least two first and second access request generators 10A, 10A, which generate a store access request to a main storage device in response to a store access command.
10B and the first and second access request generation units 10A, 1
An access request rank determining unit 12 that determines the processing order of two or more store access requests generated in 0B, and executes a store access to the main storage device in response to a store access request according to the determination order of the access request rank determining unit 12. And a second access request is generated for a block access request for sequentially accessing a plurality of data (a plurality of elements) continuously present in the main storage device when a store access instruction is received. Department only
Sends the access request to the access request processing unit, and the first and second random access requests for sequentially accessing a plurality of data distributed in the main storage device.
Both access requests from the access request generator are
Request to the request processing unit, and the access request of the first access request generation unit.
Request contains a final signal indicating the last element.
The access request from the second access request generator
Regardless, the access request from the first access request generation unit
An access control method which is preferentially transmitted to the access request processing unit is targeted.

According to the present invention, the second access request generation unit generates a block access request according to a preceding store access instruction, and generates a first access request according to a store access instruction following the preceding instruction. When a random access request having one data length is generated by the generation unit, addition of a final signal indicating final data to the random access request generated by the first access request generation unit is suppressed, and a final signal is transmitted to the second access request generation unit. A dummy access request to which a signal has been added is generated, and the access request rank determining unit waits for the random access request of one data length when receiving the random access request of one data length, processes the preceding instruction, and then executes the dummy access request. When a random access request with one data length is And wherein the sending the scan request processing section.

Further , in the present invention, the access request processing unit, when receiving the dummy access request generated by the second access request generation unit, suppresses execution of the dummy access request.

Further, in the present invention, the access request processing unit is characterized in that the execution of the dummy access request is suppressed by receiving the invalid flag added to the dummy access request by the access request generation unit.

[0020]

[0021]

According to the access control apparatus of the present invention having such a configuration, the following operation can be obtained. In the present invention,
When a specific condition that a random access request is generated by a store access instruction with a vector length = 1 is obtained,
A process of forcibly changing an access request by a store access instruction with a vector length of 1 to an access request by a store access instruction with a vector length of 2 is performed so that a final signal F that disturbs the instruction order is not added.

That is, when the first access request generator 10A (port A side) receives a store access instruction with a vector length = 1, the second access request generator 10B (port B)
Side) generates a dummy access request and the vector length = 2
Change to Upon receiving the store access request “S ^A ₁ ” of the port A, the access request rank determining unit 12 recognizes that the access is a random access, and judges that it is not the last element because the final signal F is not added.
Port B dummy of random access request obtained by adding the final signal F to an access request from the ^"F S ^A _1" port A to come to wait for the "S ^A _1".

In the meantime, the preceding store
Access instruction B access request “S^B  ₁ , S^B _Two"
Access request processing unit 18 (store access request control unit 16)
To be sent to In this state, the port B store access
A's dummy access request^F S^A ₁ "
The access request “S^A ₁ "
To the access request processing unit 18.

Subsequently, the dummy access request “
^F S ^A ₁ "access request processing section 18 to performs no processing. In this way, the execution order from the store access instruction B that generates a block access request to the store access instruction A that generates a random access request and has a vector length of 1 is guaranteed.

[0025]

FIG. 2 is a block diagram showing an embodiment of a vector processing apparatus to which the access control method of the present invention is applied. 2, reference numeral 20 denotes an instruction control unit; 22, a main storage control device to which the access control method of the present invention is applied;
Is a main storage device. The command control unit 20 outputs a start signal for performing access processing to the main storage control device 22 based on the access command.

The main storage control unit 22 is provided with an access request generation unit 10, an access request order determination unit 12, a load access request processing unit 14, and a store access request processing unit 16. In this embodiment, the access request generator 1
0 is provided with two access request generators, that is, a port A access request generator 10A (first access request generator) and a port B access request generator 10B (second access request generator).

Control rules for generating access requests at the two port A and port B access request generators 10A and 10B are defined as follows. First, in a block access using an access instruction having a vector length of 2 or more for accessing a plurality of elements existing at consecutive addresses in the main storage device 24, if the instruction is a load instruction, the port A access request generation unit 10A issues a block access request. On the other hand, if it is a store instruction, the port B access request generator 10B generates a block access request.

Next, with regard to random access for accessing a plurality of elements existing at distributed addresses in the main storage device 24, the port A access request generation section 10A and the port B access request generation Both units 10B generate random access requests, and generate random access requests alternately from port A to port B in ascending order of elements.

For this random access, vector length = 1
If the vector length is 1, the final signal F indicating the last element is always added to the port A or port B access request generators 10A and 10B which are free at that time. Generate an access request. The access request order determination unit 12 loads both random access requests from the load access request processing unit 14 or the store access request in order to guarantee the element order of access requests from the port A and port B access request generation units 10A and 10B at the time of random access. The request is sent to the request processing unit 16. At this time, if the random access request is a random access request in which a final signal F indicating the last element is added to the random access request of the port A access request generation unit 10A, the access request rank determination unit 12 determines Regardless of the access request, the random access request of the port A access request generator 10A to which the final signal F is added is sent to the access request processor 24 with priority.

In addition to such an access control method in the vector processing device, according to the present invention, when the port A access request generation unit 10A recognizes a store access instruction with a vector length = 1, the store access instruction is The addition of the final signal F indicating that this is the last element to be added to the random access request generated based on this is forcibly suppressed, and the dummy access request to which the final signal F is added has already been generated at the port B at that time. An operation that occurs after the access request of the preceding instruction and forcibly changes the store access instruction with the vector length = 1 to the store access instruction with the vector length = 2 is performed.

By this processing, even if a random access request is generated in the port A access request generator 10A by a store access instruction with a vector length = 1, the processing is prevented from being processed earlier by an access request by a preceding store access instruction B. Then, the order of the store access instructions is guaranteed. Specifically, the access request rank determining unit 12 transmits a dummy access request to the store access request processing unit 16 when sending the random access request in which the addition of the final signal F of the port A access request generating unit 10A is suppressed to the store access request processing unit 16. Is inhibited from being sent to the store access request processing unit 16 on condition that an error has occurred.

While the transmission of the random access request from the port A access request generator 10A is suppressed, the preceding block access request from the port B access request generator 10B is transmitted to the store access request processor 16 with priority. Is done. When a dummy access request appears in the port B access request generation unit 10B, the access request rank determination unit 12 sends the random access request of the port A access request generation unit 10A, which has been suppressed until then, to the store access request processing unit 16. send.

Thus, the block access request by the preceding store access instruction and the subsequent vector length =
The order of the random access requests by one store access instruction is maintained, and the order of the store access instructions can be guaranteed. Further, a dummy access request is sent from the port B access request generation unit 10B to the store access request processing unit 16 via the access request order determination unit 12, and the storage access request processing unit 16 Therefore, no processing is performed on the dummy access request, and the processing of the dummy access request to the main storage device 24 becomes invalid.

Next, the operation of the embodiment of FIG. 2 will be described in detail with reference to FIGS. FIG. 3 shows a state in which the store access instruction A with a vector length of 1 is recognized by the port A access request generator 10A, and the port A access request generator 10A adds a final signal F indicating that it is the last element. random access request without "S ^A _1"
Occurs.

At this time, the port B access request generator 10
B is a preceding store access instruction B having a vector length = 2
Block access request generated by "S ^B _1", ^"F S
^B ₂ "has already been generated, and then to cause generating a dummy access request added with the final signal F" ^F S ^A ₁ ". Subsequently, as shown in FIG. 4, the random access request “S ^A generated in the port A access request generator 10A is generated.
₁ ”and the access request“ S ^B ₁ ”generated by the port B access request unit 10B are sent to the access request rank determination unit 12, and the access request rank determination unit 12 transmits the vector length 1 to the port A access request generation unit 10A. , And waits for transmission of the random access request “S ^A ₁ ” to the store access request processing unit 16.

Therefore, only the access request “S ^B ₁ ” generated in the port B access request section 10 ^B is sent to the store access processing section 16 and processed. It is subsequently delivered to the port B access request generating unit 10B in those blocks access request generated ^"F S ^B _2" sequentially sequential store access request processing unit 16 of the need advanced processing of the access request by accessing store instruction that .

As shown in FIG. 5 for the dummy access request to the port B access request generating section 10B ^"F S ^A
_At this time, the access request rank determining unit 12 recognizes the dummy access request “ ^{FS A} ₁ ” and sends the waiting random access request “S ^A ₁ ” to the store access processing unit 16. Process. Finally, as shown in FIG. 6, the dummy access request “ ^{FS A} ₁ ” generated in the port B access request generation unit 10 B is transmitted to the store access request processing unit 16 via the access request order determination unit 12.
In the store access request processing section 16, the port A access request generation section 10A sends the vector length = 1.
Recognizes a specific condition that store access instruction A of given dummy access request ^"F S ^A _1" without any processing for, access to the dummy access request ^"F S ^A _1" by the main storage device 24 Invalidated.

FIG. 7 is a block diagram of an embodiment showing a specific embodiment of the access request generator 10 of FIG. In FIG. 7, the access request generation unit 10 is the address generation control unit 2
6, an address generation unit 28, a stack control unit 30, and an access request stack unit 32.

The access request generator 10 is provided with an instruction controller 20
An instruction address is created by receiving a start signal based on an access instruction, and an access request is issued to the access request order determination unit 12. In the access control method according to the present invention, such an access request generation unit 10 determines that the access request is a final access request when the address generation control unit 26 detects a specific condition that the access instruction is a random store instruction and the vector length = 1. The random access request is stored in the access request stack unit 32 while the addition of the final signal F indicating this to the random access request is suppressed.

At the same time, regarding the generation of the access request on the port B side, a signal indicating the validity of the address generated for generating the dummy random access is sent to the stack control unit 20, and at the same time, a final signal is issued and sent. Thus, a dummy random access request with the final signal F added is stored in the access request stack unit 32 on the port B side.

FIG. 8 shows the load access request processing unit 1 shown in FIG.
4 is a specific example configuration diagram of an access request processing unit 18 having a function as a storage access request processing unit 4 and a store access request processing unit 16; FIG. 8, the access request processing unit 18 includes an access request processing control unit 34, a vector register 36, a mask register 38, a mask data register 40, an align I
It comprises a D generator 42 and a data aligner 44.

The access request processing control unit 34 receives the start signal from the instruction control unit 20, reads out the data from the vector register 36, and simultaneously reads the data from the mask register 3.
8 is transferred to the mask data register 40.
And the alignment circuit unit is controlled by the align ID generating unit 42 and the data aligning unit 44. In the access control method of the present invention, the access request processing control unit 34 sends a random access request of a store access instruction for performing a random access with a vector length = 1 to the port A.
When the specific condition that the request is generated by the access request generation unit 10A is detected, when the corresponding reference mask data is read from the mask register 38 in response to the dummy access request via the access request rank determination unit 12, the element of the reference mask data is deleted. Forced to 0.

In the align ID generating section 42, the mask register 3 read into the mask data register 40
If the element of the reference mask data from 8 is 0, an invalid signal is sent to the data alignment unit 44. For this reason,
Even if a dummy access request is received, the data stored in the vector register 36 at this time is prevented from being stored in the main storage device 20.

In the above embodiment, the access request generator is divided into two parts, port A and port B. However, in order to further speed up the access request processing,
Even when three or more ports are provided, the access control method of the present invention can be applied as it is.

[0045]

As described above, according to the present invention, when a random access instruction having a vector length = 1 is detected at a specific port, a dummy access request is issued to the other port and the vector length is changed to 2. , The processing order for the access request of the preceding block access instruction can be guaranteed, and monitoring and control between the two ports is unnecessary. Can control.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the access control of FIG. 2;

FIG. 4 is an explanatory diagram of the operation of the access control of FIG. 2 (continued)

FIG. 5 is an explanatory diagram of the operation of the access control of FIG. 2 (continued)

FIG. 6 is an explanatory diagram of the operation of the access control in FIG. 2 (continued)

FIG. 7 is a configuration diagram of an embodiment of an access request generator of FIG. 2;

8 is a configuration diagram of an embodiment of an access request processing unit in FIG. 2;

FIG. 9 is a configuration diagram of a conventional system.

FIG. 10 is an explanatory diagram of an operation of a conventional access control.

[Explanation of symbols]

10: access request generator 10A: first access request generator (port A access request generator) 10B: second access request generator (port B access request generator) 12: access request rank determining unit 14: load access request Processing unit 16: Store access request processing unit 18: Access request processing unit 20: Instruction control unit 22: Main storage control device 24: Main storage device 26: Address generation control unit 28: Address generation unit 30: Stack control unit 32: Access Request stack unit 34: Access request processing control unit 36: Vector register 38: Mask register 40: Mask data register 42: Align ID generation unit 44: Data alignment unit

Continuation of the front page (56) References JP-A-2-19945 (JP, A) JP-A-51-48937 (JP, A) JP-A-60-215258 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) G06F 12/06 540 G06F 12/00 571 G06F 17/16

Claims (3)

(57) [Claims] At least two first and second access request generators for generating a store access request to a main storage device in response to a store access command, and at least two of the first and second access request generators generated by the first and second access request generators An access request rank determining unit that determines the processing order of the store access requests of the above, and an access request processing unit that executes a store access to the main storage device in response to a store access request according to the determination order of the access request rank determining unit. When a store access instruction is received, a block access request for sequentially accessing a plurality of data continuously present in the main storage device is processed by the access request processing unit only from the second access request generation unit. Unit, and accesses the multiple data distributed in the main memory in order. When the access request of both the first and second access request generators is sent to the access request processor, the access request of the first access request generator includes a final signal indicating the last element. In an access control method wherein an access request from the first access request generation unit is sent to the access request processing unit with priority, regardless of an access request from the second access request generation unit. In the case where a block access request is generated in the second access request generation unit by a store access instruction and a random access request of one data length is generated in the first access request generation unit by a store access instruction subsequent to the preceding instruction, A file indicating final data for a random access request generated by the first access request generation unit. While inhibiting the addition of null signals, it said the second access request generating unit to generate a dummy access request added with the final signal, the access request priority order determination unit said when receiving a random access request of the first data length After processing a preceding instruction while waiting for a random access request of one data length, the random access request of one data length is sent to the access request processing unit when the dummy access request is obtained. Access control method. 2. The access control system according to claim 1, wherein said access request processing unit executes said dummy access request when receiving a dummy access request generated by said second access request generation unit. An access control method characterized by suppressing the above. 3. The access control method according to claim 1, wherein the access request processing unit suppresses execution of the dummy access request by receiving an invalid flag added to the dummy access request by the access request generation unit. An access control method characterized in that: