JPH0225543B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a busbar control scheme, specifically, a system in which the priority of equipment boards in busbar usage is defined by the slot position on a back panel having a common busbar.
The present invention also relates to an empty slot control method suitable for use in an information processing apparatus in which a daisy chain is used as a means for competing for a bus line between each device board connected to the bus line.

Each equipment board (hereinafter simply referred to as a board) connected to a common bus (hereinafter simply referred to as a bus)
Conventionally, a method called daisy chain has existed as a means for bus contention (processed as an interrupt).

The bus contention method of each board connected by a daisy chain will be briefly explained.

Assume that there is an information processing device in which a CPU board and a plurality of input/output boards are wired-or-connected via a bus line. At this time, the interrupt acceptance signal (RACK) output from the CPU board or the board that controls the bus in response to a bus use request (interrupt) has the highest priority when using the bus (usually according to the order in which the boards are installed). If this I/O board does not request the use of the bus, the interrupt acceptance signal (TACK) is sent to the other adjacent I/O boards in order of priority. Forward. When an input/output board that has received an interrupt request signal (RACK) has issued a request to use the bus, the transfer of the interrupt acceptance signal (TACK) to the next adjacent board is prohibited, and the input/output board is not allowed to use the bus. It displays the usage of the board, occupies the bus, and communicates data with the other board. The above is an outline of Daisy Chain's battle for buses.

FIG. 1 shows a connection diagram of the daisy chain line, that is, the RACK/TACK signal, mounted on the back panel when the above-mentioned daisy chain bus contention is adopted. In the figure, RACK signals are provided from A to F (RACK A to RACK F), and the TACK signal is sent to six slots next to each other, such as RACK A in the next slot and slot B next to it.
Connected up to RACK F. Note that the numbers (1 to 10) in the horizontal direction in the figure indicate slot numbers.

Figure 2 shows a part of the circuit for bus contention provided on each of the above boards, and shows RACK A to RACK.
An example of a conventional circuit that receives an F signal and outputs a TACK signal will be shown.

By the way, according to the above conventional method, it is necessary to mount the boards in order in the slot positions so that the RACK/TACK signals on the back panel are not interrupted. It was not possible to connect the boards as flexible as if the boards were mounted in succession again. Furthermore, the mounting position of the board (CPU or input/output board) differs depending on the system configuration, so it is not possible to standardize the slot positions of the boards.

The present invention has been made based on the above circumstances, and a signal line for detecting an empty slot is provided on a common bus, and furthermore, the board to be mounted detects an empty slot via the signal line and detects an adjacent slot. Even if there is an empty slot in the board, the daisy chain signal is not interrupted and is propagated to the adjacent board.
The object of the present invention is to provide a busbar control method that allows the existence of empty slots and realizes flexible board connections.

Hereinafter, the present invention will be explained in detail using FIGS. 3 and 4.

FIG. 3 is a connection diagram of RACK/TACK signals on the back panel realized by the present invention. To the conventional back panel having a plurality of daisy chain lines (RACK/TACK), a plurality of signal lines for board check (BODCHK A to BODCHKE, BODSET) are added to further detect empty slots. These will be described later.

FIG. 4 shows an embodiment of a bus contention circuit implementing the present invention. A control circuit for detecting an empty slot is added to the conventional bus contention circuit shown in FIG. In the figure, 11 to 16 are inverters, 21 to 25 are NAND gates, 30 and 31 are AND gates, and 40 is a flip-flop that is set when the board requests bus contention.
In addition, R ₁ to _{R 6} are resistor groups that pull up the RACK A to F signals, and R ₇ to _{R 11} are BODCHK A to R 6.
This is a group of resistors that pull up each of the E signals. In the conventional example shown in FIG. 2, the "LOW" level has meaning, but in the embodiment of the present invention shown in FIG. 4, the RACK A to F and TACK signals are "HIGH".
It shall have meaning at different levels. In addition, in the actual circuit, a circuit for controlling the set conditions of the request flip-flop 40 shown in the figure or the output timing of the TACK signal is also required, but this is omitted here as it varies depending on the control method of the system.
Hardware 11-16, 21-25, 30, 31, 4 within the range necessary for understanding the present invention
Only 0 was shown.

Hereinafter, detailed explanations of the embodiments of the present invention will be given based on the following preconditions.

(1) The connections between each signal slot on the back panel shall be wired as shown in Figure 3.

(2) The request signal (RQST) output on the bus is a common line for each slot, and the request flip-flop 40 is not set while the RQST signal from another board is output on the bus. do.

(3) Each board connected to the back panel and requiring bus contention shall have a circuit equivalent to Figure 4.

(4) The timing of RACK A to F and TACK signals is briefly described below. When a bus controller is installed in the first slot of the bus, the controller outputs RACK A to E and TACK signals (equivalent to RACK A to F on the adjacent board) at a certain timing after detecting the RQST signal on the bus. shall be. On the other hand, if a bus controller board is not installed, each board monitors the RQST signal on the bus and
A timing circuit for outputting the TACK signal when the RQST signal is not being generated must be added to the bus contention circuit shown in FIG. 4. It should be noted that the functions and configuration operations of the bus controller are well known, so a description thereof will be omitted here.

The configuration and operation of the present invention will be described below assuming that the bus controller is mounted at the head of the bus. First, boards that use the bus must have
After confirming that the RQST signal does not exist, it sets its own request flip-flop 40, thereby outputting the RQST signal on the bus. When the bus controller board detects the RQST signal, it sends RACK A to RACK to the board mounted in the adjacent position based on a certain timing.
Send F signal. The board adjacent to the bus controller board has its own request flip-flop 4.
If it is not set to 0 and there are no empty slots among the five slots in the rear stage adjacent to its own board, the RACK F signal is output as the TACK signal.
This TACK signal is transmitted as a RACK signal to an adjacent board as shown in FIG. In this way, if there is no empty slot, the RACK signal is transmitted one after another to the adjacent subsequent boards. In the embodiment of the present invention, six RACK signals (RACK A to
Since RACK F) is used, each board outputs the TACK signal output from the slot 6 boards before itself as a daisy chain signal, resulting in a daisy chain of 6 boards.

Next, wiring for detecting empty slots is added to the back panel used in the present invention as shown in FIG. The BODSET signal is connected to ground on each board. (Figure 4) Therefore,
If there is an empty slot, this signal becomes HIGH level, and in the previous slot, BODCHK E goes high.
When the signal is HIGH, the slot before it
BODCHK D signal becomes HIGH level. As a result, each mounted board can detect empty slots for up to five boards after itself.
When each board detects this empty slot, it is necessary to perform control so that the daisy chain signal is not interrupted at the empty slot. Therefore, if there is a RACK signal that becomes RACK F at the position of an empty slot, for example, if there are two empty slots in the rear stage, then the RACK signal corresponding to the RACK F signal of the adjacent slot among these empty slots, and the RACK E signal corresponding to the RACK F signal of the adjacent slot of the slot adjacent to the empty slot.
RACK D signal corresponding to RACK F signal
It is necessary to add this to the TACK signal output conditions.

In this case, the BODCHK D and BODCHK E signals are at the "HIGH" level (FIG. 4) and are supplied to one input terminal of the NAND gates 21 and 22. The other input terminals of the NAND gates 21 and 22 are connected via inverters 11 and 12.
RACK E and RACK D signals are provided.
Therefore, the RACK F signal is sent to the AND gate 31, the RACK E signal and the RACK D signal are sent via the NAND gates 21 and 22, respectively, and further via the NAND gates 23, 24, and 25, respectively.
The BODCHK C, BODCHK B, and BODCHK A signals are input at "LOW" level. Further, the remaining input terminals of the AND gate 31 are supplied with a signal from a request flip-flop 40. Therefore, if the request flip-flop 40 is not set, RACK F, RACK E,
The RACK D signal will be output as the TACK signal.

As described above, according to the present invention, empty slots can be installed even in a device in which the priority order of bus use is determined by the slot position of a back panel having a common bus. Moreover, the signal line for board check (signal line for empty slot detection)
By having, for example, five BODCHK A to E), it is possible to mount boards in up to five consecutive slots.

As explained above, the slot positions of each board can be fixed, and the slot positions of the boards inserted into the back panel can be approximated. Furthermore, by standardizing the slot positions, the mounting position of the signal cable connected to the free edge side plug will also be determined. Furthermore, even in the case of expansion, it is only necessary to mount it in the designated slot, and there is no problem in the expansion work.

[Brief explanation of drawings]

Figure 1 is a connection diagram of the conventional daisy chain signal line RACK/TACK mounted on the back panel.
Fig. 2 is a configuration example showing part of a conventional bus contention circuit, Fig. 3 is a connection diagram of daisy chain signal lines mounted on the back panel by implementing the present invention, and Fig. 4 shows the realization of the present invention. This is an embodiment showing a part of a bus contention circuit. 11-16... Inverter, 21-25... NAND gate, 30, 31... AND gate, 40
...Request flipflop.

Claims (1)

[Claims] 1. In an information processing device in which bus priorities are defined by slot positions on a back panel having a common bus, and a daisy chain is used as a means for competing for a bus for each device board connected to the common bus, the common bus is empty. A device board that includes a plurality of signal lines for slot detection and that is mounted in the slot detects an empty slot using the signal line, and even if there is an empty slot at an adjacent slot position, the device board that is mounted in the slot detects the daisy chain. A bus control method characterized by the ability to propagate signals to adjacent equipment boards without interruption.