JPH08227889A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH08227889A
JPH08227889A JP3217795A JP3217795A JPH08227889A JP H08227889 A JPH08227889 A JP H08227889A JP 3217795 A JP3217795 A JP 3217795A JP 3217795 A JP3217795 A JP 3217795A JP H08227889 A JPH08227889 A JP H08227889A
Authority
JP
Japan
Prior art keywords
film
oxide film
silicon oxide
semiconductor device
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3217795A
Other languages
Japanese (ja)
Inventor
Satoshi Sugiyama
智 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3217795A priority Critical patent/JPH08227889A/en
Publication of JPH08227889A publication Critical patent/JPH08227889A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent impurities from being deposited without providing a deposit preventing film by a method wherein an interlayer insulating film of silicon oxide which contains B and P is formed on a circuit pattern, and the surface layer of the interlayer insulating film is formed of densified layer which contains a lot of oxygen. CONSTITUTION: A gate oxide film 2 and a circuit pattern 3 of polycrystalline silicon film and the like are formed on a semiconductor substrate 1 of Si or the like. A silicon oxide film 4 as an interlayer insulating film which contains B and P is grown as thick as required on the circuit pattern 3. Oxygen is introduced into the surface of the silicon oxide film 4 twice as high in dose as usual to densify only the surface of the silicon oxide film 4, the semiconductor substrate 1 is thermally treated to make the silicon oxide film 4 fluid and flat. By this setup, impurities are capable of being prevented from being deposited without providing a deposit preventing film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置及びその製造
方法に関し、特に半導体装置を構成する層間絶縁膜の構
造及びその形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of an interlayer insulating film constituting the semiconductor device and a forming method thereof.

【0002】[0002]

【従来の技術】半導体集積回路の集積度の向上に伴な
い、回路の3次元的構造がますます複雑化する反面、リ
ソグラフィー技術の必要性から凹凸が形成された回路パ
ターン上の層間絶縁膜の高平坦度への要求が近年より一
層厳しくなってきている。従来最も一般的に行われてき
た平坦化方法は、層間絶縁膜を、燐(P)、硼素(B)
等の不純物を添加した酸化シリコン膜(硼燐珪酸ガラ
ス、以下BPSGと記す)を用いて形成し、融点以上の
熱処理を施し表面張力による流動で平坦化を行う方法
(以下リフローと記す)であり、最も簡易に行うことが
できる。
2. Description of the Related Art As the degree of integration of semiconductor integrated circuits has improved, the three-dimensional structure of the circuit has become more and more complicated, but the necessity of lithography technology has led to the formation of an interlayer insulating film on a circuit pattern having irregularities. The demand for high flatness has become more severe in recent years. The most commonly used planarization method in the past is to form an interlayer insulating film with phosphorus (P) or boron (B).
It is formed by using a silicon oxide film (borophosphosilicate glass, hereinafter referred to as BPSG) to which impurities such as are added, and is subjected to heat treatment at a temperature equal to or higher than the melting point to planarize by flow due to surface tension (hereinafter referred to as reflow). , The easiest to do.

【0003】また従来の平坦化はBPSG単層のリフロ
ーで行われているが、BPSG成膜後、更に表面からの
不純物の析出防止を目的として、酸化シリコン膜や多結
晶シリコン膜をBPSG上層に形成した後、リフローを
行う方法も提案されている(特開昭61−237448
号公報及び特開平3−237744号公報)。以下従来
の層間絶縁膜の平坦化プロセスについて図4を用いて説
明する。
Conventional planarization is performed by reflowing a BPSG single layer, but after the BPSG film is formed, a silicon oxide film or a polycrystalline silicon film is formed on the BPSG upper layer for the purpose of preventing the precipitation of impurities from the surface. A method of performing reflow after formation is also proposed (Japanese Patent Laid-Open No. 61-237448).
(Japanese Patent Laid-Open No. 3-237744). The conventional flattening process of the interlayer insulating film will be described below with reference to FIG.

【0004】まず図4(a)に示すように、半導体基板
1上にゲート酸化膜2と多結晶シリコン膜等からなる回
路パターン3を形成したのち、化学気相成長法(以下C
VD法と記す)を用いてP濃度3〜6mol%、B濃度
8〜18mol%程度添加したBPSG膜4を所望の厚
さに成長させた後、更に適当なCVD法を用いP,B析
出防止膜として酸化シリコン膜6を10nm程度成長す
る。
First, as shown in FIG. 4A, a circuit pattern 3 composed of a gate oxide film 2 and a polycrystalline silicon film or the like is formed on a semiconductor substrate 1, and then a chemical vapor deposition method (hereinafter referred to as C
VD method) is used to grow a BPSG film 4 having a P concentration of 3 to 6 mol% and a B concentration of 8 to 18 mol% added to a desired thickness, and then an appropriate CVD method is used to prevent P and B precipitation. A silicon oxide film 6 is grown as a film to a thickness of about 10 nm.

【0005】次に図4(b)に示すように、900℃程
度の窒素雰囲気中で5〜30分の熱処理を行ない、BP
SG膜4を平坦化する。また析出防止膜として多結晶シ
リコン膜を選択した場合はリフローを900℃の酸素雰
囲気中で行ない、BPSG膜4を流動させると同時に多
結晶シリコン膜を酸化する。このときの多結晶シリコン
膜の厚さは5〜20nmである。
Next, as shown in FIG. 4 (b), heat treatment is performed for 5 to 30 minutes in a nitrogen atmosphere at about 900 ° C.
The SG film 4 is flattened. When a polycrystalline silicon film is selected as the deposition preventing film, reflow is performed in an oxygen atmosphere at 900 ° C. to flow the BPSG film 4 and simultaneously oxidize the polycrystalline silicon film. The thickness of the polycrystalline silicon film at this time is 5 to 20 nm.

【0006】[0006]

【発明が解決しようとする課題】この従来の層間絶縁膜
の平坦化方法では、析出防止膜として酸化シリコン膜も
しくは多結晶シリコン膜をBPSG膜上に形成している
が、次のような問題点がある。
In this conventional method for flattening an interlayer insulating film, a silicon oxide film or a polycrystalline silicon film is formed on a BPSG film as a precipitation preventing film, but the following problems occur. There is.

【0007】まず第1に、この析出防止膜がBPSG膜
の平坦化を阻害する。すなわち、析出防止膜中へのBと
Pの拡散が不十分な為、析出防止膜がないものに比べて
リフローは不完全になる。第2に析出防止膜の膜厚がウ
ェハー面内,面間で一定でない場合、当然BPSG膜の
平坦化後の形状が著しく異なってしまう。
First of all, this precipitation prevention film hinders the flattening of the BPSG film. That is, since the diffusion of B and P into the precipitation preventing film is insufficient, the reflow becomes incomplete as compared with the case without the precipitation preventing film. Secondly, if the film thickness of the precipitation preventing film is not constant in the plane of the wafer or between the planes, the shape of the BPSG film after flattening will be remarkably different.

【0008】第3に現在の最先端デバイスでは浅い拡散
層の拡大防止の必要性からリフロー処理の短時間化が進
んでおり900℃,5分〜10分程度が通常である。こ
のような熱履歴ではリフローが不十分な為、十分な平坦
性を得ることは出来ないことに加え、次世代デバイスが
要求する800〜850℃の熱処理の低温化には到底対
応していくことは出来ない。第4に析出防止膜を形成す
る工程が必要なため、プロセスが複雑化し、生産性低下
の要因となる。また加えて、現在の微細な半導体デバイ
ス製造プロセスでは、酸素雰囲気中で熱処理を行うと、
酸化種が層間絶縁膜としてCVD法で形成した酸化シリ
コン膜を通して基板まで到達してしまい、ゲート酸化膜
厚が増加しデバイス特性を劣化させる。このため窒素雰
囲気中での熱処理が一般的である。
Thirdly, in the present state-of-the-art devices, the reflow process is shortened in time because of the necessity of preventing the expansion of the shallow diffusion layer, and 900 ° C. is usually about 5 to 10 minutes. Due to insufficient thermal reflow with such heat history, sufficient flatness cannot be obtained, and in addition, it will be possible to cope with the low temperature of the heat treatment of 800 to 850 ° C required by next-generation devices. I can't. Fourthly, since the step of forming the precipitation preventing film is required, the process is complicated and the productivity is reduced. In addition, in the current fine semiconductor device manufacturing process, if heat treatment is performed in an oxygen atmosphere,
Oxidizing species reach the substrate through the silicon oxide film formed by the CVD method as an interlayer insulating film, increasing the gate oxide film thickness and degrading the device characteristics. Therefore, heat treatment in a nitrogen atmosphere is common.

【0009】本発明の目的は、析出防止膜を形成しなく
ても不純物の析出が防止でき、しかもリフロー性に優れ
た層間絶縁膜を有する半導体装置及びその製造方法を提
供することにある。
An object of the present invention is to provide a semiconductor device having an interlayer insulating film which can prevent precipitation of impurities without forming a precipitation preventing film and which is excellent in reflowability, and a manufacturing method thereof.

【0010】[0010]

【課題を解決するための手段】第1の発明の半導体装置
は、半導体基板上に形成された回路パターンと、この回
路パターン上に形成されたBとPを含む酸化シリコン膜
からなる層間絶縁膜とを有する半導体装置において、前
記層間絶縁膜の表面層は酸素を多く含む緻密化層から構
成されていることを特徴とするものである。
A semiconductor device according to a first aspect of the present invention is an interlayer insulating film formed of a circuit pattern formed on a semiconductor substrate and a silicon oxide film containing B and P formed on the circuit pattern. And a surface layer of the interlayer insulating film is formed of a densified layer containing a large amount of oxygen.

【0011】第2の発明の半導体装置の製造方法は、回
路パターンが形成された半導体基板上に層間絶縁膜とし
てCVD法によりBとPを含む酸化シリコン膜を形成す
る半導体装置の製造方法において、前記酸化膜の表面層
のみを酸素を多く含む緻密化層とすることを特徴とする
ものである。
The semiconductor device manufacturing method of the second invention is a method of manufacturing a semiconductor device, wherein a silicon oxide film containing B and P is formed as an interlayer insulating film by a CVD method on a semiconductor substrate having a circuit pattern formed thereon. Only the surface layer of the oxide film is a densified layer containing a large amount of oxygen.

【0012】CVD法により一般に形成される成長レー
トの速いBPSG膜の場合、BとPのSiとの結合は不
完全であり、OH基を多く含む。しかしながら、活性酸
素を多くし成長レートを遅くした場合は酸化反応が十分
となる為OH基は少なく、BとPのSiとの結合はほぼ
完全となり、BPSG膜は緻密になる。この為、リフロ
ー時の熱処理によってBPSG膜中の不純物の析出はほ
とんどなくなる。
In the case of a BPSG film having a high growth rate, which is generally formed by the CVD method, the bond between B and P and Si is incomplete and contains a large amount of OH groups. However, when the active oxygen is increased and the growth rate is slowed down, the oxidation reaction is sufficient, so that the OH groups are few, the bond between B and P and Si is almost complete, and the BPSG film becomes dense. Therefore, the precipitation of impurities in the BPSG film is almost eliminated by the heat treatment during the reflow.

【0013】[0013]

【実施例】次に本発明に関し図面を参照して説明する。
図1(a),(b)は本発明の第1の実施例を説明する
為の、工程順に示した半導体チップの断面図、図2は図
1(a)における矢印A部の拡大断面図である。図3は
本発明を実施する為のTEOS(テトラエチルオルソシ
リケイト)−O3 系CVD装置の模式図を示したもので
あり、ウェハー10上には第1〜第n(最終)のn個の
チャンバー51 〜5n によりn層のBPSG膜が形成さ
れる様に構成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings.
1 (a) and 1 (b) are sectional views of a semiconductor chip in order of process for explaining the first embodiment of the present invention, and FIG. 2 is an enlarged sectional view of an arrow A portion in FIG. 1 (a). Is. FIG. 3 is a schematic diagram of a TEOS (tetraethyl orthosilicate) -O 3 system CVD apparatus for carrying out the present invention. The first to nth (final) n chambers are provided on the wafer 10. and it is configured such that the BPSG film of the n-layer is formed by 51 to 5 n.

【0014】まず図1(a)に示すように、Si等の半
導体基板1上にゲート酸化膜2と多結晶シリコン膜等か
らなる回路パターン3を形成したのち、TEOS−O3
系常圧CVD法を用い、燐濃度3〜6mol%,硼素濃
度8〜13mol%を添加したBPSG膜4を所望の膜
厚(0.5〜1.0μm)に成長させる。このとき、C
VD装置が図3のように複数のチャンバー構成を成して
いることにより形成されたBPSG膜は厳密には図2に
示すような多層(n)膜となっている。ここで通常TE
OS−O3 系常圧CVD法では、通常90〜120g/
lのO3 濃度(反応ガスに対し4〜5倍の量)で成膜を
行うが、最終チャンバー5n のみ独立のガス供給系より
180〜250g/lと通常の2倍程度の量のO3 を投
入し図2のようにBPSG膜4の表面層4n のみを緻密
化する。最終チャンバー5n のみO3 濃度を増加させる
理由は、実施例の様に著しくO3 濃度を増加させた場
合、成膜速度が極端に低下し、生産性を損なうためであ
る。
First, as shown in FIG. 1A, a circuit pattern 3 composed of a gate oxide film 2 and a polycrystalline silicon film or the like is formed on a semiconductor substrate 1 of Si or the like, and then TEOS-O 3 is formed.
The atmospheric pressure CVD method is used to grow a BPSG film 4 having a phosphorus concentration of 3 to 6 mol% and a boron concentration of 8 to 13 mol% to a desired film thickness (0.5 to 1.0 μm). At this time, C
Strictly speaking, the BPSG film formed by the VD device having a plurality of chamber configurations as shown in FIG. 3 is a multilayer (n) film as shown in FIG. Normal TE here
In the OS-O 3 system atmospheric pressure CVD method, usually 90 to 120 g /
Film formation is carried out at an O 3 concentration of 1 (4 to 5 times the amount of the reaction gas), but only in the final chamber 5 n , 180 to 250 g / l, which is twice the normal amount of O, compared to an independent gas supply system. 3 is added to densify only the surface layer 4 n of the BPSG film 4 as shown in FIG. Reason for increasing the final chamber 5 n only O 3 concentration, if increased markedly O 3 concentration as in the embodiment, the deposition rate is extremely reduced, because impairing productivity.

【0015】次に図1(b)に示すように、900℃程
度の窒素雰囲気中で5〜30分熱処理を行うことにより
BPSG膜4を流動させ、平坦化を完了する。本実施例
によれば、O3 濃度を上げることにより緻密化した最表
面層は、析出防止膜として機能することに加え、通常の
3 濃度で成膜を行った場合と比較して熱処理中のBP
SG膜表面からのP,Bの外方拡散が抑制されるため、
同一濃度で成膜を行った場合より平坦化形状に優れる。
Next, as shown in FIG. 1B, heat treatment is performed in a nitrogen atmosphere at about 900 ° C. for 5 to 30 minutes so that the BPSG film 4 is fluidized and the planarization is completed. According to the present example, the outermost surface layer densified by increasing the O 3 concentration functions as a precipitation preventing film, and the heat treatment is performed during the heat treatment as compared with the case where the film is formed at a normal O 3 concentration. BP
Since the outward diffusion of P and B from the SG film surface is suppressed,
The flattened shape is superior to when the film is formed at the same concentration.

【0016】本第1の実施例によれば、不純物の析出に
よる不良の低減に加え、平坦性の向上により、メタル配
線の層間膜段差部に於ける残渣によるショート不良の低
減、リソグラフィー工程でのフォーカス不良の低減等の
効果により、半導体装置の歩留りを従来より約20%向
上させることが出来る。尚、好ましい表面層4n の厚さ
は10nm以上である。
According to the first embodiment, in addition to the reduction of defects due to the precipitation of impurities, the improvement of the flatness reduces the short defects due to the residue at the step portion of the interlayer film of the metal wiring, and in the lithography process. The yield of the semiconductor device can be improved by about 20% as compared with the conventional one due to the effect of reducing the focus defect. The preferable thickness of the surface layer 4 n is 10 nm or more.

【0017】上記第1の実施例では、900℃の窒素雰
囲気中での熱処理を用いてリフローを行ったが、第2の
実施例では、800〜950℃程度の低温リフローを行
う場合について説明する。低温リフローの為には燐・硼
素の不純物濃度合計が25〜30mol%以上が必要で
ある一方、BPSG膜の析出限界濃度は18mol%程
度であるため通常の成膜方法では不純物析出を防止する
ことが出来ない。そこでBPSG膜の表面層4n を、第
1の実施例より更に緻密化する必要性が生じる。
In the first embodiment, the reflow is performed by using the heat treatment in the nitrogen atmosphere at 900 ° C., but in the second embodiment, the case of performing the low temperature reflow at about 800 to 950 ° C. will be described. . For low temperature reflow, the total impurity concentration of phosphorus and boron is required to be 25 to 30 mol% or more, while the deposition limit concentration of the BPSG film is about 18 mol%. I can't. Therefore, it becomes necessary to further densify the surface layer 4 n of the BPSG film as compared with the first embodiment.

【0018】まず図1(a)と同様に、TEOS−O3
系常圧CVD法を用い、燐濃度5〜10mol%,硼素
濃度20〜25mol%を添加したBPSG膜を所望の
膜厚に成長させる。このとき第1の実施例と同様に、最
終チャンバー5n にのみ300〜350g/l以上のO
3 を投入し、膜の最表層を緻密化する。その後に800
〜850℃の窒素雰囲気中で5〜30分熱処理を行い、
BPSGを流動させ、平坦化を終了する。
First, as in the case of FIG. 1A, TEOS-O 3
Using a systematic atmospheric pressure CVD method, a BPSG film added with a phosphorus concentration of 5 to 10 mol% and a boron concentration of 20 to 25 mol% is grown to a desired film thickness. At this time, as in the case of the first embodiment, 300 to 350 g / l or more of O is only provided in the final chamber 5 n.
Add 3 to densify the outermost layer of the film. Then 800
Perform heat treatment for 5 to 30 minutes in a nitrogen atmosphere at ~ 850 ° C,
Flow the BPSG to complete the planarization.

【0019】第2の実施例では、BとPの高濃度化の効
果により、800〜850℃の熱処理を用いても、第1
の実施例と同等の平坦化形状を得ることができる。更に
第2の実施例はリフローの低温化にも対応できる為、熱
履歴を短縮し、浅い拡散層の拡大防止にも効果を発揮で
きる。
In the second embodiment, due to the effect of increasing the concentration of B and P, even if the heat treatment at 800 to 850 ° C. is used,
It is possible to obtain a flattened shape equivalent to that of the embodiment. Further, since the second embodiment can cope with the low temperature of the reflow, the heat history can be shortened and the effect of preventing the expansion of the shallow diffusion layer can be exerted.

【0020】上記実施例に於いてはBPSG成膜装置と
してTEOS−O3 系常圧CVD装置を用いたが、これ
は該装置が最も生産性に優れるため、今後層間絶縁膜
(BPSG)形成装置として主流となる点、また、装置
構成が複数チャンバーが可能であり、本発明の様な膜表
層のみの緻密化を行う場合、比較的容易にプロセスが制
御できる点による。本発明で目的とする膜表層の緻密化
が可能であれば他の装置を用いてもよく、反応ガスとし
てもシラン系ガスとプラズマ分解による活性化酸素等を
用いてもよい。
In the above embodiment, a TEOS-O 3 type atmospheric pressure CVD apparatus was used as the BPSG film forming apparatus, but this apparatus has the highest productivity, and therefore an interlayer insulating film (BPSG) forming apparatus will be used in the future. This is due to the fact that it is a mainstream, and that the apparatus can have a plurality of chambers, and the process can be controlled relatively easily when densifying only the film surface layer as in the present invention. Other apparatus may be used as long as it is possible to densify the film surface layer which is the object of the present invention, and a silane-based gas and activated oxygen by plasma decomposition may be used as the reaction gas.

【0021】[0021]

【発明の効果】以上説明したように本発明は、層間絶縁
膜として、BとPを含む低融点の酸化シリコン膜を形成
し、その表面層を反応ガス内の活性酸素量を増大させて
緻密化した酸化シリコン膜とすることにより、平坦化の
為の熱処理を行っても不純物の析出はなく、しかもリフ
ロー性に優れた層間絶縁膜を有する半導体装置及びその
製造方法が得られるという効果がある。
As described above, according to the present invention, a low melting point silicon oxide film containing B and P is formed as an interlayer insulating film, and its surface layer is made dense by increasing the amount of active oxygen in the reaction gas. The use of the converted silicon oxide film has an effect that a semiconductor device having an interlayer insulating film with excellent reflowability and a method for manufacturing the semiconductor device can be obtained without precipitation of impurities even when heat treatment for planarization is performed. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明する為の半導体チ
ップの断面図。
FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

【図2】図1における矢印A部の拡大断面図。FIG. 2 is an enlarged sectional view of an arrow A portion in FIG.

【図3】実施例に用いるCVD装置の模式図。FIG. 3 is a schematic diagram of a CVD apparatus used in Examples.

【図4】従来例を説明する為の半導体チップの断面図。FIG. 4 is a sectional view of a semiconductor chip for explaining a conventional example.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 ゲート酸化膜 3 回路パターン 4,41 〜4n BPSG膜 51 〜5n 第1〜第nチャンバー 6 酸化シリコン膜 10 ウェハー1 Semiconductor Substrate 2 Gate Oxide Film 3 Circuit Pattern 4, 4 1 to 4 n BPSG Film 5 1 to 5 n 1st to nth Chamber 6 Silicon Oxide Film 10 Wafer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成された回路パターン
と、この回路パターン上に形成されたBとPを含む酸化
シリコン膜からなる層間絶縁膜とを有する半導体装置に
おいて、前記層間絶縁膜の表面層は酸素を多く含む緻密
化層から構成されていることを特徴とする半導体装置。
1. A semiconductor device having a circuit pattern formed on a semiconductor substrate and an interlayer insulating film made of a silicon oxide film containing B and P formed on the circuit pattern, the surface of the interlayer insulating film. A semiconductor device, wherein the layer is composed of a densified layer containing a large amount of oxygen.
【請求項2】 回路パターンが形成された半導体基板上
に層間絶縁膜としてCVD法によりBとPを含む酸化シ
リコン膜を形成する半導体装置の製造方法において、前
記酸化膜の表面層のみを酸素を多く含む緻密化層とする
ことを特徴とする半導体装置の製造方法。
2. A method for manufacturing a semiconductor device, wherein a silicon oxide film containing B and P is formed as an interlayer insulating film by CVD on a semiconductor substrate having a circuit pattern formed thereon, wherein only the surface layer of the oxide film contains oxygen. A method of manufacturing a semiconductor device, comprising forming a densified layer containing a large amount.
【請求項3】 CVD法による酸化シリコン膜の成膜終
了直前に反応ガス内の活性酸素量を増大させ緻密化層を
形成する請求項2記載の半導体装置の製造方法。
3. The method for manufacturing a semiconductor device according to claim 2, wherein the densified layer is formed by increasing the amount of active oxygen in the reaction gas immediately before the completion of forming the silicon oxide film by the CVD method.
【請求項4】 TEOS−O3 系の反応ガスを用いる請
求項3記載の半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein a TEOS-O 3 based reaction gas is used.
JP3217795A 1995-02-21 1995-02-21 Semiconductor device and manufacture thereof Pending JPH08227889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3217795A JPH08227889A (en) 1995-02-21 1995-02-21 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3217795A JPH08227889A (en) 1995-02-21 1995-02-21 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH08227889A true JPH08227889A (en) 1996-09-03

Family

ID=12351662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3217795A Pending JPH08227889A (en) 1995-02-21 1995-02-21 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH08227889A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010278231A (en) * 2009-05-28 2010-12-09 Yamaha Corp Method for manufacturing semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0497527A (en) * 1990-08-16 1992-03-30 Applied Materials Japan Kk Method of preventing precipitation
JPH05218027A (en) * 1992-02-06 1993-08-27 Seiko Epson Corp Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0497527A (en) * 1990-08-16 1992-03-30 Applied Materials Japan Kk Method of preventing precipitation
JPH05218027A (en) * 1992-02-06 1993-08-27 Seiko Epson Corp Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010278231A (en) * 2009-05-28 2010-12-09 Yamaha Corp Method for manufacturing semiconductor device

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