JP3080809B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3080809B2 JP3080809B2 JP05104098A JP10409893A JP3080809B2 JP 3080809 B2 JP3080809 B2 JP 3080809B2 JP 05104098 A JP05104098 A JP 05104098A JP 10409893 A JP10409893 A JP 10409893A JP 3080809 B2 JP3080809 B2 JP 3080809B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- substrate
- oxide film
- gas
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 20
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical group C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 20
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 9
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 8
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910007991 Si-N Inorganic materials 0.000 description 2
- 229910006294 Si—N Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000005587 bubbling Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Classifications
-
- H01L21/205—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
- H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/118—Oxide films
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
- Chemical Vapour Deposition (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置の製造方
法に関し、より詳しくは、有機ソースとオゾンとを常圧
下で反応させる化学気相成長法(常圧ＣＶＤ法)に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a chemical vapor deposition method (atmospheric pressure CVD method) in which an organic source and ozone are reacted at normal pressure.
【０００２】[0002]
【従来の技術】半導体素子の高密度化,高集積化に伴っ
て多層配線を形成する必要から、層間絶縁膜形成法とし
て、低温(４００℃程度)で成膜ができ、かつ、優れた埋
め込み平坦性を示すＴＥＯＳ(テトラエトキシシラン)−
Ｏ3(オゾン)系常圧ＣＶＤ法が知られている。ＴＥＯＳ
−Ｏ3系常圧ＣＶＤ法は、ＴＥＯＳ(例えばＮ2ガスでバ
ブリングしたもの)とＯ3(Ｏ2をキャリアガスとする)と
を所定温度に保持した基板に導き、常圧下で化学反応さ
せて、上記基板にシリコン酸化膜を成長させる方法であ
る。2. Description of the Related Art Multilayer interconnections have to be formed in accordance with high density and high integration of semiconductor devices. Therefore, as a method of forming an interlayer insulating film, a film can be formed at a low temperature (about 400 ° C.) and an excellent burying method can be used. TEOS (tetraethoxysilane) showing flatness
An O 3 (ozone) -based atmospheric pressure CVD method is known. TEOS
-O 3 an atmospheric pressure CVD method, (which was bubbled with e.g. N 2 gas) TEOS and O 3 (the O 2 and carrier gas) and guidance to a substrate maintained at a predetermined temperature, are chemically reacted under normal pressure And growing a silicon oxide film on the substrate.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記Ｔ
ＥＯＳ−Ｏ3系常圧ＣＶＤ法では、シリコン酸化膜の成
長速度が下地の材料に依存するという問題がある。すな
わち、下地が単結晶Ｓｉ,ポリＳｉ，金属からなるとき
は成長速度が速くなる一方、下地がプラズマＳｉＯ2，
サーマル(熱酸化)ＳｉＯ2からなるときは成長速度が遅
くなる(下地がＳｉＮのときは中間速度となる。)。な
お、図６に、下地がポリＳｉ、サーマルＳｉＯ2のとき
の成長速度の差を例示している(□がポリＳｉ上の成長
速度、●がサーマルＳｉＯ2上の成長速度を表してい
る。)。このように、下地の種類によって成長速度が異
なるため、絶縁膜上に所定のピッチで金属配線などが設
けられている上に成長を行うとき(金属層間工程)、ステ
ップカバレッジが悪くなり、良好な埋め込み形状を得る
ことができない。However, the above T
The EOS-O 3 based atmospheric pressure CVD method has a problem that the growth rate of the silicon oxide film depends on the underlying material. That is, when the underlayer is made of single-crystal Si, poly-Si, or metal, the growth rate increases, while the underlayer is made of plasma SiO 2 ,
When it is made of thermal (thermally oxidized) SiO 2, the growth rate is low (when the underlayer is SiN, the growth rate is intermediate). FIG. 6 illustrates the difference between the growth rates when the underlying layer is made of poly-Si and thermal SiO 2 (□ represents the growth rate on poly-Si, and ● represents the growth rate on thermal SiO 2 ). ). As described above, since the growth rate varies depending on the type of the base, when growing on a metal wiring or the like provided at a predetermined pitch on the insulating film (metal interlayer process), the step coverage becomes poor, and the The embedded shape cannot be obtained.
【０００４】この問題を避けるために、金属層間工程で
は、一旦ＴＥＯＳを原料としてプラズマＣＶＤ法により
シリコン酸化膜(プラズマＴＥＯＳ膜)を形成し、この
後、上記ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法によりシリコン
酸化膜を形成する試みがなされている。しかし、工程数
が増加するし、また、サブハーフミクロン域ではプラズ
マＴＥＯＳ膜自体のステップカバレッジが悪いため、良
好な埋め込み形状を得ることができない。In order to avoid this problem, in the metal interlayer process, a silicon oxide film (plasma TEOS film) is once formed by a plasma CVD method using TEOS as a raw material, and then a TEOS-O 3 system normal pressure CVD method is used. Attempts have been made to form a silicon oxide film. However, the number of steps increases, and the step coverage of the plasma TEOS film itself is poor in the sub-half micron range, so that a good buried shape cannot be obtained.
【０００５】なお、ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法で、
オゾン濃度(通常５ｗｔ％）を０.５〜１.５ｗｔ％程度
に下げれば、成長速度の下地依存性を解消することがで
きるが、アニールによる膜収縮率が大きくなるなど、形
成されるシリコン酸化膜の膜質が悪くなる。[0005] It should be noted that a TEOS-O 3 system atmospheric pressure CVD method is used.
If the ozone concentration (typically 5 wt%) is reduced to about 0.5 to 1.5 wt%, the dependence of the growth rate on the base can be eliminated, but the silicon oxide formed due to the increase in the film shrinkage due to the annealing and the like can be eliminated. The quality of the film deteriorates.
【０００６】そこで、この発明の目的は、下地の如何に
かかわらず成長速度が等しく、優れた埋め込み平坦性を
示し、しかも、良好な膜質のシリコン酸化膜を形成でき
る半導体装置の製造方法を提供することにある。Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a silicon oxide film having a uniform growth rate, excellent burying flatness, and excellent film quality regardless of the underlying layer. It is in.
【０００７】[0007]
【課題を解決するための手段および作用】上記目的を達
成するため、この発明は、有機ソースとＯ3とを基板に
導き、上記有機ソースとＯ3とを常圧下で化学反応させ
て、上記基板にシリコン酸化膜を成長させる半導体装置
の製造方法において、上記有機ソースはヘキサメチルジ
シラザンであることを特徴としている。In order to achieve the above-mentioned object, the present invention introduces an organic source and O 3 to a substrate, and chemically reacts the organic source and O 3 under normal pressure to obtain In a method of manufacturing a semiconductor device for growing a silicon oxide film on a substrate, the organic source is hexamethyldisilazane.
【０００８】本発明者は、種々の有機ソース原料につい
て実験を試みた結果、有機ソースとして、組成にＳｉ−
Ｎ結合を有するものを用いた場合、形成されるシリコン
酸化膜は下地依存性がなく、優れた埋め込み平坦性を示
すことを発見した。上記有機ソースとしては、特にヘキ
サメチルジシラザンが望ましい。成長時のオゾン濃度は
通常の５ｗｔ％で良く、この結果、良好な膜質のシリコ
ン酸化膜が得られた。The present inventors have conducted experiments on various organic source materials, and as a result, have found that the organic source has a composition of Si—
It has been discovered that when a material having an N bond is used, the formed silicon oxide film has no dependence on the underlayer and exhibits excellent buried flatness. Hexamethyldisilazane is particularly desirable as the organic source. The ozone concentration during the growth may be 5 wt% as usual, and as a result, a silicon oxide film having good film quality was obtained.
【０００９】[0009]
【実施例】以下、この発明の半導体装置の製造方法を実
施例により詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to embodiments.
【００１０】図１は、この発明によりシリコン酸化膜を
成長するための有機ソース−Ｏ3系常圧ＣＶＤ装置を示
している。この装置は、基板１を所定の温度に保持でき
るヒータ２と、上記基板１に面し、カバー４に覆われた
デスパージョン・ヘッド３を備えている。上記デスパー
ジョン・ヘッド３の基板側３aに、ガスを噴出できるス
リット３１,３２が交互に設けられている。ヘッド３の
下部３bでは、スリット３１に対して有機ソースを導入
するガス系２１が接続される一方、スリット３２に対し
てＯ3およびＯ2ガスを導入するガス系２２が接続されて
いる。上記ガス系２１は、雰囲気用Ｎ2系２１aと、キャ
リアＮ2系２１bとが合流したものである。雰囲気用Ｎ2
系２１aは、マスフローコントローラ９を有し、雰囲気
用Ｎ2ガスを所定の流量でヘッド３へ供給する。キャリ
アＮ2系２１bは、マスフローコントローラ１０と、組成
にＳｉ−Ｎ結合を有する有機ソース１６を溜めたソース
容器６とを有し、ヘキサメチルジシラザン１６を所定流
量のＮ2ガスでバブリングしてヘッド３へ供給する。こ
の例では、組成にＳｉ−Ｎ結合を有する有機ソース１６
として、ヘキサメチルジシラザン(（ＣＨ3）3Ｓｉ−Ｎ
（Ｈ）−Ｓｉ(ＣＨ3）3）を用いる。なお、ヘキサメチ
ルジシラザン（ＨＭＤＳ）はＴＥＯＳに比して蒸気圧が
高いので、キャリアＮ2ガス流量を小さくすることかで
きる。一方、ガス系２２は、マスフローコントローラ８
と、オゾン発生装置５とを有し、Ｏ3およびＯ2ガスを所
定の流量,比率でヘッド３へ供給する。[0010] Figure 1 shows an organic source -O 3 an atmospheric pressure CVD apparatus for growing a silicon oxide film by the present invention. The apparatus includes a heater 2 capable of maintaining a substrate 1 at a predetermined temperature, and a dispersion head 3 facing the substrate 1 and covered by a cover 4. On the substrate side 3a of the dispersion head 3, slits 31 and 32 capable of ejecting gas are provided alternately. In the lower portion 3 b of the head 3, a gas system 21 for introducing an organic source is connected to the slit 31, while a gas system 22 for introducing O 3 and O 2 gas is connected to the slit 32. The gas system 21 is a mixture of the atmosphere N 2 system 21a and the carrier N 2 system 21b. Atmosphere for N 2
System 21a includes a mass flow controller 9, and supplies a N 2 gas atmosphere to the head 3 at a predetermined flow rate. The carrier N 2 system 21b has a mass flow controller 10 and a source container 6 storing an organic source 16 having a Si—N bond in the composition, and bubbling the hexamethyldisilazane 16 with a predetermined flow rate of N 2 gas. Supply to head 3. In this example, an organic source 16 having a Si—N bond in the composition is used.
As hexamethyldisilazane ((CH 3) 3 Si- N
Used (H) -Si (CH 3) 3). Since the vapor pressure of hexamethyldisilazane (HMDS) is higher than that of TEOS, the flow rate of the carrier N 2 gas can be reduced. On the other hand, the gas system 22 includes the mass flow controller 8.
And an ozone generator 5 for supplying O 3 and O 2 gas to the head 3 at a predetermined flow rate and ratio.
【００１１】実際に成長を行う場合、ヒータ２によって
基板１の温度を４１０℃に設定し、ヘキサメチルジシラ
ザン１６の温度を６５℃に保つ。マスフローコントロー
ラ９,１０によって、雰囲気用Ｎ2ガスの流量を１８ＳＬ
Ｍ、ヘキサメチルジシラザン１６をバブリングするキャ
リアＮ2ガスの流量を０.４ＳＬＭにそれぞれ設定する。
また、マスフローコントローラ８によってＯ2ガスの流
量を７.５ＳＬＭに設定し、オゾン発生装置５によって
Ｏ2ガス中のＯ3を５ｗｔ％に設定する。このような成長
条件で、基板１を図１において左右方向に移動させつ
つ、スリット３１,３２を通して各ガスを基板１に導い
てシリコン酸化膜を成長させる。なお、反応後のガスは
ヘッド３とカバー４との隙間３３を通して排気する。In actual growth, the temperature of the substrate 1 is set at 410 ° C. by the heater 2 and the temperature of hexamethyldisilazane 16 is maintained at 65 ° C. The mass flow controllers 9 and 10 adjust the flow rate of the atmosphere N 2 gas to 18 SL.
The flow rate of the carrier N 2 gas for bubbling M and hexamethyldisilazane 16 is set to 0.4 SLM.
The mass flow controller 8 sets the flow rate of the O 2 gas to 7.5 SLM, and the ozone generator 5 sets the O 3 in the O 2 gas to 5 wt%. Under such growth conditions, while moving the substrate 1 in the left-right direction in FIG. 1, each gas is guided to the substrate 1 through the slits 31 and 32 to grow a silicon oxide film. The gas after the reaction is exhausted through a gap 33 between the head 3 and the cover 4.
【００１２】基板１上に成長した膜を評価したところ、
形成されたシリコン酸化膜は下地の種類にかかわらず略
同一の成長速度を示した。例えば、図２に示すように、
下地がポリＳｉ、サーマルＳｉＯ2のときに、基板温度
３５０〜４３０℃の範囲で、成長速度が略同一となった
(□がポリＳｉ上の成長速度、●がサーマルＳｉＯ2上の
成長速度を表している。)。また、ライン・アンド・ス
ペース(Ｌ／Ｓ)パターン(凹凸が周期的に繰り返すパタ
ーンであって、凹部と凸部との幅が同一のもの)上に成
長させた場合、図３に示すように、パターンスペース
（凹部または凸部の幅）が０.５μｍに至るまでカバレ
ッジ比（凹部上の厚さ／凸部上の厚さ）が８０％以上と
なり、優れた埋め込み特性を示した。また、表１に示す
ように、０.５％ＨＦ液によるエッチング速度が２２５
Å／ｍｉｎ．、８００℃３０ｍｉｎ．のアニールによる
膜収縮率が５.８％となって、ＴＥＯＳ−Ｏ3の反応によ
るもの(エッチング速度２２０Å／ｍｉｎ．、膜収縮率
６.０％)と同等の良好な膜質を示した。When the film grown on the substrate 1 was evaluated,
The formed silicon oxide film showed almost the same growth rate regardless of the type of the underlayer. For example, as shown in FIG.
When the underlayer was made of poly-Si or thermal SiO 2 , the growth rate became substantially the same in the substrate temperature range of 350 to 430 ° C.
(□ represents the growth rate on poly-Si, and ● represents the growth rate on thermal SiO 2 ). When grown on a line-and-space (L / S) pattern (a pattern in which irregularities are periodically repeated and the width of the concave and convex portions is the same), as shown in FIG. In addition, the coverage ratio (thickness on the concave portion / thickness on the convex portion) was 80% or more until the pattern space (width of the concave portion or the convex portion) reached 0.5 μm, showing excellent embedding characteristics. Further, as shown in Table 1, the etching rate with a 0.5% HF solution was 225.
Å / min. , 800 ° C for 30 min. The film shrinkage by annealing of 5.8% was 5.8%, indicating good film quality equivalent to that by the reaction of TEOS-O 3 (etching rate 220 ° / min., Film shrinkage 6.0%).
【００１３】なお、この成長方法を用いて、次のように
して基板表面の平坦化を行う。基板１の表面には、図４
(a)に示すように、既にゲート絶縁膜１２と、所定のピ
ッチで並ぶゲート電極１３と、層間絶縁膜１４とが形成
され、さらに上記ゲート電極１３上に上部電極１５が形
成されていものとする。ここで、同図(b)に示すよう
に、上記成長方法を適用して、層間絶縁膜として全面に
シリコン酸化膜１６を成長させる。この後、ドライエッ
チングによりシリコン酸化膜１６を全面にわたってエッ
チングする。これにより、膜厚を調整するとともに基板
表面を平坦化することができる。By using this growth method, the substrate surface is planarized as follows. As shown in FIG.
As shown in (a), the gate insulating film 12, the gate electrodes 13 arranged at a predetermined pitch, and the interlayer insulating film 14 are already formed, and the upper electrode 15 is formed on the gate electrode 13. I do. Here, as shown in FIG. 2B, a silicon oxide film 16 is grown on the entire surface as an interlayer insulating film by applying the above-described growth method. After that, the silicon oxide film 16 is entirely etched by dry etching. Thereby, the film thickness can be adjusted and the substrate surface can be flattened.
【００１４】[0014]
【発明の効果】以上より明らかなように、この発明の半
導体装置の製造方法は、ヘキサメチルジシラザンとＯ3
とを基板に導き、上記ヘキサメチルジシラザンとＯ3と
を常圧下で化学反応させて、上記基板にシリコン酸化膜
を成長させるので、下地の如何にかかわらず成長速度が
等しく、優れた埋め込み平坦性を示し、しかも、良好な
膜質のシリコン酸化膜を形成することができる。As is clear from the above, the method of manufacturing a semiconductor device according to the present invention employs hexamethyldisilazane and O 3
Is introduced into the substrate, and the hexamethyldisilazane and O 3 are chemically reacted under normal pressure to grow a silicon oxide film on the substrate. And a silicon oxide film having good film quality can be formed.
【００１５】[0015]
【図１】 この発明によりシリコン酸化膜を成長するの
に用いる有機ソース−Ｏ3系常圧ＣＶＤ装置を示す図で
ある。FIG. 1 is a view showing an organic source-O 3 -based atmospheric pressure CVD apparatus used for growing a silicon oxide film according to the present invention.
【図２】 この発明の一実施例の成長方法により形成さ
れるシリコン酸化膜の成長速度と基板温度との関係を示
す図である。FIG. 2 is a diagram showing a relationship between a growth rate of a silicon oxide film formed by a growth method according to an embodiment of the present invention and a substrate temperature.
【図３】 上記成長方法によりシリコン酸化膜を形成し
た場合のカバレッジ比とパターンスペースとの関係を示
す図である。FIG. 3 is a diagram showing a relationship between a coverage ratio and a pattern space when a silicon oxide film is formed by the growth method.
【図４】 上記成長方法を適用して基板表面を平坦化す
る工程を説明する図である。FIG. 4 is a diagram illustrating a step of flattening a substrate surface by applying the above-described growth method.
【図５】 ヘキサメチルジシラザンおよびＴＥＯＳの蒸
気圧と温度との関係を示す図である。FIG. 5 is a diagram showing the relationship between the vapor pressure of hexamethyldisilazane and TEOS and temperature.
【図６】 ＴＥＯＳ−Ｏ3系常圧ＣＶＤ法によるシリコ
ン酸化膜の下地依存性を示す図である。FIG. 6 is a diagram showing the underlayer dependence of a silicon oxide film formed by a TEOS-O 3 based atmospheric pressure CVD method.
１ 基板 ２ ヒータ ３ デスパージョン・ヘッド ４ カバー ５ オゾン発生装置 ６,７ ソース容器 ８,９,１０ マスフローコントローラ ２１ 有機ソースを導入するガス系 ２１a キャリアＮ2系 ２１b 有機ソース系 ２２ Ｏ3およびＯ2ガスを導入するガス系DESCRIPTION OF SYMBOLS 1 Substrate 2 Heater 3 Dispersion head 4 Cover 5 Ozone generator 6,7 Source container 8,9,10 Mass flow controller 21 Gas system for introducing an organic source 21a Carrier N 2 system 21b Organic source system 22 O 3 and O 2 Gas system to introduce gas
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/31 C23C 16/00 H01L 21/205 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/31 C23C 16/00 H01L 21/205
Claims (1)
有機ソースとＯ3とを常圧下で化学反応させて、上記基
板にシリコン酸化膜を成長させる半導体装置の製造方法
において、 上記有機ソースはヘキサメチルジシラザンであることを
特徴とする半導体装置の製造方法。1. A lead to the organic source and O 3 substrate, and the organic source and O 3 by a chemical reaction under normal pressure, in the manufacturing method of a semiconductor device for growing a silicon oxide film on the substrate, the organic A method for manufacturing a semiconductor device, wherein the source is hexamethyldisilazane.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05104098A JP3080809B2 (en) | 1993-04-30 | 1993-04-30 | Method for manufacturing semiconductor device |
| US08/098,927 US5459108A (en) | 1992-10-06 | 1993-07-29 | Normal pressure CVD process for manufacture of a semiconductor device through reaction of a nitrogen containing organic source with ozone |
| KR1019930015075A KR970005678B1 (en) | 1992-10-06 | 1993-08-03 | Nitrogen source addition in lpcvd method reacted with inorganic source and ozon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05104098A JP3080809B2 (en) | 1993-04-30 | 1993-04-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06314654A JPH06314654A (en) | 1994-11-08 |
| JP3080809B2 true JP3080809B2 (en) | 2000-08-28 |
Family
ID=14371648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05104098A Expired - Fee Related JP3080809B2 (en) | 1992-10-06 | 1993-04-30 | Method for manufacturing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3080809B2 (en) |
| KR (1) | KR970005678B1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342277B1 (en) | 1996-08-16 | 2002-01-29 | Licensee For Microelectronics: Asm America, Inc. | Sequential chemical vapor deposition |
| FI118804B (en) | 1999-12-03 | 2008-03-31 | Asm Int | Process for making oxide films |
| JP4986054B2 (en) * | 2007-11-13 | 2012-07-25 | 株式会社明電舎 | Oxide film forming method and apparatus |
| JP6702514B1 (en) * | 2018-11-30 | 2020-06-03 | 株式会社明電舎 | Oxide film forming equipment |
-
1993
- 1993-04-30 JP JP05104098A patent/JP3080809B2/en not_active Expired - Fee Related
- 1993-08-03 KR KR1019930015075A patent/KR970005678B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940010187A (en) | 1994-05-24 |
| JPH06314654A (en) | 1994-11-08 |
| KR970005678B1 (en) | 1997-04-18 |
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