KR102225183B1 - A defect healing method by selective deposition for memory device - Google Patents

A defect healing method by selective deposition for memory device Download PDF

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KR102225183B1
KR102225183B1 KR1020190066737A KR20190066737A KR102225183B1 KR 102225183 B1 KR102225183 B1 KR 102225183B1 KR 1020190066737 A KR1020190066737 A KR 1020190066737A KR 20190066737 A KR20190066737 A KR 20190066737A KR 102225183 B1 KR102225183 B1 KR 102225183B1
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silicon
material layer
memory device
layer
oxide film
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KR20200140432A (en
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이한보람
김우희
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인천대학교 산학협력단
한양대학교 에리카산학협력단
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Abstract

본 발명은 메모리 소자의 미스얼라인의 결함을 해결하기 위한 메모리 소자 결함 회복 방법에 관한 것으로, 구체적으로는 1) 제1물질층과 제2물질층이 동시에 노출되어 미스얼라인이 발생된 기판을 제공하는 단계; 2) 제1물질층 또는 제2물질층 중 어느 하나가 실리콘층인 경우 O2와 H2 가스를 이용하여 실리콘층을 선택적으로 산화시켜 실리콘 산화막을 형성하는 단계; 3) 상기 실리콘 산화막에 자기조립단분자막(Self-Assembled Monolayer, SAM)을 흡착시키는 단계; 4) 실리콘층 이외의 물질층 상에 패시베이션 재료를 증착시키는 단계; 5) 상기 자기조립단분자막을 포함하는 실리콘 산화막을 에칭 공정에 의하여 제거하는 단계를 포함하며, 본 발명은 DRAM 이외에도 반도체에서 컨택을 요구하는 모든 제작 공정(소자-소자, 소자-전극, 전극-전극 등등)에서 발생하는 포토리소그라피 기술의 불일치성으로 인한 전기적 쇼트를 방지하기 위한 결함 회복 기술로서 나노 스케일 패터닝 공정의 단점을 보완해줄 뿐만 아니라 모든 공정이 진공 상에서 이루어지기 때문에 활용하면 현재의 반도체 공정에 직접적으로 적용이 가능하다.The present invention relates to a method for recovering memory device defects for solving a defect of misalignment of a memory device. Specifically, 1) a substrate in which a first material layer and a second material layer are simultaneously exposed and misaligned Providing; 2) forming a silicon oxide film by selectively oxidizing the silicon layer using O 2 and H 2 gas when either the first material layer or the second material layer is a silicon layer; 3) adsorbing a self-assembled monolayer (SAM) on the silicon oxide film; 4) depositing a passivation material on a material layer other than the silicon layer; 5) The silicon oxide film including the self-assembled monolayer is removed by an etching process, and the present invention provides all manufacturing processes (device-device, device-electrode, electrode-electrode, etc.) that require contacts in semiconductors other than DRAM. ), it is a defect recovery technology to prevent electrical shorts due to inconsistency of photolithography technology, which not only compensates for the shortcomings of the nanoscale patterning process, but also applies directly to the current semiconductor process if used because all processes are performed in a vacuum. This is possible.

Description

선택적 증착에 의한 메모리 소자 결함 회복 방법{A DEFECT HEALING METHOD BY SELECTIVE DEPOSITION FOR MEMORY DEVICE}Memory device defect recovery method by selective deposition {A DEFECT HEALING METHOD BY SELECTIVE DEPOSITION FOR MEMORY DEVICE}

본 발명은 자기조립 기반의 바텀업 나노패터닝 중 가장 각광받고 있는 지역 선택적 원자층 증착법(Area-Selective Atomic Layer Deposition, AS-ALD)을 활용하여, DRAM(Dynamic RAM) 제작에 있어 탑다운 패터닝(리소그래피+플라즈마에칭) 공정을 이용한 박막 패터닝 공정 중 발생하는 접합면 간 불일치성(Contact Mismatch or Misaligned issue)을 해결하여 DRAM에서 발생하는 전기적 쇼트(Electrical short) 문제를 방지하는 방법에 관한 것이다.The present invention utilizes the area-selective atomic layer deposition (AS-ALD), which is the most popular among self-assembly-based bottom-up nanopatterning, and uses top-down patterning (lithography) in the manufacture of dynamic RAM (DRAM). The present invention relates to a method of preventing an electrical short problem occurring in DRAM by solving contact mismatch or misaligned issue occurring during a thin film patterning process using a +plasma etching) process.

패턴과 일치하지 않는 DC(Digit Contact) 또는 CC(Cell Contact)과 WL(Word Line)의 전기적 쇼트를 방지하기 위해 워드선(WL)과 맞닿지 않는 표면을 선택적으로 산화시킨 후, 해당 표면을 선택적으로 자기조립단분자막(Self-Assembled Monolayer, SAM)이나 다른 표면 억제 분자(surface inhibition molecules)를 기상흡착 시킨다. To prevent electrical short between DC (Digit Contact) or CC (Cell Contact) and WL (Word Line) that do not match the pattern, selectively oxidize the surface that does not contact the word line, and then select the corresponding surface. As a result, self-assembled monolayer (SAM) or other surface inhibition molecules are vapor-adsorbed.

그 후, 전기적 쇼트가 발생하는 부분에 ALD 공정을 진행하여 그 부분을 패시베이션층(passivation layer)을 선택적으로 증착하고, 셀 접촉(CC)을 형성시키는 공정을 진행한다. 상기의 공정(선택적 산화→표면억제분자흡착→ALD 패시베이션층 형성)은 모두 기상에서 이뤄짐과 동시에, 나노 스케일에서의 표면반응을 기반으로 진행되기 때문에 미세 구조의 소자와 소자(또는 전극)간 불일치성으로 인한 결함을 회복하여 DRAM의 전기적 쇼트 문제를 해결할 수 있다.Thereafter, an ALD process is performed on a portion where an electrical short occurs, a passivation layer is selectively deposited on the portion, and a process of forming a cell contact (CC) is performed. Since the above processes (selective oxidation → surface inhibitory molecule adsorption → ALD passivation layer formation) are all carried out in the gas phase and proceed based on the surface reaction at the nanoscale, the microstructured device and the device (or electrode) are inconsistent. By recovering the defects caused by the DRAM, the electrical short problem of the DRAM can be solved.

반도체 소자 혹은 전자 소자의 특성을 향상시키기 위해서는 콘택트 저항을 낮추는 것이 매우 중요한데, 이를 위해 실리콘 기반의 전자 소자에서는 실리콘과 물리적 전기적으로 적합성이 뛰어난 금속 실리사이드를 콘택트로 사용해오고 있다.In order to improve the characteristics of a semiconductor device or an electronic device, it is very important to lower the contact resistance. To this end, in silicon-based electronic devices, metal silicide having excellent physical and electrical compatibility with silicon has been used as a contact.

한편, 금속 실리사이드를 제작하는 통상적인 방법은 실리콘 기판 위에 금속 박막을 증착하고 난 뒤, 열처리를 통해 실리콘과 금속 박막을 열적으로 반응시켜 금속 실리사이드를 형성하는 것이다. 이때 원하는 콘택트 부분에만 금속 실리사이드를 형성하기 위해서 금속 박막 증착 직후 에칭을 통한 패터닝(patterning)을 하거나, 금속 실리사이드가 형성된 후 에칭을 통해 패터닝을 하는 공정을 사용한다.On the other hand, a typical method of producing a metal silicide is to deposit a metal thin film on a silicon substrate, and then thermally react the silicon and the metal thin film through heat treatment to form a metal silicide. At this time, in order to form the metal silicide only on the desired contact portion, patterning is performed through etching immediately after deposition of the metal thin film, or patterning is performed through etching after the metal silicide is formed.

반도체 장치가 보다 고집적화됨에 따라 미스얼라인 마진의 확보가 어려워지고 있다. 따라서 상기 콘택홀을 형성하는 공정에서 미스얼라인이 발생할 수 있다. 이와 같이 미스얼라인이 발생하면, 노출 시키고자 하는 도전 패턴이 노출되지 않는 불량이 발생할 수 있으며 또는 반대로 노출되지 않아야 할 도전 패턴이 노출되는 불량이 발생할 수 있다. 이러한 불량이 발생하면, 상기 도전 패턴과 이후의 배선과의 전기적인 연결에 결함이 발생하여, 반도체 장치의 작동 불량이 유발된다. 또한, 상기 미스얼라인에 의해서 상기 콘택홀의 위치가 정확하지 못하면, 이후에 상기 콘택홀을 채우는 배선과 이웃하는 소자와의 전기적 절연 상에 문제점이 발생할 수 있다.As semiconductor devices become more highly integrated, it is becoming more difficult to secure misalignment margins. Therefore, misalignment may occur in the process of forming the contact hole. When a misalignment occurs in this way, a defect in which the conductive pattern to be exposed is not exposed may occur, or conversely, a defect in which the conductive pattern to be exposed is exposed may occur. When such a defect occurs, a defect occurs in the electrical connection between the conductive pattern and the subsequent wiring, causing a malfunction of the semiconductor device. In addition, if the position of the contact hole is not correct due to the misalignment, a problem may occur in electrical insulation between a wiring filling the contact hole and a neighboring device.

따라서, 반도체 소자의 미스얼라인의 결함 치유는 반도체 소자의 고집적화 및 미세화에 따른 특성 향상을 위해 매우 중요한 역할을 하게 된다.Therefore, the defect healing of the misalignment of the semiconductor device plays a very important role in improving the characteristics of the semiconductor device according to the high integration and miniaturization.

대한민국 등록특허 제10-1419533호Korean Patent Registration No. 10-1419533

본 발명은 메모리 소자의 미스얼라인의 결함을 해결하기 위한 메모리 소자 결함 회복 방법을 제공하는 것을 목적으로 한다. An object of the present invention is to provide a memory device defect recovery method for solving a memory device misalignment defect.

본 발명은 상기와 같은 문제점을 해결하기 위해 1) 제1물질층과 제2물질층이 동시에 노출되어 미스얼라인이 발생된 기판을 제공하는 단계; 2) 제1물질층 또는 제2물질층 중 어느 하나가 실리콘층인 경우 O2와 H2 가스를 이용하여 실리콘층을 선택적으로 산화시켜 실리콘 산화막을 형성하는 단계(선택적 산화); 3) 상기 실리콘 산화막에 자기조립단분자막(Self-Assembled Monolayer, SAM)을 흡착시키는 단계(표면 비활성화); 4) 실리콘층 이외의 물질층 상에 패시베이션 재료를 증착시키는 단계; 5) 상기 자기조립단분자막을 포함하는 실리콘 산화막을 에칭 공정에 의하여 제거하는 단계를 포함하는 선택적 증착에 의한 메모리 소자 결함 회복 방법을 제공한다. In order to solve the above problems, the present invention includes the steps of: 1) providing a substrate in which a first material layer and a second material layer are exposed at the same time to cause misalignment; 2) forming a silicon oxide film by selectively oxidizing the silicon layer using O 2 and H 2 gas when either the first material layer or the second material layer is a silicon layer (selective oxidation); 3) adsorbing a self-assembled monolayer (SAM) on the silicon oxide film (surface deactivation); 4) depositing a passivation material on a material layer other than the silicon layer; 5) Provides a method for recovering defects in a memory device by selective deposition, including removing a silicon oxide film including the self-assembled monolayer by an etching process.

또한 단계 5) 이후에 셀 접촉(Cell Contact)을 형성시키는 단계를 더 포함할 수 있다. In addition, it may further include forming a cell contact (Cell Contact) after step 5).

상기 2) 단계에서, 온도는 750 ~ 950℃이고, 총 기체에 대한 상기 O2 가스의 기체분압은 5 ~ 20%인 것을 특징으로 한다.In step 2), the temperature is 750 to 950°C, and the gas partial pressure of the O 2 gas relative to the total gas is 5 to 20%.

상기 자기조립단분자막은 디메틸실란 디메틸아민(dimethylsilane dimethylamine; DMSDMA), 트리메틸실란 디메틸아민(TMSDMA) 비스(디메틸아미노)디메틸실란(Bis(dimethylamino)dimethylsilane; DMADMS) 또는 (디메틸아미노)트리메틸실란((Dimethylamino)trimethylsilane; DMATMS) 및 다른 알킬 아민 실란을 흡착시킴으로써 형성되는 것을 특징으로 하며, 특히 비스(디메틸아미노)디메틸실란(Bis(dimethylamino)dimethylsilane; DMADMS) 또는 (디메틸아미노)트리메틸실란((Dimethylamino)trimethylsilane; DMATMS) 중 어느 하나를 흡착시키? 것이 바람직하며, 상기 자기조립단분자막으로 흡착된 실리콘 산화막은 표면의 물 접촉각은 80 ~ 90°인 것을 특징으로 한다. The self-assembled monolayer is dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA) bis (dimethylamino) dimethyl silane (Bis (dimethylamino) dimethylsilane; DMADMS) or (dimethylamino) trimethyl silane ((Dimethylamino)). It is characterized by being formed by adsorbing trimethylsilane; DMATMS and other alkyl amine silanes, and in particular, bis(dimethylamino)dimethylsilane (DMADMS) or (dimethylamino)trimethylsilane; DMATMS ) To adsorb any one of them? It is preferable that the silicon oxide film adsorbed by the self-assembled monolayer has a water contact angle of 80 to 90° on its surface.

상기 3) 단계 및 4) 단계는 화학적 기상 증착법, 금속 유기 화학적 기상 증착법, 분자빔 에피택시, 및 원자층 증착법 등의 방법으로 형성할 수 있으나, 원자층 증착법(Atomic Layer Deposition)에 의하여 수행되는 것이 바람직하다. Steps 3) and 4) may be formed by a chemical vapor deposition method, a metal organic chemical vapor deposition method, a molecular beam epitaxy, and an atomic layer deposition method, but is performed by an atomic layer deposition method. desirable.

따라서 본 발명에서 사용하고 있는 자기조립단분자막 흡착으로 인한 표면 비활성화 단계는 진공 챔버 내에서 짧은 시간 노출을 통하여 균일한 표면 억제막의 형성이 가능하고, 열적으로 매우 안정하여 고온의 공정에 적용이 가능하고, 짧은 분자 길이로 인해 3차원의 복잡한 나노구조 안에 입체 장애 없이 고밀도의 균일한 표면 억제막의 형성이 가능하다. Therefore, in the step of deactivating the surface due to adsorption of the self-assembled monolayer used in the present invention, a uniform surface suppression film can be formed through a short time exposure in a vacuum chamber, and it is thermally very stable and can be applied to a high-temperature process. Due to the short molecular length, it is possible to form a high-density and uniform surface suppression film without steric hindrance in a three-dimensional complex nanostructure.

상기 3) 단계는 기판의 온도가 600℃ 이하인 것을 특징으로 하며, 기판의 온도가 600℃를 초과하는 경우, 자기조립단분자막의 형성 과정에서 열화가 일어나서 4) 단계 페시베이션 박막을 선택적으로 증착하는 공정의 실현이 불가능하게 된다. 화학적으로 흡착된 2) 단계의 SAM 물질의 경우, 600℃ 이상에서 열화가 되는 것으로 알려져 있다. Step 3) is characterized in that the temperature of the substrate is 600°C or less, and when the temperature of the substrate exceeds 600°C, deterioration occurs in the process of forming the self-assembled monolayer, and the 4) step is a process of selectively depositing a passivation thin film. Becomes impossible to realize. In the case of the chemically adsorbed SAM material in step 2), it is known to deteriorate above 600°C.

상기 3) 단계의 온도는 후속 단계의 ALD 패시베이션 박막 형성 공정과 함께, 한 챔버 내에서 증착이 이뤄진다면, 동일한 온도에서 3,4단계를 온도 조건의 변화 없이 동시에 공정을 수행할 수 있다는 장점이 있다. 즉, 상기 온도는 SAM 물질이 열화되지 않는 선에서는 4단계에서 사용하는 insulating material의 공정온도와 관련이 있다. 상기 기판 온도의 하한은 50℃가 바람직하지만 이에 제한되는 것은 아니며, 4) 단계의 공정 온도와 관련하여 적절하게 조절될 수 있다. The temperature of step 3) has the advantage that if deposition is performed in one chamber together with the ALD passivation thin film formation process of the subsequent step, steps 3 and 4 can be simultaneously performed at the same temperature without changing the temperature conditions. . That is, the temperature is related to the process temperature of the insulating material used in step 4 as long as the SAM material does not deteriorate. The lower limit of the substrate temperature is preferably 50° C., but is not limited thereto, and may be appropriately adjusted in relation to the process temperature of step 4).

상기 4) 단계에서 상기 실리콘층 이외의 물질층 상에 실리콘질화막(SixNy)을 형성시키는 것을 특징으로 한다. 상기 실리콘질화막은 CC(Cell Contact)와 WL(Word Line) 간의 배리어막으로서, 텅스텐-실리콘 타겟(W-Si target) 또는 텅스텐-실리콘 소스(W-Si source)를 이용하여 화학기상증착법(CVD), 원자층증착법(ALD)을 통해 형성할 수 있으나, 본 발명의 기술적 특징에 비추어 볼 때 원자층증착법(ALD)을 통해 형성하는 것이 바람직하며, 이때 사용되는 전구체로는 실란(silane; SiH4), 디클로로실란(dichlorosil ane; SiCl2H2), 디실란(disilane; Si2H6), TEOS 등을 사용할 수 있다.In step 4), a silicon nitride film (Si x N y ) is formed on a material layer other than the silicon layer. The silicon nitride film is a barrier film between CC (Cell Contact) and WL (Word Line), and is a chemical vapor deposition method (CVD) using a tungsten-silicon target or a tungsten-silicon source. , Although it can be formed through atomic layer deposition (ALD), in view of the technical features of the present invention, it is preferable to form through atomic layer deposition (ALD), and the precursor used at this time is silane (SiH 4 ) , Dichlorosilane (SiCl 2 H 2 ), disilane (Si 2 H 6 ), TEOS, and the like may be used.

본 발명의 다른 실시 예에서, 상기 메모리 소자는 DRAM(Dynamic random-access memory)인 것을 특징으로 한다. In another embodiment of the present invention, the memory device is a dynamic random-access memory (DRAM).

본 발명은 DRAM 이외에도 반도체에서 컨택을 요구하는 모든 제작 공정(소자-소자, 소자-전극, 전극-전극 등등)에서 발생하는 포토리소그라피 기술의 불일치성으로 인한 전기적 쇼트를 방지하기 위한 결함 회복 기술로서 나노 스케일 패터닝 공정의 단점을 보완해줄 뿐만 아니라 모든 공정이 진공 상에서 이루어지기 때문에 활용하면 현재의 반도체 공정에 직접적으로 적용이 가능하다.The present invention is a nanoscale defect recovery technology for preventing electrical short due to inconsistency of photolithography technology that occurs in all manufacturing processes (device-device, device-electrode, electrode-electrode, etc.) that require contact in semiconductors other than DRAM. Not only does it compensate for the disadvantages of the patterning process, but it can be directly applied to the current semiconductor process by utilizing it because all processes are performed in a vacuum.

도 1은 본 발명의 소자 결함 회복 방법의 개략도이다.
도 2는 수소 및 산소 분압에 따른 실리콘과 텅스텐의 선택적 산화 관계를 나타내는 그래프이다.
도 3은 DMADMS 및 DMATMS 분자의 SiO2 기판에서 흡착과정을 나타내는 개략도이다.
도 4는 Si 와 SiO2 기판에서 DMADMS 노출 시간에 따른 접촉각(Contact Angle)의 변화를 나타낸 그래프이다.
도 5는 Ru 증착을 위한 ALD 공정(100 cycles) 이후 각 기판에서 FESEM 사진이다; a) Si (b) DMADMS/Si (c) SiO2 (d) DMADMS/SiO2.1 is a schematic diagram of a device defect recovery method of the present invention.
2 is a graph showing a selective oxidation relationship between silicon and tungsten according to partial pressures of hydrogen and oxygen.
3 is a schematic diagram showing the adsorption process of DMADMS and DMATMS molecules on a SiO 2 substrate.
4 is a graph showing a change in contact angle according to DMADMS exposure time in Si and SiO 2 substrates.
5 is a FESEM picture of each substrate after the ALD process (100 cycles) for Ru deposition; a) Si (b) DMADMS/Si (c) SiO 2 (d) DMADMS/SiO 2 .

이하, 본 발명을 보다 상세하게 설명한다.Hereinafter, the present invention will be described in more detail.

본 발명은 반도체 소자에서 접합 영역에서의 결함을 치유하기 위한 방법에 관한 것으로서, 본 발명은 크게 4단계의 프로세스(process)에 의해 구현된다.The present invention relates to a method for healing defects in a junction region in a semiconductor device, and the present invention is largely implemented by a four-step process.

먼저 제1공정은 박막 패터닝 공정 중 발생하는 접합면 간 불일치가 발생하는 경우 실리콘(Si) 기판을 선택적 산화시키는 단계이다. 제1공정 이전에 제1물질층과 제2물질층이 동시에 노출되어 미스얼라인이 발생된 기판을 제공하는 단계가 추가될 수 있다. First, the first process is a step of selectively oxidizing the silicon (Si) substrate when mismatch between bonding surfaces occurs during the thin film patterning process. Prior to the first process, a step of providing a substrate in which the first material layer and the second material layer are simultaneously exposed and misaligned may be added.

즉, 패턴과 일치하지 않는 DC(Digit Contact) 또는 CC(Cell Contact)와 WL(Word Line)의 전기적 쇼트를 방지하기 위해 WL과 맞닿지 않는 표면을 선택적으로 산화시키는 단계이다. That is, in order to prevent electrical short between DC (Digit Contact) or CC (Cell Contact) and WL (Word Line) that do not match the pattern, a step of selectively oxidizing a surface that does not contact WL.

접합면 간 불일치 상태에서는 텅스텐 및 실리콘이 동시에 존재하는 조건으로 선택적 산화공정으로 텡스텐은 산화시키지 않고, 실리콘 기판만 산화시켜 선택적 실리콘 산화막을 형성한다. In the state of mismatch between the bonding surfaces, tungsten is not oxidized by a selective oxidation process under the condition that tungsten and silicon are present at the same time, but only the silicon substrate is oxidized to form a selective silicon oxide film.

반도체 제조 소자를 이루는 트랜지스터의 게이트 전극은 흔히 텅스텐(W)으로 형성된다. 게이트 전극 패터닝 공정을 거친 후 게이트 전극 측벽을 산화시키기 위해 선택적 산화 공정을 실시하여 게이트 패터닝을 위한 식각 공정에서 발생한 플라즈마 손상(plasma damage)을 제거한다. 이러한 선택적 산화는 O2와 H2의 분압을 조절하여 텅스텐의 산화는 일어나지 않고 폴리실리콘 등의 실리콘만이 산화되어 실리콘 산화막(SiO2)을 형성하게 된다. A gate electrode of a transistor constituting a semiconductor manufacturing device is often formed of tungsten (W). After the gate electrode patterning process, a selective oxidation process is performed to oxidize the sidewalls of the gate electrode to remove plasma damage generated in the etching process for gate patterning. In this selective oxidation, by controlling the partial pressures of O 2 and H 2 , oxidation of tungsten does not occur, and only silicon such as polysilicon is oxidized to form a silicon oxide film (SiO 2 ).

선택적 산화 공정을 진행할 때 실리콘 산화막을 두께를 증가시키면서도 텅스텐의 산화가 일어나지 않도록 하기 위해서는 O2 와 H2의 텅스텐과의 상호 작용을 적절히 이용하여야 한다. 도 2는 850℃에서 O2와 H2의 분압 및 온도에 따른 실리콘(Si)의 선택적 산화 관계를 보이는 그래프이다. 도시되지 않았으나 본 발명자는 텅스텐옥사이드(WOx)의 텅스텐(W)으로의 환원은 750 ~ 950℃의 온도에서 산소가 5 ~ 20%인 경우에 실리콘의 선택적 산화가 80%이상 나타나는 것을 확인하였다.When performing the selective oxidation process, in order to increase the thickness of the silicon oxide layer and prevent tungsten oxidation from occurring , the interaction between O 2 and H 2 with tungsten should be properly used. 2 is a graph showing a selective oxidation relationship of silicon (Si) depending on partial pressures and temperatures of O 2 and H 2 at 850°C. Although not shown, the present inventors have confirmed that when the reduction of tungsten oxide (WOx) to tungsten (W) occurs at a temperature of 750 to 950° C. and oxygen is 5 to 20%, selective oxidation of silicon occurs by 80% or more.

텅스텐의 산화와 환원 반응의 균형을 유지시켜주는 것은 O2 와 H2의 비율이므로, O2 와 H2의 균형 관계에 변화를 일으킴으로써 실리콘 산화막의 두께를 적절하게 증가시킬 수 있다. O2의 유량을 증대시키면 실리콘의 산화막의 두께는 증가하나 동시에 텅스텐의 산화도 증가하기 때문에 수소 유량의 증대를 통해 텅스텐의 환원을 증가시켜야 한다. Since it is the ratio of O 2 and H 2 that maintains the balance between the oxidation and reduction reactions of tungsten, it is possible to appropriately increase the thickness of the silicon oxide film by causing a change in the balance relationship between O 2 and H 2. Increasing the flow rate of O 2 increases the thickness of the silicon oxide film, but increases the oxidation of tungsten at the same time. Therefore, the reduction of tungsten must be increased by increasing the flow rate of hydrogen.

제2공정은 표면 억제 공정으로, 상기 선택적으로 산화된 표면에 자기조립단분자막(Self-Assembled Monolayer, SAM)이나 다른 표면 억제 분자(surface inhibition molecules)를 기상흡착시킨다. The second process is a surface suppression process, in which a self-assembled monolayer (SAM) or other surface inhibition molecules are vapor-adsorbed on the selectively oxidized surface.

상기 표면 억제 공정은 SiO2 기판 표면상에 짧은 chain 길이를 갖는 Si 기반의 DMADMS-비스(디메틸아미노)디메틸실란(Bis(dimethylamino)dimethylsilane), DMATMS-(디메틸아미노)트리메틸실란((Dimethylamino)trimethylsilane)을 억제제(inhibitor)로써 흡착시킴으로써 이루어진다. The surface suppression process includes Si-based DMADMS-bis(dimethylamino)dimethylsilane, DMATMS-(dimethylamino)trimethylsilane having a short chain length on the SiO 2 substrate surface. Is made by adsorbing it as an inhibitor.

기존에 자기조립단분자막(Self-assembled monolayers, SAMs)을 이용한 AS-ALD 방법의 경우 주로 솔루션 공정을 활용하여 오랜 시간(>24 hr) 동안 알킬 채인(alkyl chain) 길이가 12 이상의 벌키한(분자높이 > 수nm) 표면억제막(bulky inhibition layer)을 형성한 것과 비교하여 다음과 같은 몇 가지 이점을 갖는다. 본 발명에서 제안하는 표면 억제 분자막은 알킬실릴기 그룹을 가진 분자의 선택적인 표면 기상 실릴화(gas phase silylation) 반응을 통해 (i) 진공 챔버 내 짧은 시간 노출(수십초 이내)을 통해 균일하고 오염이 없는 고품질의 표면 억제막의 형성이 가능하다. 또한, (ii) 절연체 표면 -OH 그룹에 실릴화를 통해 치환 증착된 실릴그룹(R3Si) 내 silicon-carbon 결합의 경우 열적으로 매우 안정(> 600℃)하여 고온의 고품질의 박막 형성을 필요로 하는 공정에 적용이 가능하다 (SAMs 열화: < 350℃). (iii) 뿐만 아니라, 짧은 분자 길이로 인해 3차원의 복잡한 나노구조 안에 입체 장애 없이 고밀도의 균일한 표면 억제막의 형성이 가능하여 3차원 선택 박막 형성을 가능하게 해주므로 다양한 나노소재 분야에 적용을 가능하게 해준다. In the case of the existing AS-ALD method using self-assembled monolayers (SAMs), the length of the alkyl chain is 12 or more for a long time (>24 hr) by mainly using the solution process (molecular height). > Several nm) Compared to the bulky inhibition layer formed, it has several advantages as follows. The surface-inhibiting molecular membrane proposed in the present invention is uniform and uniform through (i) a short time exposure (within tens of seconds) in a vacuum chamber through a selective surface gas phase silylation reaction of molecules having an alkylsilyl group. It is possible to form a high-quality surface suppression film without contamination. In addition, (ii) the silicon-carbon bond in the silyl group (R 3 Si), which is deposited on the surface of the insulator through silylation, is very thermally stable (> 600°C), so it is necessary to form a high-quality thin film at high temperature. Applicable to the process of (SAMs deterioration: <350℃). (iii) In addition, due to the short molecular length, it is possible to form a high-density uniform surface suppression film without steric hindrance in a three-dimensional complex nanostructure, enabling the formation of a three-dimensional selective thin film, so it can be applied to various nanomaterial fields Lets you do it.

기존의 AS-ALD 공정에서는, 원자층 박막증착 공정을 실시하기 전에 박막 성장을 원치 않는 영역에 자기조립단분자막을 형성하여 ALD 전구체의 화학 흡착을 억제하여 특정 지역에만 박막 증착이 가능하게 해준다. 그러나 SAMs을 기반으로 한 AS-ALD 에는 몇 가지 한계가 있는데, 솔루션 공정을 활용한 긴 코팅시간, 용액 상에서 일어날 수 있는 분자막 오염이슈와 서로 간의 물리적인 흡착 등으로 인한 상호 간섭이 발생하여 기판 위에 단원자 분자막을 균일하게 형성하는 것이 매우 힘들다. 뿐만 아니라, 3차원 나노구조에 활용 시 형성된 SAM의 긴 chain 길이로 인한 상호 입체 장애가 발생하여 SAMs이 만나는 에지 부분에 결함이 생기거나 균일하게 흡착이 되지 못한다는 것이다. 따라서 실제 나노스케일 반도체 공정에 쓰이기 어렵다.In the existing AS-ALD process, a self-assembled monolayer is formed in an area where the thin film is not desired to grow before performing the atomic layer thin film deposition process, thereby suppressing the chemical adsorption of the ALD precursor, allowing the deposition of a thin film only in a specific area. However, AS-ALD based on SAMs has some limitations, such as a long coating time using the solution process, molecular film contamination that may occur in the solution, and mutual interference due to physical adsorption between each other, causing the It is very difficult to uniformly form a monoatomic molecular film. In addition, when used in a 3D nanostructure, a steric hindrance occurs due to the long chain length of the SAM formed, resulting in defects at the edges where the SAMs meet, or they cannot be uniformly adsorbed. Therefore, it is difficult to be used in the actual nanoscale semiconductor process.

이러한 SAM을 기반으로 한 AS-ALD의 여러가지 한계점들을 극복하기 위해서, 본 발명자는 알킬실릴기 그룹을 가진 분자의 기상 실릴화 반응을 통해 억제제(inhibitor)를 표면에 선택적으로 SiO2 표면에 흡착시킴으로써 공정이 간단하며 chain 길이가 짧으며 열적으로 안정성이 뛰어난 분자막을 형성시켰다.In order to overcome the various limitations of AS-ALD based on this SAM, the present inventors process by selectively adsorbing an inhibitor onto the surface of SiO 2 through a gas phase silylation reaction of a molecule having an alkylsilyl group. This simple, short chain length, and excellent thermal stability formed a molecular film.

상기 제2공정에 대한 개략적인 실험 방법은 도 3에 도시되어 있다. A schematic experimental method for the second process is shown in FIG. 3.

본 발명자는 ALD를 이용한 단일 cycle로 DMADMS 을 (5, 10, 20 및 30초) pulse 및 30 sccm의 Ar gas 10초 purge으로 진행하였다. 기판 온도는 150℃이고, DMATMS의 흡착에 대해서도 동일한 실험 조건이 수행되었다. DMADMS 와 DMATMS로 코팅된 SiO2 기판은 표면 물 접촉각이 80 ~ 90°로 소수성 표면으로 성질이 변화하였다(도 4).The present inventors performed DMADMS with a single cycle using ALD (5, 10, 20 and 30 seconds) pulse and 30 sccm of Ar gas 10 seconds purge. The substrate temperature was 150° C., and the same experimental conditions were performed for adsorption of DMATMS. The properties of the SiO 2 substrate coated with DMADMS and DMATMS were changed to a hydrophobic surface with a surface water contact angle of 80 to 90° (FIG. 4).

본 발명자는 Ru 및 Al2O3를 사용하여 AS-ALD에 대한 DMADMS/SiO2 및 DMATMS/SiO2의 blocking 물성을 연구했다. Ru 증착을 위해 Carish(dicarbonyl-bis(5-methyl-2,4-hexanediketonato) Ru(II), C16H22O6Ru, Tanaka, Japan)와 산소 가스가 각각 전구체와 반응물(reactant)로 사용되었다. SiO2 및 DMADMS/SiO2 기판을 ALD 공정에 사용하였다. Carish 전구체의 온도 및 기판 온도는 각각 100 및 283℃로 유지시켰다. 전구체와 산소 가스는 각각의 반응 사이에 7초의 질소 가스 purge 와 함께 각각 (6s 및 5s)의 pulse를 설정하였다. Carish 전구체의 carrier 가스로써 100sccm의 질소 가스를 사용하였다. SiO2 및 DMADMS/SiO2 상에 Ru 증착을 위해 약 1Å/cycle의 성장 속도를 갖는 100 ALD cycle 공정을 진행하였다.The present inventors studied the blocking properties of DMADMS/SiO 2 and DMATMS/SiO 2 for AS-ALD using Ru and Al 2 O 3. Carish (dicarbonyl-bis(5-methyl-2,4-hexanediketonato) Ru(II), C 16 H 22 O 6 Ru, Tanaka, Japan) and oxygen gas are used as precursors and reactants for Ru deposition, respectively. Became. SiO 2 and DMADMS/SiO 2 substrates were used in the ALD process. The temperature of the Carish precursor and the substrate temperature were maintained at 100 and 283°C, respectively. For the precursor and oxygen gas, pulses of (6s and 5s) were set, respectively, with a nitrogen gas purge of 7 seconds between each reaction. 100 sccm of nitrogen gas was used as the carrier gas of the carish precursor. For the deposition of Ru on SiO 2 and DMADMS/SiO 2 , a 100 ALD cycle process having a growth rate of about 1 Å/cycle was performed.

또한 DMADMS/SiO2 및 DMATMS/SiO2 기판에 대한 Al2O3를 ALD 공정을 통해 blocking 물성을 테스트하였다. 여기서는 트리메틸알루미늄(trimethylaluminum, TMA)과 H2O가 각각 전구체와 반응물로 사용되었다. TMA 및 H2O는 각각 실온으로 유지하였다. Al2O3 공정의 한 cycle은 TMA pulse (5초), N2 purge (15초), H2O pulse (5초) 및 N2 purge(15초)로 구성하였다. 본 발명자는 150℃에서 DMADMS/SiO2 및 DMATMS/SiO2 기판에 대한 Al2O3 공정을 5 cycle을 진행하였다. 여기서 금속 산화물(metal oxide) 막 두께는 ALD cycle의 수를 조절하여 제어할 수 있다.In addition, Al 2 O 3 for DMADMS/SiO 2 and DMATMS/SiO 2 substrates were tested for blocking properties through the ALD process. Here, trimethylaluminum (TMA) and H 2 O were used as precursors and reactants, respectively. TMA and H 2 O were kept at room temperature, respectively. One cycle of the Al 2 O 3 process consisted of TMA pulse (5 seconds), N 2 purge (15 seconds), H 2 O pulse (5 seconds) and N 2 purge (15 seconds). The present inventors performed 5 cycles of the Al 2 O 3 process for the DMADMS/SiO 2 and DMATMS/SiO 2 substrates at 150°C. Here, the metal oxide film thickness can be controlled by adjusting the number of ALD cycles.

도 5를 참조하면 DMADMS 및 DMATMS의 blocking 능력은 Ru에 대해서는 우수했지만 Al2O3에 대해서는 그렇지 못했다. 이것은 각 전구체의 크기 또는 고유의 반응성 차이로 인한 것으로 설명된다.Referring to FIG. 5, the blocking ability of DMADMS and DMATMS was excellent for Ru, but not for Al 2 O 3 . This is explained by differences in the size or intrinsic reactivity of each precursor.

제3공정은 CC(Cell Contact)와 WL(Word Line)의 전기적 쇼트를 방지하기 위하여 패시베이션 재료를 도전성 재료 상에 증착시키는 단계이다. The third process is a step of depositing a passivation material on a conductive material to prevent electrical short between CC (Cell Contact) and WL (Word Line).

절연성 재료로서는 상기 도전성 재료 원소의 산소화합물, 질소화합물, 탄소화합물, 또는 할로겐화합물의 단층으로 형성할 수 있다. 또한, 이들의 적층을 사용할 수 있다. 대표적으로는 질화알루미늄, 질화규소, 산화규소, 실리콘 탄화물, 질화탄소, 염화알루미늄 등이 있다. 또한, 폴리이미드, 폴리아미드, BCB(벤조사이클로부텐), 아크릴 등의 유기수지를 사용할 수 있다. 또한, 실록산, 폴리실라잔 등을 사용할 수 있다. 또 상기 절연성 재료에 한정되지 않으며, 절연성 재료이면 적절하게 사용할 수 있다The insulating material may be formed of a single layer of an oxygen compound, a nitrogen compound, a carbon compound, or a halogen compound of the conductive material element. In addition, laminations of these can be used. Representative examples include aluminum nitride, silicon nitride, silicon oxide, silicon carbide, carbon nitride, and aluminum chloride. In addition, organic resins such as polyimide, polyamide, BCB (benzocyclobutene), and acrylic can be used. In addition, siloxane, polysilazane, and the like can be used. Further, it is not limited to the above insulating material, and any insulating material can be suitably used.

본 발명에서는 WL(Word Line)의 도전성 재료인 텅스텐 상에 실리콘질화막(SixNy)을 형성하는 것이 바람직하다. 상기 실리콘질화막은 CC(Cell Contact)와 WL(Word Line) 간의 배리어막으로서, 텅스텐-실리콘 타겟(W-Si target) 또는 텅스텐-실리콘 소스(W-Si source)를 이용하여 스퍼터링법(sputtering), 화학기상증착법 (CVD), 원자층증착법(ALD)을 통해 형성할 수 있으나, 본 발명의 기술적 특징에 비추어 볼 때 원자층증착법(ALD)을 통해 형성하는 것이 바람직하며, 이때 사용되는 전구체로는 실란(silane; SiH4), 디클로로실란(dichlorosil ane; SiCl2H2), 디실란(disilane; Si2H6), TEOS 등을 사용할 수 있다.In the present invention, it is preferable to form a silicon nitride film (Si x N y ) on tungsten, which is a conductive material of a word line (WL). The silicon nitride film is a barrier film between CC (Cell Contact) and WL (Word Line), and sputtering using a tungsten-silicon target or a tungsten-silicon source (W-Si source), Although it can be formed through chemical vapor deposition (CVD) and atomic layer deposition (ALD), in view of the technical features of the present invention, it is preferable to form through atomic layer deposition (ALD), and the precursor used at this time is silane (silane; SiH 4 ), dichlorosil ane (SiCl 2 H 2 ), disilane (Si 2 H 6 ), TEOS, and the like may be used.

상기 실리콘질화막은 400℃ 내지 500℃의 저온의 온도에서 원자층증착(ALD; Atomic Layer Deposition) 방식으로 형성할 수 있다. 이를 위해 먼저, 반도체 기판을 증착 장비 내에 로딩시킨다. 여기서 증착 장비는 복수 개의 웨이퍼가 장착되는 배치(batch) 타입의 플라즈마 장비를 이용한다. 다음에 증착 장비 내에 질화 증착 소스를 공급한다. 질화 증착 소스는 디클로로실란(DCS; Dichlorosilane, SiCl2H2) 가스와 암모니아(NH3) 가스를 포함한다. 구체적으로, 플라즈마 장비 내에 디클로로실란(SiCl2H2) 가스를 공급하면서 바이어스를 인가한다. 그러면 실리콘질화막이 형성될 피증착면, 즉, 텅스텐의 노출면 상에 실리콘(Si)이 흡착된다. 다음에 증착 장비 내에 퍼지(purge) 가스를 주입하여 미흡착된 실리콘을 배기시킨다. 계속해서 증착 장비 내에 암모니아(NH3) 가스를 공급하면서 플라즈마를 구동(plasma turn on)시킨다. 그러면 텅스텐 상에 흡착된 실리콘(Si)과 암모니아 가스의 질소(N)가 결합하여 실리콘질화막(SixNy)의 단원자층(mono atomic layer)을 형성한다. 다음에 증착 장비 내에 퍼지 가스를 주입하여 증착 장비 내부를 배기시킨다. 이러한 실리콘질화막의 단원자층은 한 싸이클(cycle)당 0.8Å의 증착 속도로 증착된다. 본 발명의 실시예에서, 실리콘질화막은 원자층증착방식을 적어도 50 싸이클을 진행하여 20Å 내지 50Å의 두께로 증착하는 것이 바람직하다. 상기 형성된 실리콘질화막은 CC(Cell Contact)와 WL(Word Line) 간의 접촉을 방지할 수 있다. The silicon nitride film may be formed by an atomic layer deposition (ALD) method at a low temperature of 400°C to 500°C. To do this, first, a semiconductor substrate is loaded into a deposition equipment. Here, the deposition equipment uses a batch-type plasma equipment on which a plurality of wafers are mounted. Next, a nitride deposition source is supplied into the deposition equipment. The nitride deposition source includes a dichlorosilane (DCS; SiCl 2 H 2 ) gas and ammonia (NH 3 ) gas. Specifically, a bias is applied while supplying a dichlorosilane (SiCl 2 H 2) gas into the plasma equipment. Then, silicon (Si) is adsorbed on the deposited surface on which the silicon nitride film is to be formed, that is, the exposed surface of tungsten. Next, a purge gas is injected into the deposition equipment to exhaust unadsorbed silicon. Subsequently, plasma is turned on while supplying ammonia (NH 3) gas into the deposition equipment. Then, silicon (Si) adsorbed on tungsten and nitrogen (N) of ammonia gas are combined to form a mono atomic layer of a silicon nitride film (Si x N y ). Next, a purge gas is injected into the evaporation equipment to exhaust the inside of the evaporation equipment. The monoatomic layer of the silicon nitride film is deposited at a deposition rate of 0.8 Å per cycle. In an embodiment of the present invention, the silicon nitride film is preferably deposited to a thickness of 20 Å to 50 Å by performing at least 50 cycles of an atomic layer deposition method. The formed silicon nitride layer may prevent contact between a cell contact (CC) and a word line (WL).

제4공정은 에칭 공정으로 자기조립단분자막(SAM)에 의하여 코팅된 실리콘 산화막(SiOx)을 제거하는 단계이다. 에칭 공정은 실리콘 산화막을 제거할 수 있는 공지의 에칭 방법을 사용할 수 있다. 바람직하게 HF 등을 이용한 습식 식각에 의해 이루어질 수 있으나, 반드시 이에 한정되는 것이 아니며, 공지되어 있는 임의의 방법을 사용하여 습식 또는 건식 식각하여 제거할 수도 있다.The fourth process is a step of removing the silicon oxide film (SiO x ) coated by the self-assembled monolayer (SAM) by an etching process. The etching process can use a known etching method capable of removing the silicon oxide film. It may be preferably performed by wet etching using HF or the like, but is not limited thereto, and may be removed by wet or dry etching using any known method.

이후 셀 접촉(Cell Contact)을 형성시키면, 컨택면 간 불일치성(Contact Mismatch or Misaligned issue)을 해결하여 DRAM에서 발생하는 전기적 쇼트 (Electrical short) 문제를 방지할 수 있다. Thereafter, when a cell contact is formed, a contact mismatch or misaligned issue can be solved to prevent an electrical short problem occurring in DRAM.

선행기술에 비해 본 제안 기술은 DRAM 이외에도 반도체에서 컨택을 요구하는 모든 제작 공정(소자-소자, 소자-전극, 전극-전극 등등)에서 발생하는 포토리소그라피 기술의 불일치성으로 인한 전기적 쇼트를 방지하기 위한 결함 회복 기술로서 나노 스케일 패터닝 공정의 단점을 보완해줄 뿐만 아니라 모든 공정이 진공 상에서 이루어지기 때문에 활용하면 현재의 반도체 공정에 직접적으로 적용이 가능할 것으로 판단한다. Compared to the prior art, this proposed technology is a defect to prevent electrical short due to inconsistency of photolithography technology that occurs in all manufacturing processes (device-device, device-electrode, electrode-electrode, etc.) that require contact in semiconductors other than DRAM. As a recovery technology, it not only compensates for the shortcomings of the nanoscale patterning process, but because all processes are performed in a vacuum, it is considered that it can be directly applied to the current semiconductor process.

현재 접촉 불일치(Contact Mismatch)을 위한 AS-ALD 결함 회복 기술은 기존의 보고된 여러 가지 원자층 증착 기술, 선택적 증착 기술과 본 연구진이 보유한 기술을 융합하여 성취될 수 있을 것이라고 판단된다.It is believed that the current AS-ALD defect recovery technology for contact mismatch can be achieved by fusion of several previously reported atomic layer deposition techniques, selective deposition techniques, and our own technology.

- 선택적 증착 공정 (Selective deposition process): 기존의 공정은 대부분 원하지 않는 기판을 선택적으로 passivation하기 위해 리소그래피에서의 Photo-resist(PR)을 코팅한 후, Mask 공정, PR 제거(PR removal)의 공정을 진행하거나, 자기조립단분자막(Self-Assembled Monolayer, SAM)을 용액 상에서 24시간 이상 코팅을 하는 공정이 진행되어 왔다. -Selective deposition process : In the existing process, most of the processes of photo-resist (PR) in lithography are coated in order to selectively passivation of unwanted substrates, and then the mask process and PR removal process are performed. Alternatively, a process of coating a self-assembled monolayer (SAM) on a solution for 24 hours or more has been conducted.

하지만 본 기술에서 제안하는 선택적 증착 공정은 기상에서 선택적인 산화법과 표면억제분자흡착 공정을 활용하여 표면 억제층을 선택적으로 형성하고, 후속 ALD 공정을 이용한 선택적인 passivation layer의 성장을 진행하여 노출된 전극 부분을 보호한다. However, in the selective deposition process proposed in this technology, a surface suppression layer is selectively formed using a selective oxidation method and a surface suppression molecule adsorption process in the vapor phase, and the exposed electrode is grown by selectively growing a passivation layer using a subsequent ALD process. Protect the part.

- ALD process: 대부분 ALD 공정이 솔루션 상에서 장시간 형성된 SAM molecules 위에서 진행되는 반면, 본 제안기술은 기상에서 ALD 전구체를 활용한 SDP 물질을 통하여 표면을 선택적으로 passivation 시킬 수 있으며 동시에 후속 CC 또는 DC 증착 공정이 in-situ로 이루어 질 수 있다는 장점이 있다.-ALD process: While most of the ALD processes are performed on the SAM molecules formed for a long time in the solution, this proposed technology can selectively passivation the surface through the SDP material using the ALD precursor in the vapor phase, and at the same time, the subsequent CC or DC deposition process is There is an advantage that it can be done in-situ.

- Defect healing process: 기존의 공정은 대부분 증착(Deposition)→ 식각(Etching)→ 증착(Deposition)→ 식각(Etching)→의 탑다운(Top-down) 기반 반복 공정으로서 결함이 발생할 경우, 수정이 매우 어렵다는 단점을 가지고 있다. 본 기술에서 제안하는 결함 회복 방법은 선택적 산화법, 표면억제분사 물질을 이용한 SDP 기술, ALD 공정을 기반으로 선택적으로 박막을 모두 기상에서 in-situ로 성장시켜 결함을 회복시킬 수 있으므로 사전 공정에서 컨택 간 불일치가 발생할 경우, 본 발명법을 통해 빠른 수정이 가능하며 현재의 진공 기반 반도체 직접회로 공정과의 호환성이 있다. -Defect healing process: Most of the existing processes are top-down based repeating processes of Deposition → Etching → Deposition → Etching → When defects occur, correction is very high. It has the disadvantage of being difficult. The defect recovery method proposed in this technology is based on the selective oxidation method, SDP technology using surface inhibitory spraying material, and ALD process, and the defects can be recovered by selectively growing all thin films in-situ in the gas phase. When inconsistency occurs, quick correction is possible through the method of the present invention, and there is compatibility with the current vacuum-based semiconductor integrated circuit process.

Claims (10)

1) 제1물질층과 제2물질층이 동시에 노출되어 미스얼라인이 발생된 기판을 제공하는 단계;
2) 제1물질층 또는 제2물질층 중 어느 하나가 실리콘층인 경우 O2와 H2 가스를 이용하여 실리콘층을 선택적으로 산화시켜 실리콘 산화막을 형성하는 단계;
3) 상기 실리콘 산화막에 자기조립단분자막(Self-Assembled Monolayer, SAM)을 흡착시키는 단계;
4) 실리콘층 이외의 물질층 상에 실리콘질화막(SixNy)을 증착시키는 단계;
5) 상기 자기조립단분자막을 포함하는 실리콘 산화막을 에칭 공정에 의하여 제거하는 단계를 포함하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
1) providing a substrate in which the first material layer and the second material layer are simultaneously exposed and misaligned;
2) forming a silicon oxide film by selectively oxidizing the silicon layer using O 2 and H 2 gas when either the first material layer or the second material layer is a silicon layer;
3) adsorbing a self-assembled monolayer (SAM) on the silicon oxide film;
4) depositing a silicon nitride film (Si x N y ) on a material layer other than the silicon layer;
5) A method of recovering memory device defects by selective deposition, comprising removing the silicon oxide film including the self-assembled monolayer by an etching process.
 제1항에 있어서,
상기 2) 단계에서, 온도는 750 ~ 950℃이고, 총 기체에 대한 상기 O2 가스의 기체분압은 5 ~ 20%인 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
The method of claim 1,
In the step 2), the temperature is 750 ~ 950 ℃, the gas partial pressure of the O 2 gas with respect to the total gas is 5 ~ 20% memory device defect recovery method by selective deposition, characterized in that.
 제1항에 있어서,
상기 자기조립단분자막은 DMADMS-비스(디메틸아미노)디메틸실란(Bis(dimethylamino)dimethylsilane) 또는 DMATMS-(디메틸아미노)트리메틸실란((Dimethylamino)trimethylsilane)를 흡착시킴으로써 형성되는 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
The method of claim 1,
The self-assembled monolayer is a memory by selective deposition, characterized in that it is formed by adsorbing DMADMS-bis(dimethylamino)dimethylsilane or DMATMS-(dimethylamino)trimethylsilane. Device defect recovery method.
 제1항에 있어서,
상기 3) 단계 및 4) 단계는 원자층 증착법(Atomic Layer Deposition)에 의하여 수행되는 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
The method of claim 1,
Steps 3) and 4) are performed by atomic layer deposition.
 제1항에 있어서,
상기 자기조립단분자막으로 흡착된 실리콘 산화막은 표면의 물 접촉각은 80 ~ 90°인 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
The method of claim 1,
The silicon oxide film adsorbed by the self-assembled monolayer has a surface water contact angle of 80 to 90°.
 제1항에 있어서,
상기 3) 단계는 기판의 온도가 600℃ 이하이며, 상기 4) 단계 공정 온도와 동일한 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
The method of claim 1,
In the step 3), the temperature of the substrate is 600° C. or less, and the process temperature in the step 4) is the same as that of the step 4).
 삭제delete 제1항에 있어서,
상기 실리콘질화막(SixNy)을 형성시키기 위한 전구제는 실란(silane; SiH4), 디클로로실란(dichlorosil ane; SiCl2H2), 디실란(disilane; Si2H6) 또는 TEOS 중 어느 하나인 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
The method of claim 1,
The precursor for forming the silicon nitride film (Si x N y ) is any one of silane (SiH 4 ), dichlorosilane (SiCl 2 H 2 ), disilane (Si 2 H 6 ), or TEOS. A method for recovering memory device defects by selective deposition, characterized in that one.
 제1항에 있어서,
상기 단계 5) 이후에 셀 접촉(Cell Contact)을 형성시키는 단계를 더 포함하는 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.
The method of claim 1,
And forming a cell contact after step 5).
 제1항 내지 제6항 및 제8항 내지 제9항 중 어느 한 항에 있어서,
상기 메모리 소자는 DRAM(Dynamic random-access memory)인 것을 특징으로 하는 선택적 증착에 의한 메모리 소자 결함 회복 방법.The method according to any one of claims 1 to 6 and 8 to 9,
The memory device defect recovery method by selective deposition, characterized in that the memory device is a dynamic random-access memory (DRAM).
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