JPH0794617A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0794617A JPH0794617A JP5239342A JP23934293A JPH0794617A JP H0794617 A JPH0794617 A JP H0794617A JP 5239342 A JP5239342 A JP 5239342A JP 23934293 A JP23934293 A JP 23934293A JP H0794617 A JPH0794617 A JP H0794617A
- Authority
- JP
- Japan
- Prior art keywords
- functional circuit
- circuit chip
- esd protection
- functional
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
にESD(electrostatic discha
rge)保護回路を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an ESD (electrostatic disk) device.
rge) A semiconductor device having a protection circuit.
【0002】[0002]
【従来の技術】従来の半導体装置は図3に示すように、
機能回路1aとESD保護回路2aが同一拡散で形成し
た機能回路チップ1をパッケージ5の上にマウントされ
る。機能回路チップ1の電極はボンディングワイヤ3を
介してパッケージ5の上に形成された配線4に接続さ
れ、配線4に接続された外部リード6と電気的に接続さ
れている。2. Description of the Related Art A conventional semiconductor device is shown in FIG.
The functional circuit chip 1 in which the functional circuit 1a and the ESD protection circuit 2a are formed by the same diffusion is mounted on the package 5. The electrodes of the functional circuit chip 1 are connected to the wirings 4 formed on the package 5 via the bonding wires 3 and electrically connected to the external leads 6 connected to the wirings 4.
【0003】同一拡散で機能回路1aの特性とESD保
護回路2aを形成する場合、二つの回路の特性は相反す
る関係にあるため、これを両立させるためには機能回路
1aの特性とESD保護回路2aの特性は、ともに最適
設計からずれたところに設計しなければならないという
不都合を生ずる。また、拡散のばらつきにより、いずれ
か一方の回路の規格外れが生じると、規格を満足する
(特性が最適値に近くなる)もう一方の回路も同一チッ
プ内にあるために廃棄しなくはならいという欠点があ
る。When the characteristics of the functional circuit 1a and the ESD protection circuit 2a are formed by the same diffusion, the characteristics of the two circuits have a contradictory relationship. Therefore, in order to make them compatible, the characteristics of the functional circuit 1a and the ESD protection circuit are compatible. The characteristics of 2a both cause the inconvenience of having to be designed at a position deviated from the optimum design. Also, if one of the circuits is out of specification due to dispersion in diffusion, the other circuit that satisfies the specification (the characteristics are close to the optimum value) is also in the same chip and must be discarded. There are drawbacks.
【0004】このような欠点を改善するためには、図4
に示すように、それぞれ別個に形成した技能回路チップ
1とESD保護回路チップ2をそれぞれパッケージ5上
にマウントし、ボンディングワイヤ3とパッケージ上の
配線4を介して外部リード6に電気的に接続する構造が
考察されている。しかしながら、機能回路チップ1とE
SD保護回路チップ2をパッケージ5上にマウントする
とパッケージが大きくなるという欠点がある。また、機
能回路1aの周辺からしか信号がとり出せないので、E
SD保護が機能回路1aの周辺の回路にのみでしか適用
できないという問題点やボンディングワイヤ3を介して
機能回路1aとESD保護回路チップ2を接続するた
め、接続インピーダンスが大きくなり、ESD保護の応
答か遅くなるという欠点が生じる。In order to improve such a defect, FIG.
As shown in FIG. 3, the skill circuit chip 1 and the ESD protection circuit chip 2 formed separately are mounted on the package 5, respectively, and electrically connected to the external lead 6 via the bonding wire 3 and the wiring 4 on the package. The structure is being considered. However, the functional circuit chips 1 and E
Mounting the SD protection circuit chip 2 on the package 5 has a drawback that the package becomes large. Further, since the signal can be taken out only from the periphery of the functional circuit 1a, E
The problem that the SD protection can be applied only to the circuit around the functional circuit 1a and the connection between the functional circuit 1a and the ESD protection circuit chip 2 via the bonding wire 3 increases the connection impedance and the response of the ESD protection. The drawback is that it becomes slower.
【0005】[0005]
【発明が解決しようとする課題】この従来の半導体装置
は、同一チップ上に機能回路とESD保護回路を形成し
たものでは、両者の回路特性を共に最適にする設計がで
きないという問題があり、また、それぞれ最適な特性が
得られるように別個に形成した機能回路チップとESD
保護回路チップとをパッケージ上にそれぞれマウントし
たものでは、機能回路チップの周辺部しか、ESD保護
ができない点や、機能回路とESD保護回路の接続イン
ピーダンスが大きくなり、ESD保護の応答が遅くなっ
て十分な保護ができないという問題があった。This conventional semiconductor device has a problem in that it is not possible to design the circuit characteristics of both the functional circuit and the ESD protection circuit on the same chip so that both circuits cannot be optimized. , A functional circuit chip and an ESD that are separately formed to obtain optimum characteristics.
In the case where the protective circuit chip and the protective circuit chip are mounted on the package, the ESD protection can be performed only in the peripheral portion of the functional circuit chip, and the connection impedance between the functional circuit and the ESD protective circuit becomes large, resulting in a slow response of the ESD protection. There was a problem that it could not provide sufficient protection.
【0006】[0006]
【課題を解決するための手段】本発明の第1の半導体装
置は、パッケージ上に搭載した機能回路チップと、前記
機能回路チップ上にバンプを介して搭載し前記機能回路
チップ上に形成した機能回路と電気的に接続したESD
保護回路チップとを有する。A first semiconductor device of the present invention is a functional circuit chip mounted on a package, and a function mounted on the functional circuit chip via a bump and formed on the functional circuit chip. ESD electrically connected to the circuit
And a protection circuit chip.
【0007】本発明の第2の半導体装置は、パッケージ
上に搭載した機能回路チップと、前記機能回路チップの
上面に形成した溝又は凹部と、前記溝又は凹部内に埋込
み且つ前記機能回路チップ上に形成した機能回路と電気
的に接続したESD保護回路チップとを有する。A second semiconductor device of the present invention is a functional circuit chip mounted on a package, a groove or a recess formed on the upper surface of the functional circuit chip, and embedded in the groove or the recess and on the functional circuit chip. And an ESD protection circuit chip electrically connected to the functional circuit formed in the above.
【0008】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0009】図1は本発明の第1の実施例を示す模式的
断面図である。FIG. 1 is a schematic sectional view showing a first embodiment of the present invention.
【0010】図1に示すように、上面に配線4とこの配
線4に接続する外部リード6を有するパッケージの配線
4の上にバンプ7aを介して機能回路チップ1が搭載さ
れ機能回路チップ1に形成された機能回路1aと電気的
に接続される。機能回路チップ1上にはバンプ7bを介
してESD保護回路チップ2が搭載され機能回路1aと
電気的に接続される。As shown in FIG. 1, the functional circuit chip 1 is mounted via the bumps 7a on the wiring 4 of the package having the wiring 4 and the external leads 6 connected to the wiring 4 on the upper surface. It is electrically connected to the formed functional circuit 1a. The ESD protection circuit chip 2 is mounted on the functional circuit chip 1 via the bumps 7b and electrically connected to the functional circuit 1a.
【0011】ここで、ESD保護回路チップ2と機能回
路チップ1とは別個に形成しているので最適の設計のも
のを使うことができ、かつ、バンプ7bを介してESD
保護回路チップ2と機能回路1aが直接接続されている
ため、電気的インピーダンスを0.1〜1.0Ω程度に
小さくでき、ESD保護の応答が向上できる。さらに機
能回路チップ1の上に直接ESD保護回路チップ2を接
続できるので、機能回路1aの任意の箇所にESD保護
チップ2を接続できるという利点がある。Here, since the ESD protection circuit chip 2 and the functional circuit chip 1 are formed separately, the optimum design can be used, and the ESD is provided via the bump 7b.
Since the protection circuit chip 2 and the functional circuit 1a are directly connected, the electrical impedance can be reduced to about 0.1 to 1.0Ω, and the response of ESD protection can be improved. Further, since the ESD protection circuit chip 2 can be directly connected to the functional circuit chip 1, there is an advantage that the ESD protection chip 2 can be connected to any place of the functional circuit 1a.
【0012】図2は本発明の第2の実施例を示す模式的
断面図である。FIG. 2 is a schematic sectional view showing a second embodiment of the present invention.
【0013】図2に示すように、機能回路チップ1の上
面に形成した溝8又は凹部内に機能回路チップ1とは別
個に形成したESD保護回路チップ2を埋込んで接着剤
等で固定し、ボンディングワイヤやビームリード等によ
り機能回路チップ1上に形成した機能回路1aと電気的
に接続した以外は第1の実施例と同様の構成を有してお
り、それぞれ最適条件(特に拡散工程の条件)で形成さ
れた機能回路とESD保護回路の組合せを低インピーダ
ンスで接続できる利点がある。As shown in FIG. 2, an ESD protection circuit chip 2 formed separately from the functional circuit chip 1 is embedded in a groove 8 or a recess formed on the upper surface of the functional circuit chip 1 and fixed with an adhesive or the like. The structure is similar to that of the first embodiment except that it is electrically connected to the functional circuit 1a formed on the functional circuit chip 1 by bonding wires, beam leads, etc. There is an advantage that the combination of the functional circuit formed under the conditions) and the ESD protection circuit can be connected with low impedance.
【0014】[0014]
【発明の効果】以上説明したように本発明は、機能回路
チップとは別個の条件で形成されたESD保護回路チッ
プを機能回路チップ上に低インビーダンスで電気的に接
続できるので、機能回路の特性を低下させることなく、
ESD耐圧の大きい半導体装置を実現できるという効果
を有する。As described above, according to the present invention, since the ESD protection circuit chip formed under the condition different from that of the functional circuit chip can be electrically connected to the functional circuit chip with low impedance, Without degrading the characteristics of
This has the effect of realizing a semiconductor device having a high ESD breakdown voltage.
【図1】本発明の第1の実施例を示す模式的断面図。FIG. 1 is a schematic sectional view showing a first embodiment of the present invention.
【図2】本発明の第2の実施例を示す模式的断面図。FIG. 2 is a schematic sectional view showing a second embodiment of the present invention.
【図3】従来の半導体装置の第1の例を示す模式的断面
図。FIG. 3 is a schematic cross-sectional view showing a first example of a conventional semiconductor device.
【図4】従来の半導体装置の第2の例を示す模式的断面
図。FIG. 4 is a schematic cross-sectional view showing a second example of a conventional semiconductor device.
1 機能回路チップ 1a 機能回路 2 ESD保護回路チップ 2a ESD保護回路 3 ボンディングワイヤ 4 配線 5 パッケージ 6 外部リード 7,7a,7b バンプ 8 溝 1 Functional Circuit Chip 1a Functional Circuit 2 ESD Protection Circuit Chip 2a ESD Protection Circuit 3 Bonding Wire 4 Wiring 5 Package 6 External Lead 7, 7a, 7b Bump 8 Groove
Claims (2)
と、前記機能回路チップ上にバンプを介して搭載し前記
機能回路チップ上に形成した機能回路と電気的に接続し
たESD保護回路チップとを有することを特徴とする半
導体装置。1. A functional circuit chip mounted on a package, and an ESD protection circuit chip mounted on the functional circuit chip via bumps and electrically connected to a functional circuit formed on the functional circuit chip. A semiconductor device characterized by the above.
と、前記機能回路チップの上面に形成した溝又は凹部
と、前記溝又は凹部内に埋込み且つ前記機能回路チップ
上に形成した機能回路と電気的に接続したESD保護回
路チップとを有することを特徴とする半導体装置。2. A functional circuit chip mounted on a package, a groove or a recess formed on an upper surface of the functional circuit chip, a functional circuit embedded in the groove or the recess and formed on the functional circuit chip, and an electrical circuit. And an ESD protection circuit chip connected to the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5239342A JP2500643B2 (en) | 1993-09-27 | 1993-09-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5239342A JP2500643B2 (en) | 1993-09-27 | 1993-09-27 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0794617A true JPH0794617A (en) | 1995-04-07 |
JP2500643B2 JP2500643B2 (en) | 1996-05-29 |
Family
ID=17043316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5239342A Expired - Lifetime JP2500643B2 (en) | 1993-09-27 | 1993-09-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2500643B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6198136B1 (en) | 1996-03-19 | 2001-03-06 | International Business Machines Corporation | Support chips for buffer circuits |
US6972487B2 (en) * | 2001-03-30 | 2005-12-06 | Fujitsu Limited | Multi chip package structure having a plurality of semiconductor chips mounted in the same package |
JP2014107482A (en) * | 2012-11-29 | 2014-06-09 | Denso Corp | Electronic device |
-
1993
- 1993-09-27 JP JP5239342A patent/JP2500643B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6198136B1 (en) | 1996-03-19 | 2001-03-06 | International Business Machines Corporation | Support chips for buffer circuits |
US6972487B2 (en) * | 2001-03-30 | 2005-12-06 | Fujitsu Limited | Multi chip package structure having a plurality of semiconductor chips mounted in the same package |
JP2014107482A (en) * | 2012-11-29 | 2014-06-09 | Denso Corp | Electronic device |
Also Published As
Publication number | Publication date |
---|---|
JP2500643B2 (en) | 1996-05-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960123 |