JPH0731614B2 - データ転送方法 - Google Patents

データ転送方法

Info

Publication number
JPH0731614B2
JPH0731614B2 JP3285417A JP28541791A JPH0731614B2 JP H0731614 B2 JPH0731614 B2 JP H0731614B2 JP 3285417 A JP3285417 A JP 3285417A JP 28541791 A JP28541791 A JP 28541791A JP H0731614 B2 JPH0731614 B2 JP H0731614B2
Authority
JP
Japan
Prior art keywords
bit
data
register
bits
under test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3285417A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04263335A (ja
Inventor
ティー． ジャーワラ ナジム
ダブリュー． ヤウ チー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of JPH04263335A publication Critical patent/JPH04263335A/ja
Publication of JPH0731614B2 publication Critical patent/JPH0731614B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
JP3285417A 1990-10-09 1991-10-07 データ転送方法 Expired - Fee Related JPH0731614B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/594,516 US5155732A (en) 1990-10-09 1990-10-09 Method and apparatus for data transfer to and from devices through a boundary-scan test access port
US594516 1990-10-09

Publications (2)

Publication Number Publication Date
JPH04263335A JPH04263335A (ja) 1992-09-18
JPH0731614B2 true JPH0731614B2 (ja) 1995-04-10

Family

ID=24379213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3285417A Expired - Fee Related JPH0731614B2 (ja) 1990-10-09 1991-10-07 データ転送方法

Country Status (5)

Country Link
US (1) US5155732A (enExample)
EP (1) EP0480619B1 (enExample)
JP (1) JPH0731614B2 (enExample)
KR (1) KR920009113A (enExample)
DE (1) DE69120765T2 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254942A (en) * 1991-04-25 1993-10-19 Daniel D'Souza Single chip IC tester architecture
JP2973641B2 (ja) * 1991-10-02 1999-11-08 日本電気株式会社 Ｔａｐコントローラ
US5377198A (en) * 1991-11-27 1994-12-27 Ncr Corporation (Nka At&T Global Information Solutions Company JTAG instruction error detection
US5231314A (en) * 1992-03-02 1993-07-27 National Semiconductor Corporation Programmable timing circuit for integrated circuit device with test access port
TW253097B (enExample) * 1992-03-02 1995-08-01 At & T Corp
DE4232271C1 (de) * 1992-09-25 1994-02-17 Siemens Ag Elektronischer Baustein mit einer Schieberegisterprüfarchitektur (Boundary-Scan)
US5404526A (en) * 1992-10-20 1995-04-04 Dosch; Daniel G. Improved method for accessing machine state information
US5448576A (en) * 1992-10-29 1995-09-05 Bull Hn Information Systems Inc. Boundary scan architecture extension
US5333139A (en) * 1992-12-30 1994-07-26 Intel Corporation Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain
US5379302A (en) * 1993-04-02 1995-01-03 National Semiconductor Corporation ECL test access port with low power control
US5490151A (en) * 1993-07-26 1996-02-06 At&T Corp. Boundary scan cell
US6006343A (en) * 1993-07-30 1999-12-21 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
US5544174A (en) * 1994-03-17 1996-08-06 The United States Of America As Represented By The Secretary Of The Air Force Programmable boundary scan and input output parameter device for testing integrated circuits
US5513189A (en) * 1994-05-25 1996-04-30 Tandem Computers, Incorporated Boundary scan system with improved error reporting using sentinel bit patterns
EP0858630B1 (en) * 1995-06-09 2005-03-23 Fujitsu Limited Method, system and apparatus for efficiently generating binary numbers for testing storage devices
KR100240662B1 (ko) * 1997-09-25 2000-01-15 윤종용 제이태그에 의한 다이나믹램 테스트장치
US6032279A (en) * 1997-11-07 2000-02-29 Atmel Corporation Boundary scan system with address dependent instructions
US6308290B1 (en) 1999-05-20 2001-10-23 International Business Machines Corporation Look ahead scan chain diagnostic method
DE10032256C2 (de) * 2000-07-03 2003-06-05 Infineon Technologies Ag Chip-ID-Register-Anordnung
US7188277B2 (en) * 2003-03-28 2007-03-06 Hewlett-Packard Development Company, L.P. Integrated circuit
US7206983B2 (en) * 2005-03-31 2007-04-17 Lsi Logic Corporation Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits
US8829940B2 (en) * 2008-09-26 2014-09-09 Nxp, B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
TWI640996B (zh) * 2017-12-21 2018-11-11 新唐科技股份有限公司 記憶體電路及其測試方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864844A (ja) * 1981-10-15 1983-04-18 Victor Co Of Japan Ltd 同期検出方式
US4534028A (en) * 1983-12-01 1985-08-06 Siemens Corporate Research & Support, Inc. Random testing using scan path technique
US4872169A (en) * 1987-03-06 1989-10-03 Texas Instruments Incorporated Hierarchical scan selection
US4827476A (en) * 1987-04-16 1989-05-02 Tandem Computers Incorporated Scan test apparatus for digital systems having dynamic random access memory
US4947357A (en) * 1988-02-24 1990-08-07 Stellar Computer, Inc. Scan testing a digital system using scan chains in integrated circuits
US5079725A (en) * 1989-11-17 1992-01-07 Ibm Corporation Chip identification method for use with scan design systems and scan testing techniques

Also Published As

Publication number Publication date
JPH04263335A (ja) 1992-09-18
EP0480619B1 (en) 1996-07-10
US5155732A (en) 1992-10-13
KR920009113A (ko) 1992-05-28
EP0480619A2 (en) 1992-04-15
EP0480619A3 (enExample) 1994-02-23
DE69120765T2 (de) 1996-11-28
DE69120765D1 (de) 1996-08-14

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