JPH07245392A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve reliability of a gate insulation film and to improve performance of an MOS transistor, an MOS capacitor, etc., by providing a mask to an element region, by eliminating an atomic step in an element region by etching a substrate surface and by forming an insulation film in the formed same atomic plane. CONSTITUTION:A buffer thermal oxide film 2 is formed on a silicon substrate 1 and a resist pattern 3 including an active region of an MIS element is formed thereon. A buffer thermal oxide film 2 and a silicon substrate 1 are etched by using the resist pattern 3 as a mask and a groove 4 is formed, and a resist and the buffer thermal oxide film 2 are peeled. A wafer is heated in a UHV chamber, termination treatment is performed for hydrogen to eliminate it from the wafer surface. Them, after a substrate surface is made the same atomic plane by using Si and Sn and an isolation region 10 is formed, a thermal oxide film is formed as a gate insulation film 11, and a gate electrode 12 and a diffusion layer 13 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, particularly a MOS.
The present invention relates to high reliability of a gate insulating film in a capacitor.

[0002]

2. Description of the Related Art The miniaturization of M0S elements is being advanced with the high integration of LSIs. With the miniaturization of this element, M
The gate oxide film of OS is becoming thinner, and even now
A gate insulating film of 0 nm or less is about to be used,
In the future, a thinner gate insulating film will be required. As the gate insulating film becomes thinner, precise control of the thickness of the gate insulating film and higher reliability have become important issues.

The silicon substrate currently used is a slice obtained by deciding the crystal plane orientation from an ingot. However, when looking at the flatness of the silicon surface and the crystal perfection at the atomic level, it is not flat at all and the crystal plane surrounding There are many point defects associated with steps, surface treatments, etc. due to slight deviations. For example, in the case of a silicon (100) substrate, 15.6 nm if the plane orientation of the substrate deviates by 0.5 degrees.
There will be atomic steps for each.

Regarding the reliability of the gate insulating film, the atomic level flatness of the surface of the silicon substrate impairs the reliability of the gate insulating film for the following reason. One is that when a gate insulating film is formed by oxidizing a silicon substrate, if there is unevenness on the surface of the silicon substrate before oxidation, the surface of the silicon substrate before oxidation is also oxidized and the interface between the silicon oxide film and the silicon substrate is formed. Unevenness exists at the atomic level and the film thickness of the gate insulating film becomes non-uniform. Furthermore, unevenness on the surface of the silicon substrate causes electric field concentration and lowers the breakdown voltage of the gate insulating film. Furthermore, since the steps and kinks on the surface of the silicon substrate are much more active than other portions, it is easy to adsorb metal irregularities and the like. A gate insulating film obtained by oxidizing the surface of a silicon substrate on which such a metal disordered substance is adsorbed significantly reduces reliability.

On the other hand, flatness at the atomic level has become very important in terms of the performance of MOS transistors. The performance of MOS transistors can be significantly improved by improving the mobility of carriers. If there is unevenness at the atomic level at the interface between silicon and the oxide film, the mobility will decrease due to the effect of interface roughness scattering. That is,
If a flat interface can be obtained at the atomic level, the mobility can be significantly improved.

Further, with the miniaturization of elements, it has become necessary to form a very shallow diffusion layer, and for this reason, a flat surface at the atomic level is required. For these reasons, there is a need for an atomically flat silicon substrate.
At present, a technique for flattening the surface of a silicon substrate at the atomic level is being developed. One of the methods is S. Iwanari et al.
(Extended Abstracts of the 1991 InternationalConfe
rence on Solid State Devices and Materials, p.278
(1991)). As for the silicon (111) surface, a clean surface having a 7 × 7 structure is formed in an ultrahigh vacuum, and Sn is deposited on the surface by vapor deposition of Sn, so that Sn becomes a surfactant and silicon epitaxially grows laterally from the step edge. This technique is used to planarize the surface of the silicon substrate at the atomic level. However, a silicon substrate which is flat at the atomic level over the entire surface of the wafer has a large film thickness difference when the plane orientation of the substrate is 0.5 degrees, and as a result, such a substrate cannot be produced.

[0007]

With the conventional techniques, it was impossible to form a surface having no unevenness at the atomic level over the entire surface of the wafer. The present invention has been made in view of the above circumstances, and limits the region where elements are formed on the surface of a semiconductor wafer, forms a flat surface at the atomic level in at least that region, and forms a gate there. Improves reliability of insulating film and improves MOS transistor and MO
The purpose is to improve the performance of the S capacitor and the like.

[0008]

To achieve the above object, the present invention eliminates the step of providing a mask on the element region of the surface of a semiconductor substrate and etching the substrate surface, and the atomic step on the surface of the element region. Then, there are provided a step of forming the same atomic plane and a method of manufacturing a semiconductor device in which an insulating film is formed on the same atomic plane. Preferably, the device region includes at least a region where a gate insulating film is formed.

[0009]

In the MOS transistor and the MOS capacitor according to the present invention, the element region is limited, and the surface of this region is made to have the same atomic plane. Therefore, the region where the gate insulating film is formed or the element region where the diffusion layer is formed is an atomic surface. After leveling, the gate insulating film and the diffusion layer are formed in these regions. Therefore, since there are no steps or kinks on the substrate surface before oxidation in the gate insulating film, there is no adsorption of metal impurities, and an oxide film with a uniform thickness can be formed on the substrate surface. The reliability is significantly improved. Further, in the diffusion layer, the diffusion layer having a uniform depth is formed as the surface flatness is improved, and the device characteristics are improved.

[0010]

Embodiments of the method of manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. Example 1 FIG. 1 is a process sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention.

The silicon substrate 1 has a plane orientation of (1
11) Use the surface. If necessary, impurities are diffused in the silicon substrate 1 to a desired region, then a buffer thermal oxide film 2 is formed to 100 nm on the silicon substrate 1, and MI is formed thereon.
A resist pattern 3 including the active region of the S element is formed (FIG. 1A). At this time, the margin between the element region and the resist is set in consideration of the lithography margin when forming the active region in this region in a later step.

Subsequently, the buffer thermal oxide film 2 and the silicon substrate 1 are RIE-etched using the resist pattern 3 as a mask to form a groove 4 having a depth of 10 nm, the resist is peeled off, and the buffer thermal oxidation is performed with a dilute HF aqueous solution. The film 2 is peeled off (FIG. 1 (b)). The depth of the groove 4 formed at this time is preferably 1 nm or more for achieving the same atomic plane.

FIG. 2 is an enlarged view of a cross section and a surface of the convex portion 5 including the active region of the silicon substrate 1 used in the method for manufacturing a semiconductor device of the present invention shown in FIG. At the atomic level, there are steps 6 and depressions 7 in the terrace. The native oxide film formed on the surface is removed with a dilute HF aqueous solution (for example, 1%), and subsequently, the silicon surface is subjected to hydrogen termination treatment by washing with ultrapure water (for example, the dissolved oxygen concentration is 5 ppb or less). It was Then, the wafer is introduced into the UHV chamber (for example, the degree of vacuum is 10 ⁻⁹ Torr or less). The wafer is heat-treated in the UHV chamber to release the hydrogen whose surface is terminated,
A clean silicon surface (7 × 7 structure) having a structural phase transition is used.

Next, the surface of the silicon substrate is made to have the same atomic plane by using Si and Sn. FIG. 3 shows the surface of the silicon substrate used in the method of manufacturing a semiconductor device according to the present invention.
FIG. 6 is a cross-sectional view showing the replacement of Si and Sn in the portion of FIG. For example, one atomic layer of Sn8 is deposited on the substrate 5 of FIG. 2 at 500 ° C., and then Si9 is vapor-deposited at 500 ° C. (FIG. 3A). At this time, Sn functions as a surfactant, Sn and Si are replaced at the step edge, and the step grows only in the lateral direction as shown in FIG. 3B. 1 at the end of the convex portion 5 including the element region
There is a 0 nm step, and the step flow ends there. As a result, all steps on the element region are swept out of the element region, and the element region is flattened at the atomic level (FIG. 3C). .

Then, by exposing to an oxygen atmosphere, Sn on the silicon surface is oxidized and SnO _{2 is} applied to the silicon substrate surface.
Is formed. For example, by treating this in sulfuric acid, SnO _{2 on the} surface of the silicon substrate is removed, and a silicon substrate that is flat at the atomic level is formed in the element region. After performing such a treatment, alignment is performed so that the region of the convex portion 5 including the element region becomes the active region, the element isolation region 10 is formed, and then a thermal oxide film is formed as the gate insulating film 11. For example, by forming the gate electrode 12 and the diffusion layer 13 to have a thickness of 8 nm, a highly reliable MOS transistor and MOS capacitor can be obtained (FIG. 1C).

Embodiment 2 FIG. 4 is a process sectional view showing another embodiment of the method for manufacturing a semiconductor device of the present invention.

Of the steps shown in Example 1, FIG.
After going through the same steps until the surface of the silicon substrate 1 is flattened and the surfactant Sn is removed, a thermal oxide film is formed as the gate insulating film 21 by thermal oxidation, for example, to a thickness of 8 nm, and then a polycrystalline silicon film 22 is formed. For example, 10
0 nm was deposited, and then impurities were diffused into the polycrystalline silicon film 22 (FIG. 4A).

Next, a resist pattern 23 for forming an element isolation region is formed. At this time, the resist pattern 23 is formed so as not to protrude from the convex portion 5 including the element region. Using the resist pattern 23 as a mask, the polycrystalline silicon 22 and the thermal oxide film 21 are etched by the RIE method, and the silicon substrate 1 is further etched by 300 nm, for example (FIG. 4B).

After removing the resist pattern 23, a silicon oxide film is deposited to a thickness of 500 nm by, for example, the CVD method, and the surface is flattened by the etch back method to form an element isolation pattern 24 (FIG. 4C).

After removing the natural oxide film on the surface of the polycrystalline silicon 22, a polycrystalline silicon electrode 25 is deposited to a thickness of 300 nm by the CVD method to diffuse the impurities. The gate electrode is patterned and formed by a normal MOS transistor manufacturing method (FIG. 4D).

In this way, since the gate region of the transistor is formed on the flat silicon substrate at the atomic level, a highly reliable MOS transistor can be obtained. In the first and second embodiments, Sn was used as a surfactant when epitaxially growing silicon, and was taken out of the chamber after the epitaxial growth.
Although the acid solution is used for dissolution and removal, it may be removed by, for example, HCl gas in the same chamber, and then the gate insulating film is formed.

Further, as a pretreatment for Sn deposition as a surfactant, a treatment with a dilute HF solution and a hydrogen termination treatment in ultrapure water are carried out.
It is also possible to remove the natural oxide film on the surface by heating to a high temperature in the HV chamber and to perform a treatment of exposing the clean silicon surface to the active region.

Further, the gate insulating film is formed by a method of thermally oxidizing the silicon substrate, but a deposited insulating film by a deposition method may be used. Furthermore, Sn was used as a surfactant for epitaxially growing silicon in the lateral direction of the step, but the surfactant is not limited to Sn as long as it acts similarly.

[0024]

As described above, according to the present invention, since at least a region where a gate insulating film is formed on a semiconductor substrate has a flat surface at an atomic level, the gate insulating film formed there is formed. The reliability can be increased. Further, even in the region where the shallow diffusion layer is formed, at least the region where the diffusion layer is formed is flattened at the atomic level, so that the depth of the diffusion layer can be easily controlled and the device characteristics are improved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is an enlarged view of a cross section and a surface of a convex portion including an active region of a silicon substrate used in the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing the exchange of Si and Sn on the surface of the silicon substrate used in the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a process sectional view showing another embodiment of the method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Buffer thermal oxide film 3 ... Resist pattern 4 ... The groove | channel formed in the silicon substrate 5 ... The recessed part which contains an active region 6 ... Atomic step 7 ... Defects in terrace 8 ... Sn 9 ... Si 10 ... Element isolation region 11 ... Gate insulating film 12 ... Gate electrode 13 ... Diffusion layer 21 ... Gate insulating film 22 ... Gate electrode 23 ... Resist pattern in active area 24 ·· Element isolation insulating film 25 · · Polycrystalline silicon electrode 26 · · Diffusion layer

Claims (6)

[Claims] 1. A step of forming a mask on an element region of a semiconductor substrate surface to etch the substrate surface, a step of eliminating atomic steps on the surface of the element region to form the same atomic plane, and the same atomic plane A method for manufacturing a semiconductor device, which comprises forming an insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the element region includes at least a region where the insulating film is formed. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate. 4. The semiconductor according to claim 3, wherein in the step of forming the same atomic plane, silicon is epitaxially grown on the convex portion of the substrate to eliminate atomic steps on the surface of the convex portion of the substrate. Device manufacturing method. 5. The step of forming the same atomic plane comprises depositing a surfactant on a surface of a convex portion of the substrate, then epitaxially growing silicon through the surfactant, and performing an atomic step on a surface of the convex portion of the substrate. The method for manufacturing a semiconductor device according to claim 3, wherein the method is excluded. 6. The method of manufacturing a semiconductor device according to claim 5, wherein Sn is deposited as one atomic layer as the surfactant.