JPH0723961Y2 - 半導体素子収納用パッケージ - Google Patents

半導体素子収納用パッケージ

Info

Publication number
JPH0723961Y2
JPH0723961Y2 JP1988134797U JP13479788U JPH0723961Y2 JP H0723961 Y2 JPH0723961 Y2 JP H0723961Y2 JP 1988134797 U JP1988134797 U JP 1988134797U JP 13479788 U JP13479788 U JP 13479788U JP H0723961 Y2 JPH0723961 Y2 JP H0723961Y2
Authority
JP
Japan
Prior art keywords
external lead
semiconductor element
lead terminal
glass
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1988134797U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0256446U (OSRAM
Inventor
公明 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1988134797U priority Critical patent/JPH0723961Y2/ja
Publication of JPH0256446U publication Critical patent/JPH0256446U/ja
Application granted granted Critical
Publication of JPH0723961Y2 publication Critical patent/JPH0723961Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)
JP1988134797U 1988-10-14 1988-10-14 半導体素子収納用パッケージ Expired - Fee Related JPH0723961Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988134797U JPH0723961Y2 (ja) 1988-10-14 1988-10-14 半導体素子収納用パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988134797U JPH0723961Y2 (ja) 1988-10-14 1988-10-14 半導体素子収納用パッケージ

Publications (2)

Publication Number Publication Date
JPH0256446U JPH0256446U (OSRAM) 1990-04-24
JPH0723961Y2 true JPH0723961Y2 (ja) 1995-05-31

Family

ID=31393870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988134797U Expired - Fee Related JPH0723961Y2 (ja) 1988-10-14 1988-10-14 半導体素子収納用パッケージ

Country Status (1)

Country Link
JP (1) JPH0723961Y2 (OSRAM)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001024252A1 (en) * 1999-09-28 2001-04-05 Matsushita Electric Industrial Co., Ltd. Electronic device and method of manufacture thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0713232Y2 (ja) * 1988-07-30 1995-03-29 日本電気株式会社 サーディップ型半導体装置

Also Published As

Publication number Publication date
JPH0256446U (OSRAM) 1990-04-24

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees