JPH07169601A - Square-shaped chip resistor and its manufacture - Google Patents

Square-shaped chip resistor and its manufacture

Info

Publication number
JPH07169601A
JPH07169601A JP5316335A JP31633593A JPH07169601A JP H07169601 A JPH07169601 A JP H07169601A JP 5316335 A JP5316335 A JP 5316335A JP 31633593 A JP31633593 A JP 31633593A JP H07169601 A JPH07169601 A JP H07169601A
Authority
JP
Japan
Prior art keywords
layer
electrode
electrode layer
forming
chip resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5316335A
Other languages
Japanese (ja)
Inventor
Masato Hashimoto
Yoshiharu Kimura
美晴 木村
正人 橋本
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, 松下電器産業株式会社 filed Critical Matsushita Electric Ind Co Ltd
Priority to JP5316335A priority Critical patent/JPH07169601A/en
Publication of JPH07169601A publication Critical patent/JPH07169601A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a chip resistor excellent in sulfur resistance and low in cost, in a square-shaped chip resistor which is mounted in a lump with other chip resistors. CONSTITUTION:A pair of second top electrode layers 5 being so made as to lie upon one part of the first top electrode layer 2 is so made as to overlap one part of the top of a protective layer 6, so the first top electrode layer 2 is never corroded by sulfide gas, and it is hard to cause wire breaking.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高密度配線回路に用いら
れる、角形チップ抵抗器およびその製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectangular chip resistor used in a high density wiring circuit and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来の厚膜タイプの角形チップ抵抗器の
構造の一例を、図3に示す。図3(a)は斜視図、図3
(b)は(a)のA−A’間の断面図である。
2. Description of the Related Art An example of the structure of a conventional thick film type rectangular chip resistor is shown in FIG. 3 (a) is a perspective view, FIG.
(B) is a sectional view taken along the line AA 'in (a).

【0003】従来の角形チップ抵抗器は96%アルミナ
基板10上に形成された一対の銀系厚膜による一対の上
面電極層11と前記上面電極層11と接続するように形
成されたルテニウム系厚膜による抵抗層12と、抵抗層
を完全に覆うガラス層14、上面電極層11の一部と重
なる側面電極層13とからなっている。なお、上面電極
層11および側面電極層13の露出面にははんだ付け性
を確保するためにNiメッキ層15とはんだメッキ層1
6を形成している。
A conventional rectangular chip resistor is a pair of upper electrode layers 11 made of a pair of silver-based thick films formed on a 96% alumina substrate 10 and a ruthenium-based thick film formed so as to be connected to the upper electrode layers 11. The resistance layer 12 is formed of a film, a glass layer 14 that completely covers the resistance layer, and a side surface electrode layer 13 that partially overlaps the top surface electrode layer 11. The Ni plating layer 15 and the solder plating layer 1 are formed on the exposed surfaces of the upper surface electrode layer 11 and the side surface electrode layer 13 in order to secure solderability.
6 is formed.

【0004】[0004]

【発明が解決しようとする課題】しかし、この角形チッ
プ抵抗器のガラス層14とはんだメッキ層16およびN
iメッキ層15の境目17では、チップ抵抗器をプリン
ト基板にはんだ付け実装するときに、はんだ付け時の熱
衝撃により隙間が生じ易い。さらに、このチップ抵抗器
を実装した電気製品を温泉地等の硫化ガスを含む雰囲気
で使用したとき、硫化ガスがこの隙間17に入り込み、
上面電極層11と反応し硫化銀を形成する。この硫化銀
は絶縁物であるため、反応が進むとチップ抵抗器が上面
電極11にて断線し、絶縁不良が生じるという課題を有
していた。
However, the glass layer 14, the solder plating layer 16 and the N layer of this rectangular chip resistor are used.
At the boundary 17 of the i-plated layer 15, when the chip resistor is mounted on the printed circuit board by soldering, a gap is likely to be formed due to thermal shock during soldering. Furthermore, when an electric product mounted with this chip resistor is used in an atmosphere containing a sulfurizing gas such as in a hot spring, the sulfurizing gas enters the gap 17,
Reacts with the upper electrode layer 11 to form silver sulfide. Since this silver sulfide is an insulator, there is a problem that when the reaction proceeds, the chip resistor is disconnected at the upper surface electrode 11 to cause insulation failure.

【0005】この課題を解決するためには、単純に上面
電極層を金電極等に置き換えればよいが、金電極の使用
コストは非常に高く実用化には程遠い。
In order to solve this problem, the upper electrode layer may simply be replaced with a gold electrode or the like, but the cost of using the gold electrode is very high and is far from practical use.

【0006】本発明は、このような課題を解決するもの
で、硫化ガス雰囲気中でも断線を起こしにくいチップ抵
抗器を安価で提供することを目的とする。
The present invention solves such a problem, and an object of the present invention is to provide a chip resistor which is less likely to be broken even in a sulfide gas atmosphere at a low cost.

【0007】[0007]

【課題を解決するための手段】この課題を解決するため
に本発明は、絶縁基板とこの絶縁基板上に形成された一
対の銀系の第1上面電極層と、この第1上面電極層の一
部に重なる抵抗層と、前記第1上面電極層に接続し前記
絶縁基板端部に形成された一対の端面電極層と、前記抵
抗層上に抵抗層を完全に覆う保護層と、前記第1上面電
極層上に第1上面電極層の一部に重なるように形成され
た一対の第2上面電極層とを具備し、この第2上面電極
層は保護層の上面の一部に重なっているものである。
In order to solve this problem, the present invention provides an insulating substrate, a pair of silver-based first upper surface electrode layers formed on the insulating substrate, and a first upper surface electrode layer. A resistance layer partially overlapping with the first upper surface electrode layer, a pair of end surface electrode layers connected to the first upper surface electrode layer and formed at an end portion of the insulating substrate; a protective layer completely covering the resistance layer on the resistance layer; A pair of second upper surface electrode layers formed on the first upper surface electrode layer so as to overlap a part of the first upper surface electrode layer, and the second upper surface electrode layer overlaps a part of the upper surface of the protective layer. There is something.

【0008】[0008]

【作用】これにより、第2上面電極層を保護膜に重なる
ように形成しているので、はんだ付け時の熱衝撃で隙間
が生じても第1上面電極層へは硫化ガスが達しにくいた
め硫化ガスに対して大幅に信頼性を向上した角形チップ
抵抗器を金電極等の高価な電極を使用することなく安価
に提供できる。
As a result, since the second upper surface electrode layer is formed so as to overlap the protective film, even if a gap occurs due to thermal shock during soldering, the sulfurization gas does not easily reach the first upper surface electrode layer, and therefore, the sulfurization is not performed. It is possible to provide a rectangular chip resistor with greatly improved reliability against gas at low cost without using expensive electrodes such as gold electrodes.

【0009】[0009]

【実施例】以下、本発明の一実施例について、図面を用
いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0010】(実施例1)図1(a),(b)は本発明
の角形チップ抵抗器を示す斜視図および断面図である。
(Embodiment 1) FIGS. 1A and 1B are a perspective view and a sectional view showing a rectangular chip resistor according to the present invention.

【0011】図1(a),(b)において、1は96%
アルミナ基板である。2は第1上面電極層である。4は
抵抗層である。5は第2上面電極層である。6は保護層
としてのオーバーコートガラス層である。
In FIGS. 1A and 1B, 1 is 96%.
It is an alumina substrate. 2 is a first upper surface electrode layer. Reference numeral 4 is a resistance layer. Reference numeral 5 is a second upper surface electrode layer. 6 is an overcoat glass layer as a protective layer.

【0012】このような構成の本発明の角形チップ抵抗
器は、96%アルミナ基板1上の銀系厚膜の一対の第1
上面電極層2と、第1上面電極層2の一部に重なるルテ
ニウム系厚膜の抵抗層4と、抵抗層4を完全に覆うガラ
ス層6と、第1上面電極層2上に形成された第2上面電
極層5、第1上面電極層2および第2上面電極層5の一
部に重なる銀系厚膜の端面電極層3より構成される。な
お、露出電極面にははんだ付け性を向上させるために、
Niメッキ層7とSn−Pbメッキ層8を形成してい
る。
The prismatic chip resistor of the present invention having such a structure has a pair of first silver-based thick films on a 96% alumina substrate 1.
The upper surface electrode layer 2, the resistance layer 4 of a ruthenium-based thick film that overlaps a portion of the first upper surface electrode layer 2, the glass layer 6 that completely covers the resistance layer 4, and the first upper surface electrode layer 2 are formed. The second upper surface electrode layer 5, the first upper surface electrode layer 2, and the end surface electrode layer 3 of a silver-based thick film that overlaps a part of the second upper surface electrode layer 5. In order to improve solderability on the exposed electrode surface,
The Ni plating layer 7 and the Sn-Pb plating layer 8 are formed.

【0013】次に、図1に示した本発明の角形チップ抵
抗器の製造方法について説明する。まず、耐熱性および
絶縁性に優れた96%アルミナ絶縁板を受け入れる。こ
の96%アルミナ絶縁板には短冊状、さらに個片状に分
割するために、分割するための溝(グリーンシート時に
金型成形)が形成されている。次に、96%アルミナ絶
縁板の表面に厚膜銀ペーストをスクリーン印刷・乾燥
し、ベルト式連続焼成炉によって850℃の温度で、ピ
ーク時間6分、IN−OUT45分のプロファイルによ
って焼成し、第1上面電極層2を形成した。
Next, a method of manufacturing the rectangular chip resistor of the present invention shown in FIG. 1 will be described. First, a 96% alumina insulating plate having excellent heat resistance and insulation is accepted. This 96% alumina insulating plate is formed with a strip-shaped groove and a groove for splitting (molding with a green sheet) in order to divide it into individual pieces. Next, a thick film silver paste was screen-printed and dried on the surface of a 96% alumina insulating plate, and baked by a belt type continuous baking furnace at a temperature of 850 ° C. for a peak time of 6 minutes and an IN-OUT 45 minute profile, 1 The upper surface electrode layer 2 was formed.

【0014】次に、第1上面電極層2の一部に重なるよ
うに、RuO2を主成分とする厚膜抵抗ペーストをスク
リーン印刷し、ベルト式連続焼成炉により850℃の温
度でピーク時間6分、IN−OUT45分のプロファイ
ルによって焼成し、抵抗層4を形成した。
Next, a thick film resistance paste containing RuO 2 as a main component is screen-printed so as to overlap a part of the first upper surface electrode layer 2, and a peak time 6 at a temperature of 850 ° C. in a belt type continuous firing furnace. And a resistance layer 4 was formed by firing according to a profile of 45 minutes and IN-OUT 45 minutes.

【0015】次に、第1上面電極層2間の抵抗層4の抵
抗値を揃えるために、レーザー光によって、抵抗層4の
一部を破壊し抵抗値修正(Lカット,100mm/秒,1
2KHz,5W)を行った。続いて、抵抗層4を完全に覆
うように、ホウケイ酸鉛系ガラスペーストをスクリーン
印刷し、ベルト式連続焼成炉によって590℃の温度
で、ピーク時間6分、IN−OUT50分の焼成プロフ
ァイルによって焼成し、オーバーコートガラス層6を形
成した。
Next, in order to make the resistance value of the resistance layer 4 between the first upper surface electrode layers 2 uniform, a part of the resistance layer 4 is destroyed by laser light to correct the resistance value (L cut, 100 mm / sec, 1
2 KHz, 5 W) was performed. Subsequently, a lead borosilicate glass paste was screen-printed so as to completely cover the resistance layer 4, and fired in a belt type continuous firing furnace at a temperature of 590 ° C. for a peak time of 6 minutes and an IN-OUT 50 minute firing profile. Then, the overcoat glass layer 6 was formed.

【0016】次に、第1上面電極層2の一部に重なるよ
うに厚膜銀ペーストをスクリーン印刷・乾燥し、ベルト
式連続焼成炉によって600℃の温度で、ピーク時間6
分、IN−OUT45分のプロファイルによって焼成
し、一対の第2上面電極層5を形成した。このとき図1
(a)に示す抵抗層との重なり部分の長手方向の長さX
が0.2mm以上ないと、はんだ付け時の熱衝撃で隙間が
あきやすくなった。次に、端面電極を形成するための準
備工程として、端面電極を露出させるために、96%ア
ルミナ絶縁板を短冊状に分割し、短冊状の96%アルミ
ナ絶縁板を得た。この短冊状の96%アルミナ絶縁板の
側面に、第1上面電極層2および第2上面電極層5の一
部に重なるように厚膜銀ペーストをローラーによって塗
布し、ベルト式連続焼成炉によって600℃の温度で、
ピーク時間6分、IN−OUT45分の焼成プロファイ
ルによって焼成し、端面電極層3を形成した。
Next, a thick film silver paste is screen-printed and dried so as to overlap a part of the first upper surface electrode layer 2, and the peak time is 6 at a temperature of 600 ° C. in a belt type continuous firing furnace.
And a pair of second upper surface electrode layers 5 were formed by baking according to a profile of 45 minutes for IN-OUT. At this time
Length X in the longitudinal direction of the overlapping portion with the resistance layer shown in (a)
If the thickness is 0.2 mm or more, a gap is likely to be formed due to thermal shock during soldering. Next, as a preparatory step for forming the end face electrodes, the 96% alumina insulating plate was divided into strips to expose the end face electrodes, and strip-shaped 96% alumina insulating plates were obtained. A thick film silver paste was applied to the side surface of the strip-shaped 96% alumina insulating plate by a roller so as to overlap a part of the first upper surface electrode layer 2 and the second upper surface electrode layer 5, and the belt type continuous firing furnace was used to apply 600 At a temperature of ℃,
The end face electrode layer 3 was formed by firing with a firing profile of IN-OUT 45 minutes with a peak time of 6 minutes.

【0017】次に、電極メッキの準備工程として、端面
電極層3形成済みの、短冊状の96%アルミナ絶縁板を
個片状に分割する二次基板分割を行い、個片状の96%
アルミナ基板1を得た。そして最後に、第1上面電極層
2と第2上面電極層5と端面電極層3の露出部分のはん
だ付け時の電極喰われの防止およびはんだ付けの信頼性
の確保のため、電解メッキによってNiメッキ層7を、
続いてSn−Pbのメッキ層8を形成した。
Next, as a preparatory step for electrode plating, a secondary substrate is divided into individual pieces of the strip-shaped 96% alumina insulating plate on which the end face electrode layer 3 has been formed.
Alumina substrate 1 was obtained. Finally, in order to prevent electrode erosion during soldering of exposed portions of the first upper surface electrode layer 2, the second upper surface electrode layer 5, and the end surface electrode layer 3 and to secure reliability of soldering, Ni plating is performed by electrolytic plating. Plating layer 7,
Subsequently, a Sn-Pb plated layer 8 was formed.

【0018】(実施例2)次に、本発明の第2の実施例
について説明する。
(Second Embodiment) Next, a second embodiment of the present invention will be described.

【0019】図2において、本発明の角形チップ抵抗器
は、96%アルミナ基板1上の銀系厚膜の一対の第1上
面電極層2と、第1上面電極層2の一部に重なるルテニ
ウム系厚膜の抵抗層4と、抵抗層4を完全に覆う保護層
としてのオーバーコートガラス層6と、第1上面電極層
2上に形成されたニッケルクロム薄膜による第2上面電
極層9、第1上面電極層2および第2上面電極層9の一
部に重なる銀系厚膜の端面電極層3より構成される。な
お、端面電極3および第2上面電極層9の露出面にはは
んだ付け性を向上させるために、Niメッキ層7とSn
−Pbメッキ層8を形成している。
In FIG. 2, a rectangular chip resistor according to the present invention comprises a pair of first upper surface electrode layers 2 of a silver-based thick film on a 96% alumina substrate 1 and ruthenium overlapping a part of the first upper surface electrode layer 2. A thick system resistance layer 4, an overcoat glass layer 6 as a protective layer that completely covers the resistance layer 4, a second upper surface electrode layer 9 formed of a nickel chromium thin film formed on the first upper surface electrode layer 2, 1 is composed of an upper surface electrode layer 2 and an end surface electrode layer 3 of a silver-based thick film that partially overlaps the second upper surface electrode layer 9. In order to improve solderability, the exposed surface of the end surface electrode 3 and the second upper surface electrode layer 9 should have a Ni plating layer 7 and Sn.
-Pb plating layer 8 is formed.

【0020】次に、図2に示した本発明の角形チップ抵
抗器の製造方法について説明する。まず、耐熱性および
絶縁性に優れた96%アルミナ絶縁板を受け入れる。こ
の96%アルミナ絶縁板には短冊状、さらに個片状に分
割するために、分割するための溝(グリーンシート時に
金型成形による)が形成されている。次に、96%アル
ミナ絶縁板の表面に厚膜銀ペーストをスクリーン印刷・
乾燥し、ベルト式連続焼成炉によって850℃の温度
で、ピーク時間6分、IN−OUT45分のプロファイ
ルによって焼成し、第1上面電極層2を形成した。
Next, a method of manufacturing the rectangular chip resistor of the present invention shown in FIG. 2 will be described. First, a 96% alumina insulating plate having excellent heat resistance and insulation is accepted. This 96% alumina insulating plate is formed with a strip shape and a groove for division (by die molding at the time of green sheet) for dividing into a strip shape. Next, screen print a thick film silver paste on the surface of the 96% alumina insulating plate.
It was dried and fired in a belt type continuous firing furnace at a temperature of 850 ° C. at a peak time of 6 minutes and a profile of IN-OUT 45 minutes to form a first upper electrode layer 2.

【0021】次に、第1上面電極層2の一部に重なるよ
うに、RuO2を主成分とする厚膜抵抗ペーストをスク
リーン印刷し、ベルト式連続焼成炉により850℃の温
度でピーク時間6分、IN−OUT45分のプロファイ
ルによって焼成し、抵抗層4を形成した。
Next, a thick film resistance paste containing RuO 2 as a main component was screen-printed so as to overlap a part of the first upper surface electrode layer 2, and a peak time 6 at a temperature of 850 ° C. in a belt type continuous firing furnace. And a resistance layer 4 was formed by firing according to a profile of 45 minutes and IN-OUT 45 minutes.

【0022】次に、第1上面電極層2間の抵抗層4の抵
抗値を揃えるために、レーザー光によって、抵抗層4の
一部を破壊し抵抗値修正(Lカット,100mm/秒,1
2KHz,5W)を行った。続いて、抵抗層4を完全に覆
うように、ホウケイ酸鉛系ガラスペーストをスクリーン
印刷し、ベルト式連続焼成炉によって590℃の温度
で、ピーク時間6分、IN−OUT50分の焼成プロフ
ァイルによって焼成し、オーバーコートガラス層6を形
成した。
Next, in order to make the resistance value of the resistance layer 4 between the first upper surface electrode layers 2 uniform, a part of the resistance layer 4 is destroyed by laser light to modify the resistance value (L cut, 100 mm / sec, 1
2 KHz, 5 W) was performed. Subsequently, a lead borosilicate glass paste was screen-printed so as to completely cover the resistance layer 4, and baked in a belt-type continuous baking furnace at a temperature of 590 ° C. for a peak time of 6 minutes and an IN-OUT 50 minute baking profile. Then, the overcoat glass layer 6 was formed.

【0023】次に、第1上面電極層2の一部に重なるよ
うにニッケルクロムを薄膜スパッタ工程を用いて形成
し、ニッケルクロム薄膜による第2上面電極層9を形成
した。このとき、図2(a)に示す抵抗層との重なり部
分の長手方向の長さYが0.2mm以上ないと、はんだ付
け時の熱衝撃で隙間があきやすくなった。
Next, nickel chrome was formed by a thin film sputtering process so as to overlap a part of the first upper surface electrode layer 2 to form a second upper surface electrode layer 9 of a nickel chrome thin film. At this time, if the length Y in the longitudinal direction of the overlapping portion with the resistance layer shown in FIG. 2 (a) is 0.2 mm or more, a gap is likely to be formed due to thermal shock during soldering.

【0024】次に、端面電極を形成するための準備工程
として、端面電極を露出させるために、96%アルミナ
絶縁板を短冊状に分割し、短冊状の96%アルミナ絶縁
板を得た。この短冊状の96%アルミナ絶縁板の側面
に、第1上面電極層2および第2上面電極層5の一部に
重なるように厚膜銀ペーストをローラーによって塗布
し、ベルト式連続焼成炉によって600℃の温度で、ピ
ーク時間6分、IN−OUT45分の焼成プロファイル
によって焼成し、端面電極層3を形成した。
Next, as a preparation step for forming the end face electrodes, the 96% alumina insulating plate was divided into strips to expose the end face electrodes, and strip-shaped 96% alumina insulating plates were obtained. A thick film silver paste was applied to the side surface of the strip-shaped 96% alumina insulating plate by a roller so as to overlap a part of the first upper surface electrode layer 2 and the second upper surface electrode layer 5, and the belt type continuous firing furnace was used to apply 600 The end face electrode layer 3 was formed by firing at a temperature of ℃ for 6 minutes and a firing profile of IN-OUT 45 minutes.

【0025】次に、電極メッキの準備工程として、端面
電極層3形成済みの、短冊状の96%アルミナ絶縁板を
個片状に分割する二次基板分割を行い、個片状の96%
アルミナ基板1を得た。そして最後に、露出している第
1上面電極層2と第2上面電極層5と端面電極層3のは
んだ付け時の電極喰われの防止およびはんだ付けの信頼
性の確保のため、電解メッキによってNiメッキ層7と
Sn−Pbのメッキ層8を形成した。
Next, as a preparatory step for electrode plating, a secondary substrate is divided into individual pieces of the strip-shaped 96% alumina insulating plate on which the end face electrode layer 3 has been formed.
Alumina substrate 1 was obtained. Finally, in order to prevent electrode erosion during soldering of the exposed first upper surface electrode layer 2, second upper surface electrode layer 5, and end surface electrode layer 3 and to secure reliability of soldering, electrolytic plating is performed. A Ni plating layer 7 and a Sn-Pb plating layer 8 were formed.

【0026】以上の工程により、本発明の実施例による
角形チップ抵抗器を得た。本実施例による角形チップ抵
抗器を、プリント基板へフローはんだ付けにより実装
し、硫化ガス試験(60℃ 95%RH(相対湿度)雰
囲気中に100ppmのH2S含有雰囲気中に100時
間放置 N=100)を実施した結果を(表1)に示
す。
Through the above steps, a rectangular chip resistor according to an embodiment of the present invention was obtained. The rectangular chip resistor according to this example was mounted on a printed circuit board by flow soldering, and left in a sulfide gas test (at 60 ° C., 95% RH (relative humidity) for 100 hours in an atmosphere containing 100 ppm of H 2 S N = The results of carrying out 100) are shown in (Table 1).

【0027】[0027]

【表1】 [Table 1]

【0028】(表1)より、本実施例の角形チップ抵抗
器は優れた信頼性を有することがわかる。
From Table 1, it can be seen that the rectangular chip resistor of this example has excellent reliability.

【0029】なお、本実施例において第2上面電極層は
銀の厚膜と、ニッケルクロムの薄膜を用いたが、銅厚膜
や銅または銀薄膜等の他の金属膜でもよい。
In this embodiment, the second upper electrode layer is made of a silver thick film and a nickel chrome thin film, but may be a copper thick film or another metal film such as a copper or silver thin film.

【0030】[0030]

【発明の効果】以上の説明より明らかなように絶縁基板
とこの絶縁基板上に形成された一対の銀系の第1上面電
極層と、この第1上面電極層の一部に重なる抵抗層と、
前記第1上面電極層に接続し前記絶縁基板端部に形成さ
れた一対の端面電極層と、抵抗層を完全に覆う保護層と
を備え、前記第1上面電極層の一部に重なるように形成
された一対の第2上面電極層を保護層の上面の一部に重
なるように構成することにより硫化ガス雰囲気中でも断
線を起こしにくいチップ抵抗器を、高価な電極材料を用
いず安価に提供できるという優れた効果が得られる。
As is apparent from the above description, the insulating substrate, the pair of first silver-based upper surface electrode layers formed on the insulating substrate, and the resistance layer overlapping a part of the first upper surface electrode layer. ,
A pair of end face electrode layers connected to the first top face electrode layer and formed at an end of the insulating substrate, and a protective layer that completely covers the resistance layer are provided so as to overlap a part of the first top face electrode layer. By forming the pair of formed second upper surface electrode layers so as to overlap a part of the upper surface of the protective layer, it is possible to inexpensively provide a chip resistor that does not easily break even in a sulfide gas atmosphere, without using an expensive electrode material. That is an excellent effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a) 本発明の第1の実施例における角形チ
ップ抵抗器の構造を示す斜視図 (b) 同角形チップ抵抗器の断面図
FIG. 1A is a perspective view showing the structure of a rectangular chip resistor according to a first embodiment of the present invention. FIG. 1B is a sectional view of the rectangular chip resistor.

【図2】(a) 本発明の第2の実施例における角形チ
ップ抵抗器の構造を示す斜視図 (b) 同角形チップ抵抗器の断面図
FIG. 2A is a perspective view showing the structure of a rectangular chip resistor according to a second embodiment of the present invention. FIG. 2B is a sectional view of the rectangular chip resistor.

【図3】(a) 従来の角形チップ抵抗器の構造を示す
斜視図 (b) 同角形チップ抵抗器の断面図
3A is a perspective view showing the structure of a conventional rectangular chip resistor, and FIG. 3B is a sectional view of the same rectangular chip resistor.

【符号の説明】[Explanation of symbols]

1 96%アルミナ基板 2 第1上面電極層 3 端面電極層 4 抵抗層 5,9 第2上面電極層 6 オーバーコートガラス層 7 Niメッキ層 8 はんだメッキ層 1 96% Alumina Substrate 2 First Top Electrode Layer 3 End Face Electrode Layer 4 Resistance Layer 5, 9 Second Top Electrode Layer 6 Overcoat Glass Layer 7 Ni Plating Layer 8 Solder Plating Layer

Claims (4)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 絶縁基板とこの絶縁基板上に形成された
    一対の銀系の第1上面電極層と、この第1上面電極層の
    一部に重なる抵抗層と、前記第1上面電極層に接続し前
    記絶縁基板端部に形成された一対の端面電極層と、前記
    抵抗層上に抵抗層を完全に覆う保護層と、前記第1上面
    電極層上に第1上面電極層の一部に重なるように形成さ
    れた一対の第2上面電極層とを具備し、この第2上面電
    極層は保護層の上面の一部に重なっていることを特徴と
    する角形チップ抵抗器。
    1. An insulating substrate, a pair of silver-based first upper surface electrode layers formed on the insulating substrate, a resistance layer overlapping a part of the first upper surface electrode layer, and the first upper surface electrode layer. A pair of end face electrode layers that are connected to each other and are formed at the ends of the insulating substrate, a protective layer that completely covers the resistance layer on the resistance layer, and a part of the first top surface electrode layer on the first top surface electrode layer. A prismatic chip resistor comprising a pair of second upper surface electrode layers formed so as to overlap with each other, the second upper surface electrode layer overlapping a part of the upper surface of the protective layer.
  2. 【請求項2】 保護層と、第2上面電極層の重なり部の
    長手方向の長さが0.2mm以上であることを特徴とする
    請求項1記載の角形チップ抵抗器。
    2. The rectangular chip resistor according to claim 1, wherein the length of the overlapping portion of the protective layer and the second upper surface electrode layer in the longitudinal direction is 0.2 mm or more.
  3. 【請求項3】 絶縁基板上に一対の銀系の第1上面電極
    層を形成する工程と、この第1上面電極層の一部に重な
    るように抵抗層を形成する工程と、前記上面電極層に接
    続するように前記絶縁基板端部に一対の端面電極層を形
    成する工程と、前記抵抗層上に抵抗層を完全に覆うよう
    に保護層を形成する工程と、前記第1上面電極層上に第
    1上面電極層の一部に重なるように一対の第2上面電極
    層を形成する工程とを具備し、前記第2上面電極層は保
    護層形成後に銀系の印刷ペーストを厚膜印刷方式で印刷
    形成することを特徴とする角形チップ抵抗器の製造方
    法。
    3. A step of forming a pair of silver-based first upper surface electrode layers on an insulating substrate, a step of forming a resistance layer so as to overlap a part of the first upper surface electrode layers, and the upper surface electrode layer. Forming a pair of end face electrode layers on the ends of the insulating substrate so as to connect to the insulating substrate, forming a protective layer on the resistance layer so as to completely cover the resistance layer, and forming a protective layer on the first upper surface electrode layer. And a step of forming a pair of second upper surface electrode layers so as to partially overlap with the first upper surface electrode layer, wherein the second upper surface electrode layer is formed by a thick film printing method using a silver-based printing paste after forming the protective layer. A method for manufacturing a rectangular chip resistor, which is characterized in that it is formed by printing.
  4. 【請求項4】 絶縁基板上に一対の銀系の第1上面電極
    層を形成する工程と、この第1上面電極層の一部に重な
    るように抵抗層を形成する工程と、前記上面電極層に接
    続するように前記絶縁基板端部に一対の端面電極層を形
    成する工程と、前記抵抗層上に抵抗層を完全に覆うよう
    に保護層を形成する工程と、前記第1上面電極層上に第
    1上面電極層の一部に重なるように一対の第2上面電極
    層を形成する工程とを具備し、第2上面電極層は保護層
    形成後にニッケル系の薄膜を薄膜スパッタ工法にて形成
    することを特徴とする角形チップ抵抗器の製造方法。
    4. A step of forming a pair of silver-based first upper surface electrode layers on an insulating substrate, a step of forming a resistance layer so as to partially overlap with the first upper surface electrode layer, and the upper surface electrode layer. Forming a pair of end face electrode layers on the ends of the insulating substrate so as to connect to the insulating substrate, forming a protective layer on the resistance layer so as to completely cover the resistance layer, and forming a protective layer on the first upper surface electrode layer. And a step of forming a pair of second upper surface electrode layers so as to partially overlap the first upper surface electrode layer, the second upper surface electrode layer is formed by forming a nickel-based thin film by a thin film sputtering method after forming a protective layer. A method of manufacturing a rectangular chip resistor, comprising:
JP5316335A 1993-12-16 1993-12-16 Square-shaped chip resistor and its manufacture Pending JPH07169601A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5316335A JPH07169601A (en) 1993-12-16 1993-12-16 Square-shaped chip resistor and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5316335A JPH07169601A (en) 1993-12-16 1993-12-16 Square-shaped chip resistor and its manufacture

Publications (1)

Publication Number Publication Date
JPH07169601A true JPH07169601A (en) 1995-07-04

Family

ID=18075983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5316335A Pending JPH07169601A (en) 1993-12-16 1993-12-16 Square-shaped chip resistor and its manufacture

Country Status (1)

Country Link
JP (1) JPH07169601A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001155957A (en) * 1999-04-30 2001-06-08 Furuya Kinzoku:Kk Electronic component
JP2007123832A (en) * 2005-09-27 2007-05-17 北陸電気工業株式会社 Terminal structure of chip-like electrical part
JPWO2006030705A1 (en) * 2004-09-15 2008-05-15 松下電器産業株式会社 Chip-type electronic components
JP2008300607A (en) * 2007-05-31 2008-12-11 Koa Corp Chip resistor
WO2013137338A1 (en) * 2012-03-16 2013-09-19 コーア株式会社 Chip resistor for incorporation into substrate, and method for producing same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001155957A (en) * 1999-04-30 2001-06-08 Furuya Kinzoku:Kk Electronic component
JPWO2006030705A1 (en) * 2004-09-15 2008-05-15 松下電器産業株式会社 Chip-type electronic components
JP2007123832A (en) * 2005-09-27 2007-05-17 北陸電気工業株式会社 Terminal structure of chip-like electrical part
US7825769B2 (en) 2005-09-27 2010-11-02 Hokuriku Electric Co., Ltd. Terminal structure of chiplike electric component
JP2008300607A (en) * 2007-05-31 2008-12-11 Koa Corp Chip resistor
WO2008149876A1 (en) * 2007-05-31 2008-12-11 Koa Corporation Chip resistor
WO2013137338A1 (en) * 2012-03-16 2013-09-19 コーア株式会社 Chip resistor for incorporation into substrate, and method for producing same
JPWO2013137338A1 (en) * 2012-03-16 2015-08-03 コーア株式会社 Chip resistor for built-in substrate and manufacturing method thereof

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