JPH0715007A - Conductivity-modulation mosfet - Google Patents

Abstract

PURPOSE:To provide a conductivity-modulation MOSFET wherein latchup scarcely occurs. CONSTITUTION:In a conductivity-modulation MOSFET wherein p-type base diffusion layers 13 are formed in an n<-> type high resistance layer 12 of a wafer having a p<-> type drain layer 11 and the n<-> type high resistance layer 12, an n<+> type source diffusion layer is formed in the p-type base diffusion layer 13, a gate insulating film 16 and a gate electrode are formed on the base diffusion layers 13 turning to a channel region, and source electrodes 18 which are in contact with both of the diffusion layers 13 are formed, the gate electrode consists of a polycrystalline silicon film gate electrode 17 arranged so as to cover the n<-> type high resistance layer 12 and an Al gate electrode 20 stacked on the electrode 17, and a p<-> type base diffusion layer 15 is formed under the Al gate electrode 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a conductive modulation type MOSFE.
Regarding T.

[0002]

2. Description of the Related Art A conductivity modulation type MOSFET is a power MOSFET in which a drain region has a conductivity type opposite to that of a source region. Conventional conductivity modulation type MOSFET
The structure of is shown in FIG. 41 is a p ⁺ drain layer, 42 is n
^{It is a −} type high resistance layer, and a p type base diffusion layer 43 is formed on the surface of the high resistance layer 42, and an n ⁺ type source diffusion layer 44 is further formed in the p type base diffusion layer 43. The portion of the p-type base layer 43 sandwiched between the source diffusion layer 44 and the high resistance layer 42 exposed on the surface is formed into the channel region 4.
9, a gate electrode 46 is disposed on the gate insulating film 45, and a source electrode 47 that contacts both the source diffusion layer 44 and the base diffusion layer 43 is formed thereon. A drain electrode 48 is formed on the surface of the drain layer 41.

In this conductivity modulation type MOSFET, when a positive voltage is applied to the gate electrode 46 with respect to the source electrode 47, an inversion layer is formed in the channel region 49, and electrons from the source diffusion layer 44 pass through the channel region 49. Are implanted into the n ⁻ type high resistance layer 42. The injected electrons diffuse through the high resistance layer 42 and escape to the drain electrode 48, but at this time, injection of holes from the drain layer 41 is caused. By the injection of the holes, conductivity modulation occurs in the high resistance layer 42 due to the accumulation of carriers, and the resistance of the high resistance layer 42 decreases.
As a result, a MOSFET having an ON resistance lower than that of a normal power MOSFET can be obtained.

By the way, such a conductive modulation type MOSFET
Then, the p ⁺ type drain layer 41-n ⁻ type high resistance layer 42-p
The four layers of the type base diffusion layer 43-n ⁺ type source diffusion layer 44 form a thyristor. When this parasitic thyristor becomes conductive, the element cannot be turned off even if the voltage between the gate and the source becomes zero, and in many cases, the element is destroyed. The reason why the parasitic thyristor is turned on is that the holes injected from the p ⁺ type drain layer 41 pass through the p type base diffusion layer 43 when passing out to the source electrode 47. That is, when such a hole current flows and the voltage drop due to the resistance directly below the source diffusion layer 44 of the base diffusion layer 43 exceeds the built-in voltage between the base and the source, electron injection from the source layer 44 occurs, and the parasitic thyristor. Turns on.

In order to prevent such a latching phenomenon of the parasitic thyristor, a high concentration p ⁺ -type base diffusion layer 50 is formed in the p-type base diffusion layer 43 as shown in FIG. Is being lowered. However, even with this configuration, the conventional conductivity modulation type MOSFET
However, there is a problem that only a current of about 200 A / cm ² can be turned off at most. As a result of pursuing the fundamental reason, it has been clarified that the conventional conductive modulation type MOSFET uses the same source / gate pattern as the normal power MOSFET. This point will be described in detail below.

FIG. 8 shows a diffusion layer pattern of the conductivity modulation type MOSFET of FIG. As shown in the figure, a plurality of p-type base diffusion layers 43 are formed in a hexagonal shape so as to be diffused, and a channel region 49 is formed in each peripheral portion. In a power MOSFET, such a pattern is
This was effective in increasing the gate area and decreasing the on-resistance. However, there is a demand that the parasitic thyristor should not be turned on.
In the SFET, such a pattern has the following inconveniences.

First, in order to prevent the parasitic thyristor operation, from the channel region 49 to the p ⁺ type base diffusion layer 50.
It is desirable that the resistance to the opening is as small as possible. However, in the pattern of FIG. 8, the contact of the p ⁺ -type base diffusion layer 50 with the source electrode is p-type base diffusion layer 4.
3 has a peripheral length smaller than that of the channel region 49 around the p-type base diffusion layer 43, and its permeation resistance causes the channel region 49 and p
The resistance between the source electrode of the ⁺ type base diffusion layer 50 and the contact cannot be sufficiently reduced.

Secondly, in the pattern of FIG. 8, the thyristor operation is caused when the width L _{G of} the opening of the n ⁻ type high resistance layer 42 exposed on the substrate wafer surface, that is, the portion where the gate electrode is arranged is large. It has been clarified by the study of the present inventors that it is easy to do.

The fact that the drain current during latching of the parasitic thyristor is inversely proportional to L _G is shown as follows. Since a current flows substantially uniformly under the gate insulating film and flows into the p-type base layer, the next current I _P flows under the gate insulating film having a unit width of the channel region 49.

I _P = S _G · J _P / T (1) Here, J _P is the hole current density, S _G is the area of the n ⁻ -type high resistance layer opening per unit area, and T is the unit. P per area
The perimeter of the mold base diffusion layer. When this current flows into the base diffusion layer under the source diffusion layer and the voltage drop due to the resistance R _B under the source diffusion layer becomes higher than the built-in voltage Vbi between the base and the source, the parasitic thyristor turns on. Denoting this formula, the _{Vbi = I P · R B /} T = S G · J P · R B / T ... (2). However, R _B is the resistance from the channel of the p-type base layer to the p ⁺ contact per unit perimeter. When this is solved for J _P , J _P = Vbi · T / (S _G · R _B ) ... (3) At turn-off, the channel inversion layer disappears,
Since it becomes almost a hole current, the latching current density J _L
Is J _L = Vbi · T / (S _G · R _B ) ... (4) S _G / T is approximately L _G , and J _L is inversely proportional to L _G. This is also clear from FIG. 10, which is the experimental data of the present inventors. On the other hand, as shown in the perspective view of FIG.
When the laminated structure of 6 ₁ and Al film 46 ₂ is used, the Al film 46
_If the width of ₂ is 30 μm, the width of the polycrystalline silicon film 46 ₁ needs to be 50 to 60 μm. That is, when the conventional pattern as shown in FIG. 8 is used, the width L _G of the opening of the n ⁻ type high resistance layer 42 is wider in the portion where the Al film 46 exists than in other portions, that is, The width needs to be about 50 to 60 μm. This is the conventional conductive modulation type MOSF.
This is the reason why it is impossible to effectively prevent the latch-up of ET.

[0011]

As described above, the conventional conductive modulation type MOSFET has a problem that it cannot prevent latch-up effectively. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a conductive modulation type MOSFET in which latch-up hardly occurs.
To provide.

[0012]

In order to achieve the above object, a conductive modulation type MOSFET of the present invention is a semiconductor substrate having a high concentration drain layer of the first conductivity type and a high resistance layer of the second conductivity type. A first conductivity type base diffusion layer is formed in the high resistance layer portion of the wafer, and a high concentration and second conductivity type source diffusion layer is formed in the base diffusion layer. The source diffusion layer and the high resistance layer are formed. A conductive modulation type MOSFE in which a gate electrode is formed on a base diffusion layer serving as a channel region sandwiched by a gate insulating film via a gate insulating film, and a source electrode contacting both the source diffusion layer and the base diffusion layer is formed.
At T, the gate electrode is provided with a polycrystalline silicon film continuously arranged in a mesh on the semiconductor substrate wafer so as to cover the plurality of island-shaped high resistance layer portions, and the gate electrode is overlapped on the polycrystalline silicon film. A plurality of high resistance layer portions are formed on the surface of the high resistance layer below the metal film of the polycrystalline silicon film on which the metal film is disposed. And a high-concentration first conductivity type base diffusion layer is formed. In the conductivity modulation type MOSFET, it is preferable that the opening of the high resistance layer exposed on the wafer surface has an island shape completely surrounded by the base diffusion layer.

[0013]

In the case of the conventional structure, the width L _G of the polycrystalline silicon film in which the Al film (metal film) is present among the films forming the gate electrode needs to be made wider than that of the other parts.
There is a problem that the S operation easily occurs and the latch-up current decreases.

However, in the case of the present invention, since the high-concentration first conductivity type base diffusion layer is formed under the polycrystalline silicon film in the widened portion, the MOS operation is suppressed. Become.

Therefore, the current density at which latch-up occurs becomes high, and the conductivity modulation type M in which latch-up hardly occurs.
OSFET can be realized. Further, in the present invention, the opening exposed on the wafer surface of the high resistance layer is formed into an island shape completely surrounded by the base diffusion layer, that is, the portion exposed on the wafer surface of the high resistance layer is the base diffusion layer. Contrary to the conventional pattern surrounding the, by adopting a pattern in which the exposed portion of the high resistance layer on the wafer surface is surrounded by the base diffusion layer and arranged in a plurality of islands,
The following effects can be obtained.

If such a pattern is adopted, the area of the base layer resistance below the channel region and the area of the high resistance layer opening below the gate insulating film will be smaller than before, that is,
The value of S _G · R _B becomes smaller than before.

Therefore, since the value (current density J _L ) of the formula (4) found by the present inventors is larger than that of the conventional one, the current density at which latch-up occurs becomes high, for example, up to 750 A / cm ² or more. It becomes possible to realize a conductive modulation type MOSFET that does not latch up.

[0018]

Embodiments will be described below with reference to the drawings. FIG. 1 shows a conductive modulation type MOS according to an embodiment of the present invention.
It is a top view of FET. 2, 3, and 4 are a sectional view taken along the line AA ', a sectional view taken along the line BB', and a sectional view taken along the line CC 'of the conductive modulation type MOSFET shown in FIG. 1, respectively.

An n ⁻ type high resistance layer 12 is formed on the p ⁺ type drain layer 11, a p type base diffusion layer 13 is formed on the surface of the high resistance layer 12, and an n ⁺ type diffusion layer 13 is formed in the base diffusion layer 13. The source diffusion layer 14 is formed. A polycrystalline silicon gate electrode 17 made of a polycrystalline silicon film is formed on the channel region 21 between the source diffusion layer 14 and the wafer surface opening of the high resistance layer 12 via a gate insulating film 16. . A source electrode 18 that contacts both the source diffusion layer 14 and the base diffusion layer 13 is provided, and the drain electrode 11 is provided on the drain layer 11 on the back surface of the wafer.
9 is provided. The above basic structure is the same as the conventional one.

The feature of this embodiment is that first, a plurality of portions of the high resistance layer 12 opening under the polycrystalline silicon gate electrode 17 are arranged in a matrix as a rectangle shown by a width L _G in FIG. That is, the channel region 21 is formed along the long side thereof. The reason for using the rectangle is n ⁻
This is because the lateral width of the channel region can be maximized when the die high resistance layer is formed in an island shape.

The second feature is that such a plurality of rectangular openings are each completely surrounded by the p-type base diffusion layer to form an island shape. That is, the polycrystalline silicon gate electrode 17 includes the channel region 21 and the high resistance layer 12.
Is continuously arranged on the entire surface of the substrate wafer so as to cover the rectangular opening of the above, and the stripe-shaped Al gate electrode 20 is arranged in a portion on which the source electrode 18 does not run.
As shown in FIGS. 2 to 4, an Al gate electrode 20 stacked under the source electrode 18 and on the polycrystalline silicon gate electrode 17
A high-concentration p ⁺ -type base diffusion layer 15 is formed under
The type base diffusion layer 13 and the p ⁺ type base diffusion layer 15 form a rectangular opening of the high resistance layer 12.

The high-concentration p ⁺ -type base diffusion layer 15 below the Al gate electrode 20 surrounds the high-resistance layer 12 together with the p-type base diffusion layer 13 and also plays the following role. .

First, since the Al gate electrode 20 is not formed on the entire surface of the polycrystalline silicon gate electrode 17 but only partially, the width of the Al gate electrode 20 is wide in order to suppress an increase in resistance. As a result, The width L _G of the portion where the Al gate electrode 20 is provided becomes large.

The conductive modulation type MOSFET having a large width L _G easily causes latch-up as described above. In order to avoid such an inconvenience, in this embodiment, for example, FIG.
As shown in FIG.
^{The +} type base diffusion layer 15 is formed so that the conductive modulation type MOSFET is not formed in the portion where the Al gate electrode 20 is provided.

The holes flowing under the Al gate electrode 20 are discharged to the source electrode 18 through the high-concentration p ⁺ type base diffusion layer 15 and the p type base diffusion layer 13. As a result, holes flowing under the Al gate electrode 20 are
Since it directly flows into the source electrode 18 near the Al gate electrode 20, it becomes difficult to cause MOS operation, and it becomes possible to avoid a state where latch-up easily occurs.

In the actual device manufacturing, for example, a p ⁺ type Si substrate to be the drain layer 11 is used as a starting substrate and a wafer on which an n ⁻ type high resistance layer 12 is epitaxially grown is used. The electrodes are sequentially formed.
Of course, the n ⁻ type high resistance layer 12 may be used as the starting substrate.

In this embodiment, as is apparent from FIG. 1, the rectangular high resistance layer 12 opened below the gate electrode 17.
The entire lateral width of the channel on the periphery of the p ⁺ -type base diffusion layer 15 in contact with the source electrode 18 is substantially equal to the perimeter of the opening. Therefore, compared to the conventional structure as shown in FIG. 8, there is no spreading resistance, and the base diffusion layer resistance under the source diffusion layer is small. Further, since only the polycrystalline silicon gate electrode 17 is present on the portion where the high resistance layer 12 is opened on the wafer surface and there is no Al gate electrode, the gate electrode width L _G of this portion can be made sufficiently small. This L _G is inversely proportional to the latching current density as described above. In an actual prototype example, L _G = 15 μm. Therefore, according to this embodiment, the latch-up phenomenon can be prevented more effectively than in the conventional case, and the latch-up current density 750A.
/ Cm ² is obtained. Also, the total operating area is 20 mm ²
As a result, the current up to 150 A could be turned off.

The present invention is not limited to the above embodiment.
For example, the shape of the high resistance layer portion exposed on the wafer surface is not necessarily rectangular. Corresponding to the conventional pattern of FIG. 8, the pattern of the embodiment in which the arrangement of the p ⁺ type base diffusion layer for making contact with the source electrode and the n ⁻ type high resistance layer opening below the gate electrode is reversed. Is shown in FIG. Note that, in FIG. 5, portions corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. If such a pattern is used, the effect of the present invention can be easily explained by comparison with FIG. Now, it is assumed that the width Ln of the source diffusion layer 14 is the same as that in FIG. 8, and the length and the lateral width T (peripheral length) of the channel region 21 are also the same as those in FIG. In the case of FIG. 5, the current path of the hole current flowing from the high resistance layer 12 under the gate electrode to the p ⁺ type layers 13 and 15 under the channel region 21 is opposite to that of the conventional one in FIG. Therefore, p from the high resistance layer opening of the same peripheral length
The base resistance under the channel region up to the contact portion of the ⁺ type base diffusion layer with the source electrode is obviously smaller than that in the case where the p ⁺ type base diffusion layer is surrounded by the channel region and is at the center as shown in FIG. . As a result, the pattern of the present invention is less likely to latch up than the conventional one.

Further, the island-shaped high resistance layer portion has a shape similar to a rectangle having at least two parallel sides, and a channel region is formed along each four sides or two long sides. Good.

In general, in the equation (4), S _G is the area of the opening of the high resistance layer and T is the peripheral length of the opening, that is, the lateral width of the channel. Therefore, in FIG. 5 and FIG. In the case of the same, S _G · R _B is larger in FIG. 8, and therefore the current density J _{L for} latching up is generally smaller in FIG. The pattern shown in FIG. 8 used in the conventional power MOSFET is not used at present. This is because it has been clarified that in the high breakdown voltage power MOSFET, the ON resistance increases unless the area S _G of the opening of the high resistance layer and the peripheral length T are increased. However, conductivity modulation type MOS
Since the n ⁻ type layer of the FET undergoes conductivity modulation, the resistance is low, and therefore it is not necessary to make the area of the opening as wide as in the power MOSFET.

As is clear from the above description, when the present invention is applied to the conductivity modulation type MOSFET, the power MOSFE is provided.
It is possible to exert a great effect which is completely different from that applied to T.

[0032]

As described in detail above, according to the present invention, the conductive modulation type MOSF in which latch-up is less likely to occur than in the prior art.
You will be able to realize ET.

[Brief description of drawings]

FIG. 1 is a conductivity modulation type MOSFE according to an embodiment of the present invention.
Top view of T

FIG. 2 is a cross-sectional view taken along the line AA ′ of the conductivity modulation type MOSFET of FIG.

3 is a cross-sectional view of the conductivity modulation type MOSFET of FIG. 1 taken along the line BB ′.

FIG. 4 is a sectional view taken along the line CC ′ of the conductivity modulation type MOSFET of FIG.

FIG. 5 is a conduction modulation type MOSF according to another embodiment of the present invention.
The figure which shows the diffusion layer pattern of ET

FIG. 6 is a sectional view of a conventional conductivity modulation type MOSFET.

FIG. 7 is a sectional view of another conventional conductivity modulation type MOSFET.

FIG. 8 is a diagram showing a diffusion layer pattern of a conventional conductivity modulation type MOSFET.

FIG. 9 is a perspective view of a conventional conductivity modulation type MOSFET.

FIG. 10: Experimental data showing latching characteristics

[Explanation of symbols]

11 ... p ⁺ -type drain layer 12 ... n ^- -type high resistance layer 13 ... p-type base diffusion layer 14 ... n ⁺ -type source diffusion layer 15 ... p ⁺ -type base diffusion layer 16 ... gate insulating film 17 ... polysilicon gate electrode 18 ... Source electrode 19 ... Drain electrode 20 ... Al gate electrode 21 ... Channel region

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiromichi Ohashi No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research Laboratories

Claims (1)

[Claims] 1. A base diffusion layer of a first conductivity type is formed in a portion of the high resistance layer of a semiconductor substrate wafer having a high-concentration first conductivity type drain layer and a second conductivity type high resistance layer. A high-concentration, second-conductivity-type source diffusion layer is formed in the diffusion layer, and a gate electrode is formed on the base diffusion layer, which is a channel region sandwiched between the source diffusion layer and the high resistance layer, via a gate insulating film. In the conductive modulation type MOSFET, which is formed and has a source electrode in contact with both the source diffusion layer and the base diffusion layer, the gate electrode is
A polycrystalline silicon film continuously arranged in a mesh on the semiconductor substrate wafer, and a metal film arranged so as to overlap the polycrystalline silicon film, and a metal film formed on the polycrystalline silicon film. A high-concentration first-conductivity-type base diffusion layer is formed on the surface of the high-resistivity layer below the layer where is provided.