JPH071489B2 - コンピュータ装置およびコンピュータ装置においてキャッシュデータアレイ内のデータの不一致を検出して修正する方法 - Google Patents

コンピュータ装置およびコンピュータ装置においてキャッシュデータアレイ内のデータの不一致を検出して修正する方法

Info

Publication number
JPH071489B2
JPH071489B2 JP63247551A JP24755188A JPH071489B2 JP H071489 B2 JPH071489 B2 JP H071489B2 JP 63247551 A JP63247551 A JP 63247551A JP 24755188 A JP24755188 A JP 24755188A JP H071489 B2 JPH071489 B2 JP H071489B2
Authority
JP
Japan
Prior art keywords
virtual
cache
memory
address
virtual address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63247551A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01108651A (ja
Inventor
ウイリアム・ヴアン・ルー
ジヨン・ワトキンス
ジヨセフ・モラン
ウイリアム・シヤノン
レイ・チエン
Original Assignee
サン・マイクロシステムズ・インコーポレーテツド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by サン・マイクロシステムズ・インコーポレーテツド filed Critical サン・マイクロシステムズ・インコーポレーテツド
Publication of JPH01108651A publication Critical patent/JPH01108651A/ja
Publication of JPH071489B2 publication Critical patent/JPH071489B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/653—Page colouring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP63247551A 1987-10-02 1988-10-03 コンピュータ装置およびコンピュータ装置においてキャッシュデータアレイ内のデータの不一致を検出して修正する方法 Expired - Fee Related JPH071489B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10463587A 1987-10-02 1987-10-02
US104.635 1987-10-02

Publications (2)

Publication Number Publication Date
JPH01108651A JPH01108651A (ja) 1989-04-25
JPH071489B2 true JPH071489B2 (ja) 1995-01-11

Family

ID=22301527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63247551A Expired - Fee Related JPH071489B2 (ja) 1987-10-02 1988-10-03 コンピュータ装置およびコンピュータ装置においてキャッシュデータアレイ内のデータの不一致を検出して修正する方法

Country Status (7)

Country Link
JP (1) JPH071489B2 (enrdf_load_stackoverflow)
AU (1) AU609519B2 (enrdf_load_stackoverflow)
CA (1) CA1301354C (enrdf_load_stackoverflow)
DE (1) DE3832758C2 (enrdf_load_stackoverflow)
FR (1) FR2621408A1 (enrdf_load_stackoverflow)
GB (1) GB2210479B (enrdf_load_stackoverflow)
HK (1) HK95493A (enrdf_load_stackoverflow)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276798A (en) * 1990-09-14 1994-01-04 Hughes Aircraft Company Multifunction high performance graphics rendering processor
US5813046A (en) * 1993-11-09 1998-09-22 GMD--Forschungszentrum Informationstechnik GmbH Virtually indexable cache memory supporting synonyms
GB2293670A (en) * 1994-08-31 1996-04-03 Hewlett Packard Co Instruction cache
US6189074B1 (en) 1997-03-19 2001-02-13 Advanced Micro Devices, Inc. Mechanism for storing system level attributes in a translation lookaside buffer
US6446189B1 (en) 1999-06-01 2002-09-03 Advanced Micro Devices, Inc. Computer system including a novel address translation mechanism
US6510508B1 (en) 2000-06-15 2003-01-21 Advanced Micro Devices, Inc. Translation lookaside buffer flush filter
US6665788B1 (en) 2001-07-13 2003-12-16 Advanced Micro Devices, Inc. Reducing latency for a relocation cache lookup and address mapping in a distributed memory system
US6954829B2 (en) * 2002-12-19 2005-10-11 Intel Corporation Non-speculative distributed conflict resolution for a cache coherency protocol
US10846235B2 (en) 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
US11853231B2 (en) 2021-06-24 2023-12-26 Ati Technologies Ulc Transmission of address translation type packets

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148329A (en) * 1978-05-15 1979-11-20 Toshiba Corp Buffer memory control system and information processor containing buffer memory
JPS595482A (ja) * 1982-06-30 1984-01-12 Fujitsu Ltd キヤツシユバツフア装置管理方式
JPS62145341A (ja) * 1985-12-20 1987-06-29 Fujitsu Ltd キヤツシユメモリシステム
EP0282213A3 (en) * 1987-03-09 1991-04-24 AT&T Corp. Concurrent context memory management unit

Also Published As

Publication number Publication date
CA1301354C (en) 1992-05-19
GB2210479B (en) 1992-06-17
AU609519B2 (en) 1991-05-02
GB8819017D0 (en) 1988-09-14
GB2210479A (en) 1989-06-07
DE3832758C2 (de) 1996-05-30
HK95493A (en) 1993-09-24
FR2621408A1 (fr) 1989-04-07
DE3832758A1 (de) 1989-04-13
JPH01108651A (ja) 1989-04-25
AU2242288A (en) 1989-04-06
FR2621408B1 (enrdf_load_stackoverflow) 1994-04-22

Similar Documents

Publication Publication Date Title
US5119290A (en) Alias address support
JP2684196B2 (ja) ワークステーシヨン
CA2414438C (en) System and method for semaphore and atomic operation management in a multiprocessor
US7360054B2 (en) Method and apparatus for direct conveyance of physical addresses from user level code to peripheral devices in virtual memory systems
US6742104B2 (en) Master/slave processing system with shared translation lookaside buffer
US7073044B2 (en) Method and apparatus for sharing TLB entries
US7197585B2 (en) Method and apparatus for managing the execution of a broadcast instruction on a guest processor
US6907494B2 (en) Method and system of managing virtualized physical memory in a memory controller and processor system
US6920521B2 (en) Method and system of managing virtualized physical memory in a data processing system
US5463739A (en) Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold
US6904490B2 (en) Method and system of managing virtualized physical memory in a multi-processor system
WO1996012227A1 (en) An address queue capable of tracking memory dependencies
EP0766177A1 (en) Information handling system including effective address translation for one or more auxiliary processors
US7552255B1 (en) Dynamically partitioning pipeline resources
US6742103B2 (en) Processing system with shared translation lookaside buffer
US7552254B1 (en) Associating address space identifiers with active contexts
US20020156989A1 (en) Method for sharing a translation lookaside buffer between CPUs
US5479629A (en) Method and apparatus for translation request buffer and requestor table for minimizing the number of accesses to the same address
US6647468B1 (en) Method and system for optimizing translation buffer recovery after a miss operation within a multi-processor environment
JPH071489B2 (ja) コンピュータ装置およびコンピュータ装置においてキャッシュデータアレイ内のデータの不一致を検出して修正する方法
JP2000339221A (ja) 変換装置のエントリを無効化するシステム及び方法
US5687350A (en) Protocol and system for performing line-fill address during copy-back operation
JPS6237752A (ja) 別々の命令及びデ−タインタ−フエ−ス及びキヤツシユを持つたマイクロプロセサを有するマルチプルバスシステム
EP1262875A1 (en) Master/slave processing system with shared translation lookaside buffer
EP1262876B1 (en) Multiprocessing system with shared translation lookaside buffer

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees