JPH0650989Y2 - リードフレーム - Google Patents

リードフレーム

Info

Publication number
JPH0650989Y2
JPH0650989Y2 JP2416888U JP2416888U JPH0650989Y2 JP H0650989 Y2 JPH0650989 Y2 JP H0650989Y2 JP 2416888 U JP2416888 U JP 2416888U JP 2416888 U JP2416888 U JP 2416888U JP H0650989 Y2 JPH0650989 Y2 JP H0650989Y2
Authority
JP
Japan
Prior art keywords
lead
lead frame
outer leads
tie bar
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2416888U
Other languages
English (en)
Japanese (ja)
Other versions
JPH01129846U (enrdf_load_stackoverflow
Inventor
明生 吉原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP2416888U priority Critical patent/JPH0650989Y2/ja
Publication of JPH01129846U publication Critical patent/JPH01129846U/ja
Application granted granted Critical
Publication of JPH0650989Y2 publication Critical patent/JPH0650989Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2416888U 1988-02-25 1988-02-25 リードフレーム Expired - Lifetime JPH0650989Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2416888U JPH0650989Y2 (ja) 1988-02-25 1988-02-25 リードフレーム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2416888U JPH0650989Y2 (ja) 1988-02-25 1988-02-25 リードフレーム

Publications (2)

Publication Number Publication Date
JPH01129846U JPH01129846U (enrdf_load_stackoverflow) 1989-09-04
JPH0650989Y2 true JPH0650989Y2 (ja) 1994-12-21

Family

ID=31243785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2416888U Expired - Lifetime JPH0650989Y2 (ja) 1988-02-25 1988-02-25 リードフレーム

Country Status (1)

Country Link
JP (1) JPH0650989Y2 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010098156A1 (ja) * 2009-02-25 2010-09-02 三洋電機株式会社 フレームパッケージ型発光装置およびその製造方法

Also Published As

Publication number Publication date
JPH01129846U (enrdf_load_stackoverflow) 1989-09-04

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