KR100833938B1 - 반도체 패키지용 리드프레임 및 리드프레임 제조 방법 - Google Patents
반도체 패키지용 리드프레임 및 리드프레임 제조 방법 Download PDFInfo
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- KR100833938B1 KR100833938B1 KR1020020017101A KR20020017101A KR100833938B1 KR 100833938 B1 KR100833938 B1 KR 100833938B1 KR 1020020017101 A KR1020020017101 A KR 1020020017101A KR 20020017101 A KR20020017101 A KR 20020017101A KR 100833938 B1 KR100833938 B1 KR 100833938B1
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- die pad
- semiconductor chip
- downset
- forming
- etched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (6)
- 반도체 칩의 접착면과, 그 반대편 배면의 테두리에 형성된 하프 에칭면과, 상기 하프 에칭면과 단차지게 형성된 중앙 돌출면을 구비하는 다이패드;상기 다이패드로부터 이격되어 방사상으로 연장되는 복수 개의 리드;상기 다이패드의 가장자리로부터 방사상으로 연장되며 다운셋 가공된 복수 개의 타이바; 및상기 다이패드의 반도체 칩 접착면에 형성되는 도금층;을 구비하는 것으로,상기 다이패드의 하프 에칭면에는 상기 타이바와 연결되는 다운셋 지지부가 형성되며, 상기 다운셋 지지부는 중앙 돌출면과 이격되어 있는 것을 특징으로 하는 반도체 패키지용 리드프레임.
- 제 1 항에 있어서,상기 다이패드 접착면이 저면이고, 반대편 배면이 상면인 것을 특징으로 하는 반도체 패키지용 리드프레임.
- 제 1 항 또는 제 2 항에 있어서,상기 도금층이 은(Ag) 도금층인 것을 특징으로 하는 반도체 패키지용 리드프 레임.
- 소재의 소정 부분을 제거함으로써 반도체 칩이 접착될 다이패드와, 상기 다이패드의 가장자리로부터 방사상으로 연장된 복수 개의 타이바와, 상기 다이패드로부터 이격되어 방사상으로 연장되는 복수 개의 리드를 형성하는 단계;상기 다이패드에서 반도체 칩 접착면의 반대편에 있는 배면을 소정 패턴으로 하프 에칭함으로써, 테두리의 하프 에칭면과, 상기 하프 에칭면으로부터 단차진 중앙 돌출면, 및 상기 하프 에칭면상에서 상기 타이바와 연결되고 중앙 돌출면과는 이격되는 다운셋 지지부를 형성하는 단계;상기 다운셋 지지부가 지지된 상태에서 타이바를 다운셋 가공하는 단계; 및상기 다이패드의 반도체 칩 접착면에 도금층을 형성하는 단계;를 구비하는 것을 특징으로 하는 반도체 패키지용 리드프레임 제조 방법.
- 소재의 소정 부분을 제거함으로써 반도체 칩이 접착될 다이패드와, 상기 다이패드의 가장자리로부터 방사상으로 연장된 복수 개의 타이바와, 상기 다이패드로부터 이격되어 방사상으로 연장되는 복수 개의 리드를 형성하는 단계;상기 다이패드에서 반도체 칩 접착면의 반대편에 있는 배면을 소정 패턴으로 하프 에칭함으로써, 테두리의 하프 에칭면과, 상기 하프 에칭면으로부터 단차진 중앙 돌출면을 형성하는 단계;상기 중앙 돌출면의 코너가 지지된 상태에서 타이바를 다운셋 가공하는 단 계; 및상기 다이패드의 반도체 칩 접착면에 도금층을 형성하는 단계;를 구비하는 것을 특징으로 하는 반도체 패키지용 리드프레임 제조 방법.
- 제 4 항 또는 제 5 항에 있어서,상기 도금층 형성 단계는 상기 다이패드의 배면에 마스크를 씌우는 단계;상기 다이패드를 도금액에 침잠시키고 통전하는 단계; 및상기 다이패드에서 마스크를 분리하는 단계;를 구비하여 된 것을 특징으로 하는 반도체 패키지용 리드프레임 제조 방법.
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KR1020020017101A KR100833938B1 (ko) | 2002-03-28 | 2002-03-28 | 반도체 패키지용 리드프레임 및 리드프레임 제조 방법 |
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KR100833938B1 true KR100833938B1 (ko) | 2008-05-30 |
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US7612436B1 (en) | 2008-07-31 | 2009-11-03 | Micron Technology, Inc. | Packaged microelectronic devices with a lead frame |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970077547A (ko) * | 1996-05-31 | 1997-12-12 | 김광호 | 분리된 다이패드 및 그를 이용한 반도체 칩 패키지 및 제조 방법 |
KR100202286B1 (ko) * | 1994-08-11 | 1999-06-15 | 모기 준이치 | 리드프레임과 그 제조방법 |
JP2001237361A (ja) * | 2000-01-31 | 2001-08-31 | Texas Instr Inc <Ti> | 小さな持上げマウントパッドを有するリードフレーム |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100202286B1 (ko) * | 1994-08-11 | 1999-06-15 | 모기 준이치 | 리드프레임과 그 제조방법 |
KR970077547A (ko) * | 1996-05-31 | 1997-12-12 | 김광호 | 분리된 다이패드 및 그를 이용한 반도체 칩 패키지 및 제조 방법 |
JP2001237361A (ja) * | 2000-01-31 | 2001-08-31 | Texas Instr Inc <Ti> | 小さな持上げマウントパッドを有するリードフレーム |
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