JPH0637093A - Forming method for bump electrode - Google Patents
Forming method for bump electrodeInfo
- Publication number
- JPH0637093A JPH0637093A JP18652392A JP18652392A JPH0637093A JP H0637093 A JPH0637093 A JP H0637093A JP 18652392 A JP18652392 A JP 18652392A JP 18652392 A JP18652392 A JP 18652392A JP H0637093 A JPH0637093 A JP H0637093A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- photoresist
- copper
- semiconductor substrate
- head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の基板、特に
金属の内部拡散を防止できるバンプ電極の形成方法に関
連する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate of a semiconductor device, and more particularly to a method of forming a bump electrode capable of preventing metal from diffusing inside.
【0002】[0002]
【従来の技術】バンプ電極と称する半導体素子の突起状
電極は、絶縁膜に形成された開口を通じて半導体基板に
接続された下地金属層と、この下地金属層の上面に茸形
状断面で形成された中間金属層と、この中間金属層の上
面に半球状に形成された半田層とから構成される。2. Description of the Related Art A protruding electrode of a semiconductor element, called a bump electrode, is formed on a base metal layer connected to a semiconductor substrate through an opening formed in an insulating film and a mushroom-shaped cross section on the upper surface of the base metal layer. It is composed of an intermediate metal layer and a solder layer formed in a hemispherical shape on the upper surface of the intermediate metal layer.
【0003】茸形状断面を備えた中間金属層は銅(C
u)メッキ層で形成されることが多く、この場合、中間
金属層の銅と半田層中の錫(Sn)成分とが反応して両
層の界面に錫-銅合金層が形成され易いことが確認され
ている。この合金層は経時的に両層の結合強度を低下さ
せ、最終的に半田層の剥離を招来することがある。そこ
で、銅メッキ層の表面にニッケル(Ni)メッキを施し
て前記合金層の成長を抑制する技術が提案されている。
この技術では、ニッケルメッキ層によって半田層と中間
金属層間の金属成分の相互拡散を抑制することができ
る。また、錫と銅との反応で形成される合金層に比べ
て、ニッケル−銅合金層の成長速度は十分に遅いから、
合金層の成長に伴う上記剥離の問題を解消することがで
きる。An intermediate metal layer having a mushroom-shaped cross section is made of copper (C
u) It is often formed by a plating layer, and in this case, the copper of the intermediate metal layer reacts with the tin (Sn) component in the solder layer to easily form a tin-copper alloy layer at the interface between the two layers. Has been confirmed. This alloy layer may reduce the bond strength of both layers with the passage of time, and eventually lead to peeling of the solder layer. Therefore, a technique has been proposed in which the surface of the copper plating layer is plated with nickel (Ni) to suppress the growth of the alloy layer.
In this technique, the nickel plating layer can suppress mutual diffusion of metal components between the solder layer and the intermediate metal layer. Further, compared to the alloy layer formed by the reaction of tin and copper, the growth rate of the nickel-copper alloy layer is sufficiently slow,
It is possible to solve the above-mentioned problem of peeling accompanying the growth of the alloy layer.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、中間金
属層にニッケルメッキを施して半田層の剥離を防止でき
るが、バンプ電極の周辺部付近で絶縁膜と半導体基板と
の積層部にクラックが生じ易いことが判明した。この理
由は必ずしも明らかではないが、中間金属層以外の部分
に形成されたニッケルメッキ層によって熱処理の際に不
測の機械的応力が生ずるためと推測される。However, the intermediate metal layer can be plated with nickel to prevent the peeling of the solder layer, but cracks are likely to occur in the laminated portion of the insulating film and the semiconductor substrate near the peripheral portion of the bump electrode. It has been found. The reason for this is not clear, but it is presumed that the nickel plating layer formed on the portion other than the intermediate metal layer causes unexpected mechanical stress during the heat treatment.
【0005】そこで、本発明は中間金属層と半田層との
剥離を確実に防止し且つ絶縁膜及び半導体基板への損傷
の発生も抑制できるバンプ電極の形成方法を提供するこ
とを目的とする。Therefore, it is an object of the present invention to provide a bump electrode forming method capable of surely preventing separation of an intermediate metal layer and a solder layer and suppressing damage to an insulating film and a semiconductor substrate.
【0006】[0006]
【課題を解決するための手段】本発明によるバンプ電極
の形成方法は、半導体基板に直接固着され又は導電層を
介して間接的に固着された支持部及び支持部の側部から
外側に突出して支持部の上部に形成された頭部とを備え
た突起状金属層を形成する工程と、突起状金属層をポジ
形のフォトレジストで被覆する工程と、フォトレジスト
に光を射照してこれを感光させ、頭部の上面のフォトレ
ジストは除去するが、頭部と半導体基板との中間領域に
はフォトレジストを残存させる工程と、頭部の上面に選
択的に金属膜を形成する工程とを含む。SUMMARY OF THE INVENTION A bump electrode forming method according to the present invention comprises a support portion fixed directly to a semiconductor substrate or indirectly fixed via a conductive layer and protruding outward from a side portion of the support portion. Forming a protruding metal layer having a head formed on the top of the support, coating the protruding metal layer with a positive photoresist, and irradiating the photoresist with light And removing the photoresist on the upper surface of the head, but leaving the photoresist in the intermediate region between the head and the semiconductor substrate, and a step of selectively forming a metal film on the upper surface of the head. including.
【0007】[0007]
【作用】露光の際に、突起状金属層の頭部を遮光マスク
として頭部の下方に選択的にポジ形のフォトレジストを
残存させ、この残存したフォトレジストを更にマスクと
してメッキ又は蒸着を施すと、頭部の上面に選択的に金
属層を形成できる。In the exposure, the head of the protruding metal layer is used as a light-shielding mask to selectively leave a positive photoresist below the head, and the remaining photoresist is further used as a mask for plating or vapor deposition. The metal layer can be selectively formed on the upper surface of the head.
【0008】この金属層の上面に半田層を形成すると、
この金属層は突起状金属層と半田層間の金属成分の相互
拡散を抑制する作用がある。また、金属層は頭部の上面
にのみに制限して形成されるので、金属層の膨張率差に
起因する機械的応力を低減できる。When a solder layer is formed on the upper surface of this metal layer,
This metal layer has an effect of suppressing mutual diffusion of metal components between the protruding metal layer and the solder layer. Further, since the metal layer is formed only on the upper surface of the head, the mechanical stress caused by the difference in the expansion coefficient of the metal layer can be reduced.
【0009】[0009]
【実施例】以下、本発明によるバンプ電極の形成方法の
一実施例を図1〜図10について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bump electrode forming method according to the present invention will be described below with reference to FIGS.
【0010】まず、シリコン(Si)等から成る半導体
基板(ウェハ)(1)の上面全体にアルミニウム(Al)
を真空蒸着した後、これを選択的にエッチングしてバン
プ電極形成予定領域に図1に示す約2μm(マイクロメ
ータ)の厚みを有するアルミニウム層(2)を形成す
る。First, aluminum (Al) is formed on the entire upper surface of a semiconductor substrate (wafer) (1) made of silicon (Si) or the like.
Is vacuum-deposited, and then selectively etched to form an aluminum layer (2) having a thickness of about 2 μm (micrometer) shown in FIG.
【0011】次に、周知のCVD(Chemical Vapor Dep
osition)法等によって半導体基板(1)の上面全体に二
酸化珪素(SiO2)膜を形成した後、選択的にエッチン
グし、図2に示すように、バンプ電極形成予定領域に開
口(4)を有する絶縁膜(3)を形成する。アルミニウム
層(2)の中心側は開口(4)から露出し、周辺側は絶縁
膜(3)に被覆される。Next, the well-known CVD (Chemical Vapor Dep
After forming a silicon dioxide (SiO2) film on the entire upper surface of the semiconductor substrate (1) by an osition method or the like, it is selectively etched to have an opening (4) in a bump electrode formation planned region as shown in FIG. An insulating film (3) is formed. The center side of the aluminum layer (2) is exposed from the opening (4) and the peripheral side is covered with the insulating film (3).
【0012】続いて、図3のように、半導体基板(1)
の上面全体にクロム(Cr)と銅(Cu)を連続的に真空
蒸着して約4,500オングストロームの厚さのクロム
層(5)と約3μmの厚さの銅層(6)を形成する。アル
ミニウム層(2)、クロム層(5)及び銅層(6)は導電
層を形成し、クロム層(5)と銅層(6)は中間金属層を
形成する。Then, as shown in FIG. 3, the semiconductor substrate (1)
Of chromium (Cr) and copper (Cu) are continuously vacuum-deposited on the entire upper surface of the substrate to form a chromium layer (5) having a thickness of about 4,500 Å and a copper layer (6) having a thickness of about 3 μm. . The aluminum layer (2), the chromium layer (5) and the copper layer (6) form a conductive layer, and the chromium layer (5) and the copper layer (6) form an intermediate metal layer.
【0013】更に、銅層(6)の上面全体にフォトレジ
ストを形成してこの一部を選択的にエッチング除去し、
図4に示すように開口(7)を有するフォトレジスト膜
(8)を形成する。銅層(6)の一部は、バンプ電極形成
予定領域に設けられた開口(7)から露出する。続い
て、開口(7)内及びその周辺のフォトレジスト膜(8)
上に厚さ30〜40μmの銅メッキ層(9)を突起状電
極層として形成する。銅メッキ層(9)の断面形状は開
口(7)を通じて銅層(6)に直接接触する支持部(9a)
と、開口(7)の近傍のフォトレジスト膜(8)の上面に
延在する頭部(9b)とを備えた茸形状となる。したがっ
て、銅メッキ層(9)の支持部(9a)は開口(7)内に埋
設され、頭部(9b)は支持部(9a)の側部及び開口
(7)の周縁から外側に張出している。Further, a photoresist is formed on the entire upper surface of the copper layer (6) and a part thereof is selectively removed by etching.
As shown in FIG. 4, a photoresist film (8) having an opening (7) is formed. A part of the copper layer (6) is exposed from the opening (7) provided in the bump electrode formation planned region. Then, the photoresist film (8) in and around the opening (7)
A copper plating layer (9) having a thickness of 30 to 40 μm is formed thereon as a protruding electrode layer. The cross-sectional shape of the copper plating layer (9) has a supporting portion (9a) that directly contacts the copper layer (6) through the opening (7).
And a head portion (9b) extending on the upper surface of the photoresist film (8) near the opening (7). Therefore, the support portion (9a) of the copper plating layer (9) is embedded in the opening (7), and the head portion (9b) extends outward from the side portion of the support portion (9a) and the peripheral edge of the opening (7). There is.
【0014】次に、図4のフォトレジスト膜(8)を除
去した後、半導体基板(1)を所定のエッチング液中に
浸漬させて、図5に示すように銅メッキ層(9)の支持
部(9a)よりも外側に延在したクロム層(5)と銅層
(6)を部分的に除去する。エッチングの際に銅メッキ
層(9)がマスクとなるため、支持部(9a)の下方とそ
の近接部分にクロム層(5a)と銅層(6a)が残存する。
本実施例では、中間金属層を構成するクロム層(5)と
銅層(6)の各周縁部は頭部(9b)より内側に位置す
る。前記エッチング処理では銅メッキ層(9)の表面部
も若干溶融するが、銅メッキ層(9)の径及び厚みはク
ロム層(5)及び銅層(6)に比べて十分に大きいので、
銅メッキ層(9)のエッチングによる影響は無視できる
程度である。Next, after removing the photoresist film (8) of FIG. 4, the semiconductor substrate (1) is immersed in a predetermined etching solution to support the copper plating layer (9) as shown in FIG. The chromium layer (5) and the copper layer (6) extending outside the portion (9a) are partially removed. Since the copper plating layer (9) serves as a mask during etching, the chromium layer (5a) and the copper layer (6a) remain below the supporting portion (9a) and in the vicinity thereof.
In this embodiment, the respective peripheral portions of the chromium layer (5) and the copper layer (6) forming the intermediate metal layer are located inside the head portion (9b). In the etching treatment, the surface portion of the copper plating layer (9) is also slightly melted, but since the diameter and thickness of the copper plating layer (9) are sufficiently larger than those of the chromium layer (5) and the copper layer (6),
The effect of etching the copper plating layer (9) is negligible.
【0015】次に、図6に示すように、半導体基板
(1)の上面全体に第1のポジ形フォトレジスト(10)
と第2のポジ形フォトレジスト(11)を順次塗布する。
第1のポジ形フォトレジスト(10)と第2のポジ形フォ
トレジスト(11)はいずれも露出されることによってア
ルカリ水溶液等の現像液に対して可溶性となるフォトレ
ジストである。ここで、銅メッキ層(9)の頭部(9b)
と絶縁膜(3)の対向間隔は数10μmの幅狭領域Aで
ある。本実施例では、相対的に流動性の高い第1のポジ
形フォトレジスト(10)で幅狭領域Aにこれを充填した
後、相対的に流動性の低い第2のポジ形フォトレジスト
(11)を塗布することにより、大きなレジスト膜厚を確
保し且つ幅狭領域Aにフォトレジストを良好に充填する
ことができる。Next, as shown in FIG. 6, a first positive photoresist (10) is formed on the entire upper surface of the semiconductor substrate (1).
And a second positive photoresist (11) are sequentially applied.
Both the first positive photoresist (10) and the second positive photoresist (11) are photoresists that become soluble in a developing solution such as an alkaline aqueous solution when exposed. Here, the head (9b) of the copper plating layer (9)
And the insulating film (3) face each other in a narrow region A of several tens of μm. In this embodiment, after filling the narrow region A with the first positive photoresist (10) having relatively high fluidity, the second positive photoresist (11) having relatively low fluidity is provided. By applying (1), it is possible to secure a large resist film thickness and satisfactorily fill the narrow region A with photoresist.
【0016】図6のように、フォトレジストは頭部(9
b)の外周側で相対的に薄く形成される。また、頭部(9
b)の外周側から離間するにつれてフォトレジストの厚
さは薄くなる。As shown in FIG. 6, the photoresist has a head (9
It is formed relatively thin on the outer peripheral side of b). Also, the head (9
The thickness of the photoresist becomes thinner as it is separated from the outer peripheral side of b).
【0017】次に、フォトレジスト(10)(11)に対し
て半導体基板(1)の表面に直交する図6の矢印B方向
に紫外線を照射すると、遮光マスクとなる銅メッキ層
(9)の頭部(9b)は、幅狭領域Aに充填されたフォト
レジスト(10)(11)への紫外線の照射を阻止する。紫
外線の照射後、半導体基板(1)をアルカリ水溶液等の
現像液に浸漬すると、図7に示すように、幅狭領域A内
のフォトレジスト(10a)(11a)は残存し、他領域のフ
ォトレジスト(10)(11)はエッチング除去される。Next, the photoresists (10) and (11) are irradiated with ultraviolet rays in the direction of arrow B in FIG. 6 which is orthogonal to the surface of the semiconductor substrate (1), whereby the copper plating layer (9) serving as a light-shielding mask is formed. The head portion (9b) blocks irradiation of the photoresist (10) (11) filled in the narrow region A with ultraviolet rays. When the semiconductor substrate (1) is dipped in a developing solution such as an alkaline aqueous solution after being irradiated with ultraviolet rays, as shown in FIG. 7, the photoresists (10a) and (11a) in the narrow region A remain and the photo resists in other regions are left. The resists (10) (11) are removed by etching.
【0018】次に、図7の半導体基板(1)にニッケル
(Ni)メッキを施して、銅メッキ層(9)の頭部(9b)
上面に0.5μm程度の厚みのニッケルメッキ層(12)
を金属膜として形成する。フォトレジスト(10a)(11
a)によって被覆された頭部(9b)の下面、支持部(9
a)、クロム層(5a)及び銅層(6a)の側面にはニッケ
ルメッキ層(12)が形成されない。特に、フォトレジス
ト(10a)(11a)は、クロム層(5a)及び銅層(6a)に
対するニッケルメッキ層(12)の付着を有効に阻止す
る。二酸化珪素からなる絶縁膜(3)は、フォトレジス
ト(10a)(11a)によってニッケルメッキ層(12)と完
全に分断されているから、これにはニッケルメッキは付
着しない。Next, the semiconductor substrate (1) of FIG. 7 is plated with nickel (Ni), and the head portion (9b) of the copper plating layer (9).
Nickel plating layer (12) with a thickness of about 0.5 μm on the top surface
Is formed as a metal film. Photoresist (10a) (11
The underside of the head (9b) covered by a), the support (9
a), the nickel plating layer (12) is not formed on the side surfaces of the chromium layer (5a) and the copper layer (6a). In particular, the photoresists (10a) (11a) effectively prevent the nickel plating layer (12) from adhering to the chromium layer (5a) and the copper layer (6a). Since the insulating film (3) made of silicon dioxide is completely separated from the nickel plating layer (12) by the photoresists (10a) (11a), the nickel plating does not adhere to it.
【0019】最後に、図9に示すように、銅メッキ層
(9)の上面にニッケルメッキ層(12)を介して鉛(P
b)と錫(Sn)を成分とする半田をメッキ等によって選
択的に付着させて半球状の半田層(13)を形成し、バン
プ電極を完成する。ニッケルメッキ層(12)の厚みは、
機械的応力の低減のために1μm以下が望ましいが、銅
メッキ層(9)と半田層(13)間の金属成分の相互拡散
を十分に抑制するため、0.3μm以上が良い。Finally, as shown in FIG. 9, lead (P) is formed on the upper surface of the copper plating layer (9) through the nickel plating layer (12).
Solder containing b) and tin (Sn) as components is selectively adhered by plating or the like to form a hemispherical solder layer (13) to complete the bump electrode. The thickness of the nickel plating layer (12) is
The thickness is preferably 1 μm or less in order to reduce the mechanical stress, but is preferably 0.3 μm or more in order to sufficiently suppress the mutual diffusion of metal components between the copper plating layer (9) and the solder layer (13).
【0020】本実施例によって形成されたバンプ電極に
よれば以下の効果が得られる。According to the bump electrode formed in this embodiment, the following effects can be obtained.
【0021】(1) 銅メッキ層(9)と半田層(13)との
間にニッケルメッキ層(12)が介在するので、銅メッキ
層(9)の銅と半田層(13)の鉛又は錫の相互拡散が抑
制され、合金層成長に伴うバンプ電極の層間剥離を防止
できる。(1) Since the nickel plating layer (12) is interposed between the copper plating layer (9) and the solder layer (13), copper of the copper plating layer (9) and lead of the solder layer (13) or Mutual diffusion of tin is suppressed, and delamination of the bump electrodes due to alloy layer growth can be prevented.
【0022】(2) 銅メッキ層(9)の上面にのみニッケ
ルメッキ層(12)が形成されるので、ニッケルメッキ層
(12)の膨張率の差異等に起因する機械的応力が絶縁膜
(3)及び半導体基板(1)に影響を与えない。(2) Since the nickel plating layer (12) is formed only on the upper surface of the copper plating layer (9), the mechanical stress due to the difference in the expansion coefficient of the nickel plating layer (12) is caused by the insulating film ( 3) and does not affect the semiconductor substrate (1).
【0023】本発明の実施態様は前記の実施例に限定さ
れず、更に変更が可能である。例えば、本発明は、電力
用ショットキバリアダイオード及びその他の半導体装置
に本発明を適用することが可能である。また、アルミニ
ウム層(2)、クロム層(5)及び銅層(6)により導電
層を構成したが、導電層を省略して銅メッキ層(9)を
半導体基板(1)に直接固着したり、所望数の層を介し
て銅メッキ層(9)を半導体基板(1)に固着することが
できる。更に、突起状電極層として銅メッキ層(9)を
形成する例を示したが、アルミニウム等他の金属でもよ
い。フォトレジスト(10)(11)の感光、現像を2回に
分けて行ってもよい。まず、図10のようにレジストの
厚みの差を利用して、頭部(9b)の外周側にもレジスト
が残存するようにして再度感光現像して図7のようにレ
ジストを形成してもよい。The embodiment of the present invention is not limited to the above embodiment, and can be modified. For example, the present invention can be applied to power Schottky barrier diodes and other semiconductor devices. Further, although the conductive layer is composed of the aluminum layer (2), the chromium layer (5) and the copper layer (6), the conductive layer may be omitted and the copper plating layer (9) may be directly fixed to the semiconductor substrate (1). The copper plating layer (9) can be fixed to the semiconductor substrate (1) through a desired number of layers. Furthermore, although the example in which the copper plating layer (9) is formed as the protruding electrode layer has been shown, other metals such as aluminum may be used. Photosensitization and development of the photoresists (10) and (11) may be performed twice. First, as shown in FIG. 10, by utilizing the difference in the thickness of the resist, the resist is left on the outer peripheral side of the head portion (9b), and the photoresist is developed again to form the resist as shown in FIG. Good.
【0024】[0024]
【発明の効果】前述のように、本発明では、頭部の上面
にのみに制限して形成された金属層により中間金属層と
半田層との剥離を確実に防止し且つ絶縁膜及び半導体基
板への損傷の発生も抑制できるバンプ電極の形成方法が
得られる。As described above, according to the present invention, the metal layer formed only on the upper surface of the head prevents the intermediate metal layer and the solder layer from being separated from each other, and the insulating film and the semiconductor substrate. A bump electrode forming method capable of suppressing the occurrence of damage to the bump electrode is obtained.
【図1】 本発明によるバンプ電極の形成方法に使用す
る半導体基板にアルミニウム層を形成した状態を示す断
面図FIG. 1 is a cross-sectional view showing a state in which an aluminum layer is formed on a semiconductor substrate used in the method for forming bump electrodes according to the present invention.
【図2】 図1において絶縁層を形成した状態を示す断
面図FIG. 2 is a sectional view showing a state in which an insulating layer is formed in FIG.
【図3】 図2において中間金属層を形成した状態を示
す断面図FIG. 3 is a cross-sectional view showing a state in which an intermediate metal layer is formed in FIG.
【図4】 図3において銅メッキ層を突起状電極層とし
て形成した状態を示す断面図FIG. 4 is a cross-sectional view showing a state in which a copper plating layer is formed as a protruding electrode layer in FIG.
【図5】 図4において中間金属層の周縁部をエッチン
グ除去した状態を示す断面図FIG. 5 is a cross-sectional view showing a state in which the peripheral edge portion of the intermediate metal layer is removed by etching in FIG.
【図6】 図5においてフォトレジストを塗布した状態
を示す断面図FIG. 6 is a cross-sectional view showing a state in which a photoresist is applied in FIG.
【図7】 図6において紫外線の照射後、突起状電極層
の周囲のフォトレジストを除去した状態を示す断面図FIG. 7 is a cross-sectional view showing a state in which the photoresist around the protruding electrode layer has been removed after irradiation with ultraviolet rays in FIG.
【図8】 突起状金属の上面にニッケルメッキ層を形成
した状態を示す断面図FIG. 8 is a sectional view showing a state in which a nickel plating layer is formed on the upper surface of the protruding metal.
【図9】 ニッケルメッキ層の上に半田層を形成した状
態を示す断面図FIG. 9 is a sectional view showing a state in which a solder layer is formed on a nickel plating layer.
【図10】 本発明の他の実施例を示す断面図FIG. 10 is a sectional view showing another embodiment of the present invention.
(1)...半導体基板、 (2)...アルミニウム
層、(3)...絶縁層、(4)...開口、
(5)...クロム層(導電層)、(6)...銅層(導
電層)、(7)...開口、(8)...フォトレジスト
膜、(9)...銅メッキ層、(9a)...支持部、(9
b)...頭部、(10)、(11)...フォトレジス
ト、(12)...ニッケルメッキ層(金属膜)、(1
3)...半田層、(1). . . Semiconductor substrate, (2). . . An aluminum layer, (3). . . Insulating layer, (4). . . Opening,
(Five). . . Chrome layer (conductive layer), (6). . . Copper layer (conductive layer), (7). . . Opening, (8). . . Photoresist film, (9). . . Copper plating layer, (9a). . . Support, (9
b). . . Head, (10), (11). . . Photoresist, (12). . . Nickel plating layer (metal film), (1
3). . . Solder layer,
Claims (1)
介して間接的に固着された支持部及び該支持部の側部か
ら外側に突出して前記支持部の上部に形成された頭部と
を備えた突起状金属層を形成する工程と、 前記突起状金属層をポジ形のフォトレジストで被覆する
工程と、 前記フォトレジストに光を射照してこれを感光させ、前
記頭部の上面のフォトレジストは除去するが、前記頭部
と前記半導体基板との中間領域には前記フォトレジスト
を残存させる工程と、 前記頭部の上面に選択的に金属膜を形成する工程とを含
むことを特徴とするバンプ電極の形成方法。1. A support portion directly fixed to a semiconductor substrate or indirectly fixed via a conductive layer, and a head portion protruding outward from a side portion of the support portion and formed on an upper portion of the support portion. A step of forming a protruding metal layer provided with, a step of coating the protruding metal layer with a positive photoresist, irradiating the photoresist with light to expose it to light, Although the photoresist is removed, the method includes the steps of leaving the photoresist in an intermediate region between the head and the semiconductor substrate, and selectively forming a metal film on the upper surface of the head. Forming method of bump electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18652392A JP3116573B2 (en) | 1992-07-14 | 1992-07-14 | Bump electrode for semiconductor device and method of forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18652392A JP3116573B2 (en) | 1992-07-14 | 1992-07-14 | Bump electrode for semiconductor device and method of forming the same |
Publications (2)
Publication Number | Publication Date |
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JPH0637093A true JPH0637093A (en) | 1994-02-10 |
JP3116573B2 JP3116573B2 (en) | 2000-12-11 |
Family
ID=16189990
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18652392A Expired - Fee Related JP3116573B2 (en) | 1992-07-14 | 1992-07-14 | Bump electrode for semiconductor device and method of forming the same |
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JP (1) | JP3116573B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006505955A (en) * | 2002-11-06 | 2006-02-16 | インターナショナル レクティファイアー コーポレイション | Chip scale Schottky device |
JP2006332694A (en) * | 2006-07-24 | 2006-12-07 | Megic Corp | Method for forming metal bumps on semiconductor surface |
JP2008060588A (en) * | 2007-09-21 | 2008-03-13 | Fujitsu Ltd | Method for manufacturing semiconductor device |
JP2008160158A (en) * | 2008-03-21 | 2008-07-10 | Fujitsu Ltd | Semiconductor device |
WO2021177034A1 (en) * | 2020-03-03 | 2021-09-10 | ローム株式会社 | Semiconductor device |
WO2023026984A1 (en) * | 2021-08-26 | 2023-03-02 | ローム株式会社 | Electronic component |
-
1992
- 1992-07-14 JP JP18652392A patent/JP3116573B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006505955A (en) * | 2002-11-06 | 2006-02-16 | インターナショナル レクティファイアー コーポレイション | Chip scale Schottky device |
US8921969B2 (en) | 2002-11-06 | 2014-12-30 | Siliconix Technology C. V. | Chip-scale Schottky device |
JP2006332694A (en) * | 2006-07-24 | 2006-12-07 | Megic Corp | Method for forming metal bumps on semiconductor surface |
JP2008060588A (en) * | 2007-09-21 | 2008-03-13 | Fujitsu Ltd | Method for manufacturing semiconductor device |
JP4617339B2 (en) * | 2007-09-21 | 2011-01-26 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
JP2008160158A (en) * | 2008-03-21 | 2008-07-10 | Fujitsu Ltd | Semiconductor device |
WO2021177034A1 (en) * | 2020-03-03 | 2021-09-10 | ローム株式会社 | Semiconductor device |
WO2023026984A1 (en) * | 2021-08-26 | 2023-03-02 | ローム株式会社 | Electronic component |
Also Published As
Publication number | Publication date |
---|---|
JP3116573B2 (en) | 2000-12-11 |
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