KR950003517B1 - Manufacturing method of solder bump of semiconductor device - Google Patents
Manufacturing method of solder bump of semiconductor device Download PDFInfo
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- KR950003517B1 KR950003517B1 KR1019920006298A KR920006298A KR950003517B1 KR 950003517 B1 KR950003517 B1 KR 950003517B1 KR 1019920006298 A KR1019920006298 A KR 1019920006298A KR 920006298 A KR920006298 A KR 920006298A KR 950003517 B1 KR950003517 B1 KR 950003517B1
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000007787 solid Substances 0.000 claims abstract description 4
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 104
- 238000009792 diffusion process Methods 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 238000005476 soldering Methods 0.000 claims description 5
- 230000003064 anti-oxidating effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000004411 aluminium Substances 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000003292 glue Substances 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 8
- 239000011651 chromium Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000003963 antioxidant agent Substances 0.000 description 4
- 230000003078 antioxidant effect Effects 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11472—Profile of the lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11474—Multilayer masks
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
제 1 도 및 제 2 도는 종래 반도체 소자의 솔더 범프 형성방법을 예시하는 공정도로서,1 and 2 are process diagrams illustrating a method for forming solder bumps of a conventional semiconductor device.
제1(a)도, 제1(b)도, 제1(c)도, 제1(d)도, 제1(e)도는 종래 일렉트로 플래팅방법에 의한 솔더 범프 형성 공정도.1 (a), 1 (b), 1 (c), 1 (d), and 1 (e) are solder bump forming process diagrams by the conventional electroplating method.
제2(a)도, 제2(b)도, 제2(c)도, 제2(d)도, 제2(e)도는 종래 리프트-오프 방법에 의한 솔더 범프 형성 공정도.2 (a), 2 (b), 2 (c), 2 (d), and 2 (e) are solder bump forming process diagrams by the conventional lift-off method.
제3(a)도, 제3(b)도, 제3(c)도, 제3(d)도, 제3(e)도, 제3(f)도, 제3(g)도, 제3(h)도는 본 발명에 의한 반도체 소자의 솔더 범프 형성방법을 설명하기 위한 공정도.Third (a), third (b), third (c), third (d), third (e), third (f), third (g), third 3 (h) is a process chart for explaining a solder bump forming method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 소자 12 : 알루미늄 패드11: semiconductor device 12: aluminum pad
13 : PR층 14 : 절연층13: PR layer 14: insulation layer
15 : 범프에어리어 16 : 접착층15 bump area 16 adhesive layer
17 : 확산 방지층 18 : 산화방지층17 diffusion barrier layer 18 antioxidant layer
19 : 솔더 범프 20 : 메탈 마스크19: solder bump 20: metal mask
본 발명의 반도체 소자의 솔더 범프(Solder Bump)형성방법에 관한 것으로, 특히 플립 칩(Flip Chip)을 위한 솔더 범프를 형성함에 있어서 메탈디포지션(Metal Deposition)시의 메탈 브리지(Metal Bridge)현상을 방지하고, 공정을 단순화하며, 포토레지스트(Photo Resist)층의 두께를 보다 줄일 수 있도록 하기 위한 반도체 소자의 솔더 범프 형성방법에 관한 것이다.The present invention relates to a method of forming a solder bump of a semiconductor device of the present invention. In particular, in forming a solder bump for a flip chip, a metal bridge phenomenon during metal deposition is disclosed. The present invention relates to a method of forming a solder bump in a semiconductor device to prevent the process, simplify the process, and further reduce the thickness of a photoresist layer.
일반적으로 플립 칩은 단순화하며, 디바이스와는 달리 별도의 패키징(Packing)을 행하지 않고 상면에 격자 형태로 배열된 다수개의 알루미늄 패드위의 각각 솔더 범프를 형성하고, 이 솔더 범프를 이용하여 기판에 표면 실장하도록 되어 있다.In general, flip chip is simplified, and unlike the device, without forming a separate packaging, each solder bump is formed on a plurality of aluminum pads arranged in a lattice form on the top surface, and the solder bump is used to surface the substrate. It is meant to be mounted.
따라서 플립 칩에서는 솔더 범프의 형성이 매우 중요한 인자로 알려지고 있는 바, 이러한 솔더 범프를 형성하는 종래의 방법으로는 제 1 도에서 보는 바와 같은 일레트로 플래팅(Electroplating)기술에 의한 방법과, 제 2 도에서 보는 바와 같은 리프트-오프(Lift-off)기술에 의한 방법이 알려지고 있다.Therefore, the formation of solder bumps is known to be a very important factor in flip chips. Conventional methods for forming such solder bumps include an electroplating technique as shown in FIG. The method by the lift-off technique as shown in FIG. 2 is known.
제 1 도는 일반적인 일렉트로 플래팅기술에 의하여 반도체 소자의 각 알루미늄 패드위에 솔더 범프를 형성하는 공정을 보인 것으로, 이 기술에 의하여 솔더 범프를 형성함에 있어서는 반도체 소자(1)의 알루미늄 패드(2)위에 크롬(Cr), 구리(Cu), 골드(Au)를 순차적으로 디포지션(Deposition)하여 제1(a)도와 같이 접착층(Adhesion layer)(3), 디퓨젼 베리어 층(Diffusion Battier Layer)(4)및 산화방지층(5)을 형성하는 제 1 단계 공정과, 포토레지스트(Photo Resist ; 이하 "PR"이라 약칭함)을 소정 두께로 코팅(Coating)한 후 마스크(Mask)를 사용하여 PR을 익스포우져(Exposure)/디벨로프(Develop)시켜 제1(b)도와 같이 범프 레어리어(6)를 형성하는 제 2 단계 공정과, 반도체 소자(1)에서는 "+"전하를 인가하고 메탈층(3,4,5)에는 "-"전하를 인가하여 솔더를 일렉트로 플래팅함으로써 제1(c)도에서와 같이 범프(7)를 형성하는 제 3 단계 공정과, 에칭(Etching)방법에 의하여 제1(d)도에서와 같이 PR 및 메탈층(3,4,5)을 제거하는 제 4 단계 공정과, 리플로워 솔더링(Reflow Soldering)함으로써 최종적으로 솔더 범프를 형성하는 제 5 단계 공정을 순차적으로 진행하여 제1(e)도에서 보는 바와 같이 반도체 소자(1)의 패드(2)위에 솔더 범프(7)를 형성하게 되는 것이었다.1 shows a process of forming solder bumps on each aluminum pad of a semiconductor device by a general electroplating technique. In forming solder bumps by this technique, chromium is deposited on the aluminum pads 2 of the semiconductor device 1. (Cr), copper (Cu), and gold (Au) are sequentially deposited to deposit an adhesion layer 3 and a diffusion barrier layer 4 as shown in FIG. And a first step of forming the anti-oxidation layer 5, coating a photoresist (hereinafter referred to as "PR") to a predetermined thickness, and then exposing the PR using a mask. A second step of forming the bump area 6 by exposure / development to form the bump layer 6 as shown in FIG. 1 (b), and in the semiconductor device 1, a "+" charge is applied to the metal layer 3 , 4,5) by electroplating the solder by applying a "-" charge, as shown in FIG. A third step of forming the bumps 7, a fourth step of removing the PR and metal layers 3, 4, and 5 as shown in FIG. 1 (d) by an etching method, and a ripple A fifth step process of finally forming solder bumps by reflow soldering is sequentially performed, and the solder bumps 7 are placed on the pads 2 of the semiconductor device 1 as shown in FIG. It was to be formed.
제 1 도에서 미설명 부호 8은 패시베이션층(Passivation Layer)을 보인 것이다.In FIG. 1, reference numeral 8 denotes a passivation layer.
제 2 도는 일반적인 리프트-오프 기술에 의하여 솔더 범프를 형성하는 공정을 보인 것으로, 이 기술에 의하여 솔더 범프를 형성함에 있어서는, 제2(a)도와 같은 반도체 소자(1')의 알루미늄 패드(2')위에 소정 두께로 PR을 적층(Lamination), 제2(b)도와 같이 PR을 익스포우저, 디벨로프하여 범프 에어리어(6')를 형성한다. 이후 제2(c)도에서와 같이 메탈 디포지션 공정을 수행하고 제2(d)도와 같이 PR제거 공정을 수행하여 범프(7)를 형성한 다음 최종적으로 리플로워 솔더링 공정을 행하여 제2(e)도와 같은 솔더 범프를 형성하게 된다.2 shows a process of forming solder bumps by a general lift-off technique. In forming solder bumps by this technique, the aluminum pad 2 'of the semiconductor element 1' as shown in FIG. ) PR is laminated on a predetermined thickness and the PR is exposed and enveloped to form a bump area 6 ′ as shown in Fig. 2 (b). Then, as shown in FIG. 2 (c), the metal deposition process is performed, as shown in FIG. 2 (d), the PR removal process is performed to form the bumps 7, and finally, the reflow soldering process is performed to perform the second (e) process. To form solder bumps.
제 2 도에서 미설명 부호 8'는 패시베이션층을 보인 것이다.In FIG. 2, reference numeral 8 ′ denotes a passivation layer.
그러나, 상기한 바와 같은 종래의 솔더 범프 형성방법에 의하면 일렉트로 플래팅 기술의 경우, 접착층(3), 확산방지층(4)및 산화방지층(5)등과 같은 메탈층을 웨이퍼 전면에 디포지션 한 후 에칭시켜야 하므로 공정이 매우 복잡하게 된다는 단점이 있었으며, 리프트-오프 기술의 경우에는 메탈(Solder)이 디포지션된 PR의 상부가 넓은 구조를 갖게 되어 알루미늄 패드(2')위에 디포지션된 메탈과 PR위에 디포지션된 메탈이 상호브리지(Bridge)될 우려가 있는 것이었다.However, according to the conventional solder bump forming method as described above, in the case of the electroplating technique, metal layers such as the adhesive layer 3, the diffusion barrier layer 4, and the antioxidant layer 5, etc. are deposited on the entire surface of the wafer and then etched. The process was very complicated because it had to be done, and in the case of lift-off technology, the upper portion of the PR on which the metal is deposited has a wide structure, and the metal and PR deposited on the aluminum pad 2 'are placed on top. There was a fear that the deposited metal would be bridged.
본 발명의 목적은 반도체 소자의 알루미늄 패드 위에 적층되는 PR층의 상부에 절연층을 형성하여 범프 에어리어의 상부폭을 그 하부폭 보다 크게 함으로써 메탈브리지를 방지하고, 알루미늄 패드위에 Cr, Cu, Au등과 같은 메탈과 범프 메탈을 동시에 디포지션함과 아울러 PR제거시 불필요한 메탈들을 동시에 제거함으로써 공정을 단순화시키도록 한 반도체 소자의 솔더 범프 형성방법을 제공하려는 것이다.An object of the present invention is to form an insulating layer on top of the PR layer laminated on the aluminum pad of the semiconductor device to prevent the metal bridge by making the upper width of the bump area larger than the lower width, Cr and Cu, Au and the like on the aluminum pad The purpose of the present invention is to provide a solder bump forming method of a semiconductor device which simplifies the process by simultaneously depositing the same metal and the bump metal and simultaneously removing unnecessary metals during PR removal.
이러한 본 발명의 목적을 달성하기 위하여 반도체 소자의 알루미늄 패드위에 솔리드 PR층 적층하여 PR층을 형성하는 단계와, 상기 PR층의 상부에 소정 두께의 절연층을 형성하는 단계와, 상기 절연층을 에칭하여 부분적으로 오픈하는 단계와, 상기 절연층 하부의 PR층을 오버 에칭하여 절연층의 오픈하는 단계와, 상기 절연층 하부의 PR층을 오버 에칭하여 절연층의 오픈 폭보다 넓은 폭의 범프 에어리어를 형성하는 단계와, 상기 범프 에어리어내에서 알루미늄 패드위에 접착층, 확산방지층, 산화방지층 및 솔더 범프를 형성하는 단계와, 화공약품을 이용하여 PR층 및 절연층을 제거하는 단계 및 상기 솔더 범프를 리플로워 솔더링 하는 단계로 이루어짐을 특징으로 하는 반도체 소자의 솔더 범프 형성방법이 제공된다.In order to achieve the object of the present invention to form a PR layer by laminating a solid PR layer on the aluminum pad of the semiconductor device, forming an insulating layer of a predetermined thickness on the PR layer, and etching the insulating layer Opening the insulating layer by partially etching the PR layer under the insulating layer, and overetching the PR layer under the insulating layer, thereby forming a bump area wider than the open width of the insulating layer. Forming an adhesive layer, an anti-diffusion layer, an anti-oxidation layer, and a solder bump on the aluminum pad in the bump area, removing the PR layer and the insulating layer using chemicals, and reflowing the solder bumps. Provided is a method for forming solder bumps of a semiconductor device, comprising the steps of soldering.
이하, 본 발명에 의한 반도체 소자의 솔더 범프 형성방법을 첨부도면에 도시한 실시예에 따라서 상세히 설명한다.Hereinafter, the solder bump forming method of the semiconductor device according to the present invention will be described in detail according to the embodiment shown in the accompanying drawings.
제 3 도는 본 발명에 의한 반도체 소자의 솔더 범프 형성방법을 보인 공정도로서 이에 도시한 바와 같이, 제3(a)도와 같이 반도체 소자(11)의 알루미늄 패드(12)위에 솔리드(Solid) PR을 적층하여 소정 두께의 PR층(13)을 형성하는 단계와, 제3(b)도와 같이 상기 PR층(13)의 상부에 소정 두께의 절연층(14)을 형성하는 단계와, 제3(c)도와 같이 상기 절연층(14)을 에칭하여 부분적으로 오픈하는 단계와, 제3(d)도와 같이 상기 절연층(14)하부의 PR층(13)을 익스포우저/디벨로프하여 상기 절연층(14)의 오픈 폭보다 넓은 폭의 범프 에러리어(15)을 형성하는 단계와, 제3(e)도와 같이 상기 범프 에어리어(15)내에서 패드(12)위에 크롬(Cr), 구리(Cu), 골드(Au), 주석(Sn), 납(Pb)등이 메탈을 차례로 증착하여 접착층(16), 확산방지층(17), 산화방지층(18)및 솔더 범프(19)를 형성하는 단계와, 제3(f)도와 같이 화공 약품을 이용하여 PR층(13) 및 절연층(14)을 제거하는 단계와, 제3(g)도와 같이 리플로워 솔더링에 의하여 솔더 범프(19)의 모양을 갖추는 단계로 이루어진다.3 is a process chart showing a solder bump forming method of a semiconductor device according to the present invention. As shown in FIG. 3A, solid PR is laminated on an aluminum pad 12 of the semiconductor device 11 as shown in FIG. Forming a PR layer 13 having a predetermined thickness, forming an insulating layer 14 having a predetermined thickness on top of the PR layer 13 as shown in FIG. 3 (b), and (3) Etching and partially opening the insulating layer 14, and as shown in FIG. 3D, the PR layer 13 under the insulating layer 14 is exposed / developed to form the insulating layer ( Forming a bump error area 15 having a width wider than the open width of 14) and chromium (Cr) and copper (Cu) on the pad 12 in the bump area 15 as shown in FIG. , Gold (Au), tin (Sn), lead (Pb), etc. deposit metal in order to form an adhesive layer 16, a diffusion barrier layer 17, an antioxidant layer 18, and a solder bump 19, Third (f) Removing the PR layer 13 and the insulating layer 14 by using a chemical agent as shown in the drawings, and the step of forming the shape of the solder bump 19 by reflow soldering as shown in the third (g).
이때, 상기 절연층(14)은 디포지션되는 메탈과 접착성이 좋지 않은 것을 사용하는 것이 바람직하다.At this time, it is preferable to use the insulating layer 14 having a poor adhesion with the deposited metal.
상기 절연층(14)을 부분적으로 오픈하는 단계는 제3(c)도에 도시한 바와같이 절연층(14)의 상면에 메탈 마스크(20)을 얹고 드라이 에칭하여 오픈할 수도 있고, 도시하지 않았지만 절연층(14)의 상부에 액체 PR층을 형성한후 에칭하여 오픈할 수도 있다.The step of partially opening the insulating layer 14 may be opened by dry etching etching the metal mask 20 on the top surface of the insulating layer 14 as shown in FIG. 3 (c). The liquid PR layer may be formed on the insulating layer 14 and then etched to open.
또한 절연층(14)을 오픈함에 있어서는 그 오픈되는 폭이 원하는 범프 에어리어(15)의 폭보다 작게 되도록 한 다음, 제3(e)도의 범프 에어리어 형성 단계에서 전원을 일반적인 에칭에 비하여 약하게 하고 에칭시간을 길게하여 오버 에칭(Over Etching)을 행함으로써 범프 에어리어(15)의 폭을 절연층(14)의 오픈 폭 보다 넓게 형성할 수 있게되는 것이며, 상부가 넓고 하부가 좁게 형성되는 것이다.In opening the insulating layer 14, the opening width is made smaller than the width of the desired bump area 15. Then, in the bump area forming step of FIG. By overetching to make the width of the bump area 15 wider than the open width of the insulating layer 14, the upper portion is wider and the lower portion is narrower.
한편, 제3(e)도에 도시한 접착층(16), 확산방지층(17), 산화방지층(18) 및 솔더 범프(19)를 형성하는 단계에서는 절연층(14)위에도 이들 메탈층(16,17,18,19)에 대응하는 메탈층(16')(17')(18')(19')이 형성되는바 범프 에어리어(15)의 폭이 절연층(14)의 폭보다 넓게 형성되어 있으므로 알루미늄 패드(12)위에 증착되는 메탈층(16)(17)(18)(19)와 절연층(14)위에 증착되는 메탈층(16')(17')(18')(19')이 서로 연결되는 메탈 브리지 현상이 발생되지 않게 된다.On the other hand, in the step of forming the adhesive layer 16, the diffusion barrier layer 17, the oxidation prevention layer 18 and the solder bumps 19 shown in FIG. 3 (e), these metal layers 16, The metal layers 16 ′, 17 ′, 18 ′, and 19 ′ corresponding to 17, 18, and 19 are formed so that the width of the bump area 15 is wider than that of the insulating layer 14. Therefore, the metal layers 16, 17, 18 and 19 deposited on the aluminum pad 12 and the metal layers 16 ', 17', 18 'and 19' deposited on the insulating layer 14 are thus provided. This metal bridge phenomenon is not generated.
도면중 미설명 부호 21은 패시베이션층을 보인 것이다.Reference numeral 21 in the figure shows a passivation layer.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 솔더 범프 형성방법에 의하면, 종래 리프트-오프 기술에 의한 솔더 범프 형성방법에 있어서 메탈(Solder)디포지션시 디포지션하고자 하는 PR층의 범프 에어리어의 형상이 상부가 넓은 구조로 되어 있어 알루미늄 패드 위에 디포지션된 메탈과 PR층위에 디포지션되는 메탈이 브리지되는 결합을 해결할 수 있는 것이다.As described above, according to the solder bump forming method of the semiconductor device according to the present invention, the shape of the bump area of the PR layer to be deposited during metal deposition in the solder bump forming method according to the conventional lift-off technique. The wide structure of the upper part solves the coupling between the metal deposited on the aluminum pad and the metal deposited on the PR layer.
즉, 본 발명에서는 제3(d)도에 도시한 바와 같이 PR층(13)위에 형성된 절연층(14)을 원하는 범프 에어리어(15)의 폭보다 작게 오픈시킨 다음 PR층(13)을 오버 에칭시킴으로써 절연층(14)의 오픈 폭보다 범프 에어리어(15)의 폭이 넓게 형성되므로 제3(e)도에 도시한 바와 같이 PR층(13)에는 접착층(16), 확산방지층(17), 산화방지층(18) 및 솔더 범프(19)에 대응하는 메탈층이 형성되지 않아 알루미늄 패드(12)에 증착되는 접착층(16), 확산방지층(17), 산화방지층(18) 및 솔더 범프(19)과 이에 대응하여 절연층(14)에 형성되는 메탈층 (16')(17')(18')(19')사이에서 메탈 브리지 현상이 발생되지 않게 되는 것이다.That is, in the present invention, as shown in FIG. 3 (d), the insulating layer 14 formed on the PR layer 13 is opened smaller than the width of the desired bump area 15, and then the overetching of the PR layer 13 is performed. As a result, the width of the bump area 15 is wider than that of the insulating layer 14, so that the adhesive layer 16, the diffusion barrier layer 17, and the oxidation layer are formed on the PR layer 13 as shown in FIG. Since the metal layer corresponding to the prevention layer 18 and the solder bumps 19 is not formed, the adhesive layer 16, the diffusion barrier layer 17, the antioxidant layer 18, and the solder bumps 19 deposited on the aluminum pad 12 may be formed. Correspondingly, a metal bridge phenomenon does not occur between the metal layers 16 ', 17', 18 ', and 19' formed on the insulating layer 14.
한편, 상술한 바와 같이 알루미늄 패드(11)위에 증착되는 접착층(16), 확산방지층(17), 산화방지층(18)및 솔더 범프(19)와 이에 대응하여 절연층(14)에 증착되는 메탈층(16')(17')(18')(19')사이에서 메탈 브리지 현상이 발생되지 않으므로 PR층(13)과 절연층(14)을 화학 약품에 의하여 제거할때 불필요한 메탈층(16')(17')(18')(19')이 동시에 제거되므로 전체 공정을 간소화할 수 있게 되는 것이다.Meanwhile, as described above, the adhesive layer 16, the diffusion barrier layer 17, the anti-oxidation layer 18, and the solder bumps 19 deposited on the aluminum pad 11 and the metal layer deposited on the insulating layer 14 correspondingly. Since no metal bridge phenomenon occurs between (16 '), 17', 18 'and 19', the metal layer 16 'which is unnecessary when the PR layer 13 and the insulating layer 14 are removed by chemicals ) 17 ', 18' and 19 'are removed at the same time, simplifying the overall process.
또한 PR층(13)위에 절연층(14)을 형성하여 상술한 바와 같이 메탈 브리지 현상을 확실하게 방지할 수 있으므로 종래 방법에서와 동일한 높이의 솔더 범프를 형성하고자 하는 경우 PR층(13)의 두께를 보다 줄일 수 있어 이로 인한 PR재료와 이 PR층을 제거하기 위한 화학 약품을 절감할 수 있는 부수적인 효과도 있는 것이다.In addition, since the insulating layer 14 is formed on the PR layer 13 to reliably prevent the metal bridge phenomenon as described above, the thickness of the PR layer 13 when a solder bump having the same height as in the conventional method is to be formed. In addition, it can reduce the amount of PR material and chemicals for removing the PR layer.
Claims (4)
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| KR1019920006298A KR950003517B1 (en) | 1992-04-15 | 1992-04-15 | Manufacturing method of solder bump of semiconductor device |
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| KR1019920006298A KR950003517B1 (en) | 1992-04-15 | 1992-04-15 | Manufacturing method of solder bump of semiconductor device |
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