JP6836615B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device.

Conventionally, there is a semiconductor device in which a mounting area is reduced by laminating and connecting substrates provided with semiconductor elements and integrated circuits. Such a semiconductor device can be miniaturized in the length direction and the width direction as compared with the case where a plurality of substrates are placed flat and mounted, but there is room for improvement in the miniaturization in the thickness direction.

Japanese Unexamined Patent Publication No. 2013-187259

One embodiment aims to provide a semiconductor device and a method for manufacturing the semiconductor device, which can be miniaturized in the thickness direction.

According to one embodiment, a semiconductor device is provided. The semiconductor device according to the embodiment is provided in a first substrate having a first wiring using copper and tungsten and a first semiconductor layer inside, and a surface layer of the first substrate, and is connected to the first wiring. An aluminum pad, a passivation film provided on the surface layer side of the first substrate and covering a part of the aluminum pad, and a part of the passivation film embedded in the passivation film and connected to the aluminum pad, and the top surface is the passivation. A first nickel electrode protruding from the film, a first penetrating electrode penetrating the first semiconductor layer, a first silicon nitride film covering at least a part of the first semiconductor layer, and a part of the first silicon nitride. A second substrate embedded in a film, connected to the first through electrode, having a second nickel electrode whose top surface projects from the first silicon nitride film, a second semiconductor layer, and laminated on the first substrate. A second penetrating electrode penetrating the second semiconductor layer, a second silicon nitride film covering at least a part of the second semiconductor layer, and a part thereof are embedded in the second silicon nitride film, and the top surface is formed. The first penetrating electrode includes a third nickel electrode protruding from the second silicon nitride film, a connecting layer formed of an alloy containing tin and connecting the first nickel electrode and the third nickel electrode. Is electrically connected to the aluminum pad via the first wiring and is directly connected to the second nickel electrode, and the second through electrode is directly connected to the third nickel electrode.

Explanatory drawing which shows the typical cross section of the semiconductor device which concerns on embodiment. The explanatory view which shows the manufacturing process of the semiconductor device which concerns on embodiment. The explanatory view which shows the manufacturing process of the semiconductor device which concerns on embodiment. The explanatory view which shows the manufacturing process of the semiconductor device which concerns on embodiment. The explanatory view which shows the manufacturing process of the semiconductor device which concerns on embodiment. The explanatory view which shows the manufacturing process of the semiconductor device which concerns on embodiment. The explanatory view which shows the manufacturing process of the semiconductor device which concerns on embodiment.

The semiconductor device according to the embodiment and the method for manufacturing the semiconductor device will be described in detail with reference to the accompanying drawings. The present invention is not limited to this embodiment. FIG. 1 is an explanatory view showing a schematic cross section of the semiconductor device 1 according to the embodiment.

As shown in FIG. 1, in the semiconductor device 1 according to the embodiment, the mounting area can be reduced by stacking and connecting the first substrate 10 provided with semiconductor elements and integrated circuits and the second substrate 11. It has a possible structure.

Here, a general semiconductor device manufactured by laminating substrates is a pillar-shaped electrode (hereinafter, "pillar electrode") formed on the surface of each substrate on the facing side, for example, using copper. ”) Is provided, and the pillar electrodes facing each other are connected to each other using solder.

However, if the copper pillar electrodes are directly connected to each other using solder, the solder diffuses into the pillar electrodes and the connection characteristics deteriorate. Therefore, a barrier layer for preventing the diffusion of solder is generally provided between the pillar electrode and the solder.

However, in such a configuration, since the pillar electrodes, the barrier layer, the solder layer, the barrier layer, and the pillar electrodes are sequentially laminated between the substrates, the distance between the laminated substrates becomes wide and the thickness of the semiconductor device increases. Therefore, the semiconductor device 1 is provided with a pillar electrode formed by using Ni (nickel) capable of suppressing the diffusion of solder instead of the copper pillar electrode, thereby enabling miniaturization in the thickness direction.

Specifically, the first substrate 10 of the semiconductor device 1 includes a semiconductor layer 8, a protective film 80 provided on the lower surface of the semiconductor layer 8, and a first insulating layer 30 and a second insulating layer 30 sequentially laminated on the semiconductor layer 8. It includes an insulating layer 4 and a passivation film 5.

The protective film 80 is formed using, for example, SiN (silicon nitride). The semiconductor layer 8 is formed using, for example, Si (silicon), and a through electrode 81 that penetrates the front and back surfaces of the semiconductor layer 8 is provided inside. The through electrode 81 is formed by using, for example, Cu (copper) or Ni (nickel).

Further, at the interface between the through electrode 81 and the semiconductor layer 8, a barrier metal film 82 for preventing the diffusion of metal (for example, Cu) from the through electrode 81 to the semiconductor layer 8 is provided. The barrier metal film 82 is formed using, for example, Ti (titanium). Although not shown here, a semiconductor element, an integrated circuit, or the like is provided inside the semiconductor layer 8. Further, although not shown here, an insulating film using, for example, SiO2 (silicon oxide) is provided between the protective film 80 and the semiconductor layer 8 and between the barrier metal film 82 and the semiconductor layer 8.

The first insulating layer 30 is formed by using, for example, SiO2, and the multilayer wiring 3 is provided inside. The multilayer wiring 3 includes a first wiring 31 connected to the upper surface of the through electrode 81, a second wiring 32 connected to the upper surface of the first wiring 31, and a third wiring 33 connected to the upper surface of the second wiring 32. And include.

The first wiring 31 is formed using, for example, W (tungsten). The second wiring 32 and the third wiring 33 are formed using, for example, Cu. The second wiring 32 and the third wiring 33 are covered with the barrier metal film 34. The barrier metal film 34 is formed using, for example, Ti.

The second insulating layer 4 is formed by using, for example, SiO2, and an aluminum pad 40 connected to the upper surface of the third wiring 33 is provided inside. The aluminum pad 40 is covered with the barrier metal film 41. The barrier metal film 41 is formed using, for example, Ti. The passivation film 5 is formed by using, for example, SiN or polyimide.

A part of the upper surface of the first substrate 10 is embedded in the passivation film 5 and connected to the aluminum pad 40, and the top surface is formed by using pillar-shaped Ni (nickel) protruding from the surface of the passivation film 5. The first Ni electrode 6 is provided.

A barrier metal film 60 is provided at the interface between the first Ni electrode 6 and the passivation film 5. The barrier metal film 60 is formed using, for example, Ti. Further, the first Ni electrode 6 includes a Cu diffusion region 61 containing Cu at a portion in contact with the barrier metal film 60. The Cu diffusion region 61 is formed by diffusing Cu used as a seed in the step of forming the first Ni electrode 6 to the first Ni electrode 6.

Further, the first substrate 10 is provided with a second Ni electrode 9 formed by using pillar-shaped Ni (nickel) on the lower surface side. Specifically, the second Ni electrode 9 has a shape in which a part thereof is embedded in the protective film 80 and the top surface protrudes from the surface (here, the lower surface) of the protective film 80.

A barrier metal film 90 is provided at the interface between the second Ni electrode 9 and the protective film 80. The barrier metal film 90 is formed using, for example, Ti. Further, the second Ni electrode 9 includes a Cu diffusion region 91 containing Cu at a portion in contact with the barrier metal film 90. The Cu diffusion region 91 is formed by diffusing Cu used as a seed in the step of forming the second Ni electrode 9 to the second Ni electrode 9.

Further, a connecting layer 7 formed of an alloy containing Sn (tin) is provided on the top surface (here, the lower surface) of the second Ni electrode 9. Such a connection layer 7 is formed by using, for example, solder. Further, the connection layer 7 includes an Au diffusion region 71 containing Au (gold) at a portion in contact with the second Ni electrode 9.

The Au diffusion region 71 is formed by diffusing Au of the Au film 104 (see (c) of FIG. 4), which will be described later, formed on the top surface of the second Ni electrode 9 in the middle of the manufacturing process to the connecting layer 7. .. When the first substrate 10 is laminated on another substrate (not shown), the connection layer 7 is connected to a connection terminal on the surface of the other substrate. A support portion 72 is provided between the adjacent second Ni electrodes 9. The support portion 72 is formed by using, for example, a photosensitive adhesive resin.

On the other hand, the second substrate 11 has the same configuration of the connecting portions on the upper surface and the back surface side as the first substrate 10. Here, the configurations of the semiconductor element and the integrated circuit formed inside the second substrate 11 may be the same as or different from those of the first substrate 10. Therefore, FIG. 1 selectively shows a portion of the second substrate 11 below the semiconductor layer 8.

In the semiconductor device 1, the second substrate 11 is laminated on the first substrate 10. As a result, in the semiconductor device 1, the connection layer 7 of the second substrate 11 is laminated directly above the first Ni electrode 6 of the first substrate 10, and the second Ni electrode 9 of the second substrate 11 is directly above the connection layer 7. The structure is such that the second substrate 11 is laminated on the second Ni electrode 9 of the second substrate 11.

Further, in the semiconductor device 1, one end surface (here, the upper surface) of the support portion 72 of the second substrate 11 abuts on the lower surface of the protective film 80 of the second substrate 11, and the other end surface (here, the lower surface) is in contact with the lower surface. It comes into contact with the upper surface of the passivation film 5 of the first substrate 10.

As described above, the semiconductor device 1 includes a first substrate 10 provided with the multilayer wiring 3, an aluminum pad 40 provided in the surface layer of the first substrate 10 and connected to the multilayer wiring 3, and a part of the first substrate. It includes a first Ni electrode 6 embedded in the substrate 10 and connected to the aluminum pad 40. The top surface of the first Ni electrode 6 projects from the surface of the first substrate 10.

Further, the semiconductor device 1 has a second substrate 11 laminated on the first substrate 10, and a second substrate 11 which is partially embedded in the second substrate 11 and whose top surface projects from the surface of the second substrate 11 on the first substrate 10 side. A 2Ni electrode 9 and a solder connection layer 7 for connecting the first Ni electrode 6 and the second Ni electrode 9 are provided.

As described above, in the semiconductor device 1, the first substrate 10 and the second substrate 11 are connected by a laminate of three types of components, the first Ni electrode 6, the solder connection layer 7, and the second Ni electrode 9. .. For this reason, the semiconductor device 1 is a laminate of five types of components, that is, a pillar electrode, a barrier layer, a solder layer, a barrier layer, and a pillar electrode, between the substrates on which the substrates provided with general Cu pillar electrodes are laminated. Compared to the semiconductor device connected by, it is possible to reduce the size in the thickness direction.

The first Ni electrode 6 of the semiconductor device 1 includes a Cu diffusion region 61 containing Cu at a portion in contact with the barrier metal film 60. The first Ni electrode 6 can be formed by using general Cu as a seed. Therefore, according to the present embodiment, it is possible to manufacture the semiconductor device 1 capable of miniaturization in the thickness direction without significantly changing the existing general manufacturing process.

Further, the connection layer 7 of the semiconductor device 1 includes an Au diffusion region 71 containing Au at a portion in contact with the first Ni electrode 6 and a portion in contact with the second Ni electrode 9. As a result, the semiconductor device 1 can reduce the connection resistance between the connection layer 7 and the first Ni electrode 6 and the second Ni electrode 9.

Further, the semiconductor device 1 has a support portion 72 formed by using a resin in which one end face abuts on the surface of the first substrate 10 and the other end face abuts on the surface of the second substrate 11 on the first substrate 10 side. To be equipped. Such a support portion 72 can prevent the distance between the first substrate 10 and the second substrate 11 from becoming excessively narrow when the second substrate 11 is laminated on the first substrate 10.

Therefore, according to the semiconductor device 1, when the second substrate 11 is laminated on the first substrate 10, the solder of the connection layer 7 is excessively crushed and hangs down, and adheres to the passivation film 5 of the first substrate 10. It is possible to prevent the occurrence of current leakage.

When the height of the top surface of the first Ni electrode 6 from the surface of the passivation film 5 is 1 μm to 10 μm and the height (thickness) of the support portion 72 is 17 μm to 25 μm, the occupied area of the support portion 72 is the first substrate. If it is 10% to 50% of the area of 10 surfaces, it is possible to prevent the solder from dripping.

Next, a method of manufacturing the semiconductor device 1 according to the embodiment will be described with reference to FIGS. 2 to 7. 2 to 7 are explanatory views showing a manufacturing process of the semiconductor device 1 according to the embodiment. Hereinafter, among the components shown in FIGS. 2 to 7, the same components as those shown in FIG. 1 are designated by the same reference numerals as those shown in FIG. 1, and detailed description thereof will be omitted. ..

Further, the manufacturing steps of the first substrate 10 and the second substrate 11 are the same steps except that the forming steps of the semiconductor element and the integrated circuit formed on the semiconductor layer 8 are different. Therefore, here, the manufacturing process of the first substrate 10 will be described, and the description of the manufacturing process of the second substrate 11 will be omitted.

Further, among the manufacturing steps of the first substrate 10, the step of forming the first insulating layer 30 and the multilayer wiring 3 on the semiconductor layer 8 is the same as the manufacturing process of a general semiconductor device. The explanation is omitted.

When manufacturing the semiconductor device 1, as shown in FIG. 2A, a first substrate 10 in which the first insulating layer 30 and the multilayer wiring 3 are formed on the semiconductor layer 8 is prepared. After that, as shown in FIG. 2 (b), the second insulating layer 4 is formed by laminating SiO2 on the first insulating layer 30 by, for example, CVD (Chemical Vapor Deposition).

Subsequently, for example, SiO2 of the portion forming the aluminum pad 40 is selectively removed from the second insulating layer 4 by RIE (Reactive Ion Etching), and then the surface of the second insulating layer 4 is coated with Ti. As a result, the barrier metal film 41 is formed.

Then, for example, Al (aluminum) is laminated on the second insulating layer 4 by sputtering, and then the aluminum is patterned by, for example, RIE. In this way, as shown in FIG. 2 (b), the aluminum pad 40 is formed on the second insulating layer 4.

Subsequently, as shown in FIG. 2 (c), the passivation film 5 is formed by laminating SiN or polyimide on the second insulating layer 4 on which the aluminum pad 40 is formed. The passivation film 5 may be formed between the passivation film 5 and the aluminum pad 40 via SiO2.

Then, as shown in FIG. 3A, the resist 100 is applied onto the passivation film 5, and the resist 100 on the formation position of the first Ni electrode 6 (see FIG. 1) is selectively removed by photolithography. ..

Then, by performing etching using the remaining resist 100 as a mask, the aluminum pad 40 coated with the barrier metal film 41 at the position where the first Ni electrode 6 is formed on the passivation film 5 is 0 from the surface of the passivation film 5. It forms an opening 1010 that reaches the surface.

Subsequently, as shown in FIG. 3 (b), after removing the resist 100, the upper surface of the passivation film 5, the inner peripheral surface of the opening 101, and the bottom surface are covered with Ti to form the barrier metal film 60. Form. Further, the surface of the barrier metal film 60 is coated with Cu to form the seed film 61a.

Subsequently, as shown in FIG. 3C, after applying the resist 102 to the surface of the seed film 61a, the resist 102 on the formation position of the first Ni electrode 6 (see FIG. 1) is selectively removed. To expose the opening 101 covered by the seed film 61a.

Then, as shown in FIG. 4A, the first Ni electrode 6 is formed by laminating Ni on the seed film 61a of the portion where the resist 102 is removed and exposed. Ni is laminated by electroplating using the seed film 61a as an electrode film. At the portion where the first Ni electrode 6 and the seed film 61a come into contact with each other, Ni is later diffused from the first Ni electrode 6 to the seed film 61a, and Cu is diffused from the seed film 61a to the first Ni electrode 6.

As a result, the seed film 61a in the portion in contact with the first Ni electrode 6 becomes an alloy of Cu and Ni and becomes a part of the first Ni electrode 6, and the portion in contact with the barrier metal film 60 of the first Ni electrode 6 The Cu diffusion region 61 is formed in the above.

As a result, there is no pure Cu region between the barrier metal film 60 and the first Ni electrode 6. In this way, a part of the opening 101 in which the barrier metal film 60 is formed is embedded and connected to the aluminum pad 40, and the first Ni electrode 6 whose top surface projects from the surface of the passivation film 5 is formed.

Then, after forming the Au film 103 on the upper surface of the first Ni electrode 6, the resist 102 is removed as shown in FIG. 4 (b). Then, by performing RIE using the first Ni electrode 6 on which the Au film 103 is formed as a mask, the seed film 61a and the barrier metal film 60 in the unnecessary portion are removed from the upper surface of the passivation film 5.

Subsequently, a through electrode 81 is formed inside the semiconductor layer 8. Here, for example, a protective film 80 is formed on the lower surface of the semiconductor layer 8, a TSV (Through Silicon Via) extending from the lower surface of the semiconductor layer 8 to the lower surface of the first wiring 31 is formed, and the inner peripheral surface of the TSV is made of a barrier metal. After coating with the film 82, the through electrode 81 is formed by embedding Cu inside the TSV.

After that, as shown in FIG. 4 (c), the same steps as those described with reference to FIGS. 3 and 4 are performed on the protective film 80 to form the barrier metal film 90 and the barrier metal film 90. A second Ni electrode 9 having a Cu diffusion region 91 is formed in a portion in contact with the above.

As a result, a part of the second Ni electrode 9 is embedded in the protective film 80, and a pillar-shaped second Ni electrode 9 whose top surface projects from the surface (here, the lower surface) of the protective film 80 is formed. Then, the Au film 104 is formed on the top surface (here, the bottom surface) of the second Ni electrode 9.

Subsequently, as shown in FIG. 5, a photosensitive adhesive resin 105 is applied to the lower surface of the first substrate 10. After that, exposure is performed, and the adhesive resin 105 of the portion irradiated with light is removed by development. As a result, the support portion 72 shown in FIG. 6A is formed. Then, by forming a solder layer on the lower surface of the Au film 104, the connection layer 7 is formed as shown in FIG. 6 (b).

At the portion where the connection layer 7 and the Au film 104 come into contact with each other, the solder is later diffused from the connection layer 7 to the Au film 104, and Au is diffused from the Au film 104 to the connection layer 7. As a result, the Au film 104 in the portion in contact with the connection layer 7 becomes an alloy of Au and solder and becomes a part of the connection layer 7, and the portion in contact with the second Ni electrode 9 of the connection layer 7 becomes Au. The diffusion region 71 is formed, and the first substrate 10 is completed.

Finally, as shown in FIG. 7, the completed second substrate 11 is arranged on the completed first substrate 10, and the connection layer 7 of the second substrate 11 corresponding to the first Ni electrode 6 of the first substrate 10 is arranged. After aligning the above, the second substrate 11 is laminated on the first substrate 10. As a result, the semiconductor device 1 shown in FIG. 1 is completed.

As described above, the semiconductor device according to the embodiment has three types of semiconductor devices in which the first substrate and the second substrate are the first Ni electrode on the first substrate side, the solder connection layer, and the second Ni electrode on the second substrate side. It is connected by a laminate of components.

As a result, the semiconductor device according to the embodiment is a general semiconductor in which the substrates to be laminated are connected by a laminate of five types of components, a pillar electrode, a barrier layer, a solder layer, a barrier layer, and a pillar electrode. Compared to the device, it is possible to reduce the size in the thickness direction.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 Semiconductor device, 3 Multi-layer wiring, 4 Second insulating layer, 5 Passion film, 6 1st Ni electrode, 7 Connection layer, 8 Semiconductor layer, 9 2nd Ni electrode, 10 1st substrate, 11 2nd substrate, 30 1st insulation Layer, 31 1st wiring, 32 2nd wiring, 33 3rd wiring, 34 barrier metal film, 40 aluminum pad, 41 barrier metal film, 60 barrier metal film, 61 Cu diffusion area, 61a seed film, 71 Au diffusion area, 72 Support, 80 Protective Membrane, 81 Through Electrode, 82 Barrier Metal Membrane, 90 Barrier Metal Membrane, 91 Cu Diffusion Region, 100 Resist, 101 Opening, 102 Resist, 103 Au Membrane, 104 Au Membrane, 105 Adhesive Resin

Claims (4)

A wiring using copper and tungsten inside, a first substrate having a first semiconductor layer, and
An aluminum pad provided in the surface layer of the first substrate and connected to the wiring, and
A passivation film provided on the surface layer side of the first substrate and covering a part of the aluminum pad,
A first nickel electrode, a part of which is embedded in the passivation film and connected to the aluminum pad, and the top surface of which protrudes from the passivation film.
A first through electrode penetrating the first semiconductor layer and
A first silicon nitride film that covers at least a part of the first semiconductor layer,
A second nickel electrode, a part of which is embedded in the first silicon nitride film and connected to the first through electrode, and a top surface of the part protrudes from the first silicon nitride film.
A second substrate provided with a second semiconductor layer and laminated on the first substrate,
A second through electrode penetrating the second semiconductor layer and
A second silicon nitride film that covers at least a part of the second semiconductor layer,
A third nickel electrode is partially embedded in the second silicon nitride film, and the top surface of the part is projected from the second silicon nitride film.
It is formed of an alloy containing tin and comprises a connecting layer that connects the first nickel electrode and the third nickel electrode.
The first through electrode is electrically connected to the aluminum pad via the wiring and is directly connected to the second nickel electrode.
The second through electrode is a semiconductor device characterized in that it is directly connected to the third nickel electrode. The first nickel electrode has a first barrier metal film using titanium and has a first barrier metal film.
The second nickel electrode has a second barrier metal film using titanium, and has a second barrier metal film.
The third nickel electrode has a third barrier metal film using titanium, and has a third barrier metal film.
The first barrier metal film is in contact with the passivation film and the aluminum pad.
The first nickel electrode contains copper at a portion in contact with the first barrier metal film.
The second barrier metal film is in contact with the first silicon nitride film and the first through electrode.
The second nickel electrode contains copper at a portion in contact with the second barrier metal film.
The third barrier metal film is in contact with the second silicon nitride film and the second through electrode.
The third nickel electrode contains copper at a portion in contact with the third barrier metal film.
The semiconductor device is
A fourth barrier metal film using titanium provided at the interface between the first semiconductor layer and the first through electrode.
A first insulating film provided at a boundary between the first semiconductor layer and the fourth barrier metal film,
A fifth barrier metal film using titanium provided at the interface between the second semiconductor layer and the second through electrode.
A second insulating film provided at the boundary between the second semiconductor layer and the fifth barrier metal film,
The semiconductor device according to claim 1, further comprising. The wiring includes a first wiring and a second wiring connected to the first wiring.
Tungsten is used for the first wiring.
Copper is used for the second wiring.
The first through electrode is connected to the first wiring and is connected to the first wiring.
The semiconductor device according to claim 1 or 2, wherein the aluminum pad is connected to the second wiring. A step of forming an aluminum pad connected to the first wiring in the surface layer of the first substrate having the first semiconductor layer and the first wiring inside.
A step of forming a passivation film covering a part of the aluminum pad on the surface layer side of the first substrate, and
A step of forming an opening extending from the surface of the passivation film to the surface of the aluminum pad, and
A step of forming a barrier metal film with titanium on the inner peripheral surface and the bottom surface of the opening, and
A part is embedded in the opening in which the barrier metal film is formed and connected to the aluminum pad via the barrier metal film to form a first nickel electrode whose top surface projects from the surface of the first substrate. Process and
A step of forming a first silicon nitride film covering the side of the first semiconductor layer opposite to the surface layer, and
A step of exposing the surface from the opening formed in the first silicon nitride film and forming a first through electrode that penetrates the first semiconductor layer and connects to the first wiring.
A step of forming a second nickel electrode in which a part is embedded in the first silicon nitride film and connected to the first through electrode, and the top surface of the part protrudes from the first silicon nitride film.
A step of forming a second silicon nitride film having a second semiconductor layer and a second wiring inside and covering the second semiconductor layer of the second substrate laminated on the first substrate.
A step of exposing the surface from the opening formed in the second silicon nitride film and forming a second through electrode that penetrates the second semiconductor layer and connects to the second wiring.
A step of forming a third nickel electrode in which a part is embedded in the second silicon nitride film and connected to the second through electrode, and the top surface of the part is projected from the second silicon nitride film.
On both or one of the top surface of the first nickel electrode and the top surface of the third nickel electrode,
The process of laminating the connection layer with an alloy containing tin,
A method for manufacturing a semiconductor device, which comprises a step of laminating the second substrate on the first substrate and connecting the first nickel electrode and the third nickel electrode via the connection layer.

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