JPH0653222A - Formation method of bump electrode - Google Patents

Formation method of bump electrode

Info

Publication number
JPH0653222A
JPH0653222A JP20540692A JP20540692A JPH0653222A JP H0653222 A JPH0653222 A JP H0653222A JP 20540692 A JP20540692 A JP 20540692A JP 20540692 A JP20540692 A JP 20540692A JP H0653222 A JPH0653222 A JP H0653222A
Authority
JP
Japan
Prior art keywords
layer
photoresist
metal layer
bump electrode
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20540692A
Other languages
Japanese (ja)
Inventor
Kenichi Takishima
健一 滝島
Masaaki Matsudo
正明 松戸
Shigetoshi Ito
重寿 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP20540692A priority Critical patent/JPH0653222A/en
Publication of JPH0653222A publication Critical patent/JPH0653222A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To achieve that a bump electrode can be formed at a prescribed height without reducing the maximum width of the bump electrode by a method wherein a protrusion-shaped metal layer is covered with a photoresist, the photoresist at the upper part is removed and the head part of the protrusion- shaped metal layer which has been exposed is removed by etching by a definite thickness. CONSTITUTION:A protrusion-shaped metal layer 9 is formed in such a way that it is provider with a support part 9a which is fixed and bonded directly to a semiconductor substrate 1 or fixed and bonded indirectly via conductive layers 2, 5, 6 and that it is provided with a head part 9b formed at the upper part of the support part 9a so as to protrude to the outside from the side part of the support part 9a. Then, the protrusion-shaped metal layer 9 is covered with positive-type photoresists 10, 11, and the photoresists 10, 11 with which the upper part of the head part 9b of the protrusion-shaped metal layer 9 is covered are removed selectively by etching. Then, the head part 9b of the protrusion-shaped metal layer 9 which is exposed from the photoresists 10, 11 is removed by etching by a prescribed thickness. For example, a protrusion- shaped metal layer 9 is formed as a plated layer composed of copper.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はバンプ電極の形成方法に
関連する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump electrode forming method.

【0002】[0002]

【従来の技術】バンプ電極と称する半導体素子の突起状
電極は、絶縁膜に形成された開口を通じて半導体基板に
接続された下地金属層と、この下地金属層の上面に形成
された断面茸形状の中間金属層と、この中間金属層の上
面に半球状に形成された半田層とから構成される。
2. Description of the Related Art A protruding electrode of a semiconductor element called a bump electrode has a base metal layer connected to a semiconductor substrate through an opening formed in an insulating film and a mushroom-shaped cross section formed on the upper surface of the base metal layer. It is composed of an intermediate metal layer and a solder layer formed in a hemispherical shape on the upper surface of the intermediate metal layer.

【0003】[0003]

【発明が解決しようとする課題】ところで、この種のバ
ンプ電極を低い高さで形成する場合、その上部をエッチ
ングで除去すれば良いが、単にエッチングを施すとバン
プ電極の径も小さくなる不都合がある。
By the way, in the case of forming this kind of bump electrode at a low height, the upper portion thereof may be removed by etching, but if etching is simply performed, the diameter of the bump electrode becomes small. is there.

【0004】そこで、本発明ではバンプ電極の最大横幅
が小さくならずに、バンプ電極を所望の高さで形成でき
るバンプ電極の形成方法を提供する。
Therefore, the present invention provides a method of forming bump electrodes which can form bump electrodes at a desired height without reducing the maximum lateral width of the bump electrodes.

【0005】[0005]

【課題を解決するための手段】本発明によるバンプ電極
の形成方法は、半導体基板に直接固着され又は導電層を
介して間接的に固着された支持部及び支持部の側部から
外側に突出して支持部の上部に形成された頭部とを備え
た突起状金属層を形成する工程と、突起状金属層をポジ
形のフォトレジストで被覆する工程と、突起状金属層の
頭部の上部を被覆するフォトレジストをエッチングによ
り選択的に除去する工程と、フォトレジストから露出す
る突起状電極層の頭部を一定厚さだけエッチングにより
除去する工程とを含む。このバンプ電極の形成方法で
は、更に、頭部の上面に選択的に金属膜を形成する工程
を含んでもよい。また、フォトレジストを被覆する工程
は相対的に流動性の高い第1のポジ形フォトレジスト
と、相対的に流動性の低い第2のポジ形フォトレジスト
を第1のフォトレジストの表面に形成する工程とを含ん
でもよい。
SUMMARY OF THE INVENTION A bump electrode forming method according to the present invention comprises a support portion fixed directly to a semiconductor substrate or indirectly fixed via a conductive layer and protruding outward from a side portion of the support portion. A step of forming a protruding metal layer having a head formed on the top of the support, a step of coating the protruding metal layer with a positive photoresist, and an upper part of the head of the protruding metal layer. The method includes a step of selectively removing the photoresist to be coated by etching, and a step of removing the head portion of the protruding electrode layer exposed from the photoresist by a certain thickness by etching. This bump electrode forming method may further include a step of selectively forming a metal film on the upper surface of the head. In the step of coating the photoresist, a first positive photoresist having a relatively high fluidity and a second positive photoresist having a relatively low fluidity are formed on the surface of the first photoresist. And a process may be included.

【0006】[0006]

【作用】突起状金属層の頭部の上部を被覆するフォトレ
ジストをエッチングにより選択的に除去し、残部のフォ
トレジストをマスクにして一定厚さの頭部をエッチング
により除去するので、頭部の最大横幅を実質的に減少さ
せずに頭部の厚みを薄くすることができる。
Function: The photoresist covering the upper part of the head of the protruding metal layer is selectively removed by etching, and the remaining part of the photoresist is used as a mask to remove the head of a certain thickness by etching. The head thickness can be reduced without substantially reducing the maximum lateral width.

【0007】[0007]

【実施例】以下、本発明によるバンプ電極の形成方法の
一実施例を図1〜図10について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bump electrode forming method according to the present invention will be described below with reference to FIGS.

【0008】まず、シリコン(Si)等から成る半導体
基板(ウェハ)(1)の上面全体にアルミニウム(Al)
を真空蒸着した後、これを選択的にエッチングしてバン
プ電極形成予定領域に図1に示す約2μm(マイクロメ
ータ)の厚みを有するアルミニウム層(2)を形成す
る。
First, aluminum (Al) is formed on the entire upper surface of a semiconductor substrate (wafer) (1) made of silicon (Si) or the like.
Is vacuum-deposited, and then selectively etched to form an aluminum layer (2) having a thickness of about 2 μm (micrometer) shown in FIG.

【0009】次に、周知のCVD(Chemical Vapor Dep
osition)法等によって半導体基板(1)の上面全体に二
酸化珪素(SiO2)膜を形成した後、選択的にエッチン
グし、図2に示すように、バンプ電極形成予定領域に開
口(4)を有する絶縁膜(3)を形成する。アルミニウム
層(2)の中心側は開口(4)から露出し、周辺側は絶縁
膜(3)に被覆される。
Next, the well-known CVD (Chemical Vapor Dep
After forming a silicon dioxide (SiO2) film on the entire upper surface of the semiconductor substrate (1) by an osition method or the like, it is selectively etched to have an opening (4) in a bump electrode formation planned region as shown in FIG. An insulating film (3) is formed. The center side of the aluminum layer (2) is exposed from the opening (4) and the peripheral side is covered with the insulating film (3).

【0010】続いて、図3のように、半導体基板(1)
の上面全体にクロム(Cr)と銅(Cu)を連続的に真空
蒸着して約4,500オングストロームの厚さのクロム
層(5)と約3μmの厚さの銅層(6)を形成する。アル
ミニウム層(2)、クロム層(5)及び銅層(6)は導電
層を形成し、クロム層(5)と銅層(6)は中間金属層を
形成する。
Then, as shown in FIG. 3, the semiconductor substrate (1)
Of chromium (Cr) and copper (Cu) are continuously vacuum-deposited on the entire upper surface of the substrate to form a chromium layer (5) having a thickness of about 4,500 Å and a copper layer (6) having a thickness of about 3 μm. . The aluminum layer (2), the chromium layer (5) and the copper layer (6) form a conductive layer, and the chromium layer (5) and the copper layer (6) form an intermediate metal layer.

【0011】更に、銅層(6)の上面全体にフォトレジ
ストを形成してこの一部を選択的にエッチング除去し、
図4に示すように開口(7)を有するフォトレジスト膜
(8)を形成する。銅層(6)の一部は、バンプ電極形成
予定領域に設けられた開口(7)から露出する。続い
て、開口(7)内及びその周辺のフォトレジスト膜(8)
上に厚さ30〜40μmの銅メッキ層(9)を突起状電
極層として形成する。銅メッキ層(9)の断面形状は開
口(7)を通じて銅層(6)に直接接触する支持部(9a)
と、開口(7)の近傍のフォトレジスト膜(8)の上面に
延在する頭部(9b)とを備えた茸形状となる。したがっ
て、銅メッキ層(9)の支持部(9a)は開口(7)内に埋
設され、頭部(9b)は支持部(9a)の側部及び開口
(7)の周縁から外側に張出している。
Further, a photoresist is formed on the entire upper surface of the copper layer (6) and a part of this is selectively removed by etching.
As shown in FIG. 4, a photoresist film (8) having an opening (7) is formed. A part of the copper layer (6) is exposed from the opening (7) provided in the bump electrode formation planned region. Then, the photoresist film (8) in and around the opening (7)
A copper plating layer (9) having a thickness of 30 to 40 μm is formed thereon as a protruding electrode layer. The cross-sectional shape of the copper plating layer (9) has a supporting portion (9a) that directly contacts the copper layer (6) through the opening (7).
And a head portion (9b) extending on the upper surface of the photoresist film (8) near the opening (7). Therefore, the support portion (9a) of the copper plating layer (9) is embedded in the opening (7), and the head portion (9b) extends outward from the side portion of the support portion (9a) and the peripheral edge of the opening (7). There is.

【0012】次に、図4のフォトレジスト膜(8)を除
去した後、半導体基板(1)を所定のエッチング液中に
浸漬させて、図5に示すように銅メッキ層(9)の支持
部(9a)よりも外側に延在したクロム層(5)と銅層
(6)を部分的に除去する。エッチングの際に銅メッキ
層(9)がマスクとなるため、支持部(9a)の下方とそ
の近接部分にクロム層(5a)と銅層(6a)が残存する。
本実施例では、中間金属層を構成するクロム層(5)と
銅層(6)の各周縁部は頭部(9b)より内側に位置す
る。前記エッチング処理では銅メッキ層(9)の表面部
も若干溶融するが、銅メッキ層(9)の径及び厚みはク
ロム層(5)及び銅層(6)に比べて十分に大きいので、
銅メッキ層(9)のエッチングによる影響は無視できる
程度である。
Next, after removing the photoresist film (8) of FIG. 4, the semiconductor substrate (1) is immersed in a predetermined etching solution to support the copper plating layer (9) as shown in FIG. The chromium layer (5) and the copper layer (6) extending outside the portion (9a) are partially removed. Since the copper plating layer (9) serves as a mask during etching, the chromium layer (5a) and the copper layer (6a) remain below the supporting portion (9a) and in the vicinity thereof.
In this embodiment, the respective peripheral portions of the chromium layer (5) and the copper layer (6) forming the intermediate metal layer are located inside the head portion (9b). In the etching treatment, the surface portion of the copper plating layer (9) is also slightly melted, but since the diameter and thickness of the copper plating layer (9) are sufficiently larger than those of the chromium layer (5) and the copper layer (6),
The effect of etching the copper plating layer (9) is negligible.

【0013】次に、図6に示すように、半導体基板
(1)の上面全体に第1のポジ形フォトレジスト(10)
と第2のポジ形フォトレジスト(11)を順次塗布する。
第1のポジ形フォトレジスト(10)と第2のポジ形フォ
トレジスト(11)はいずれも露光領域が現像液に対して
可溶性となるフォトレジストである。銅メッキ層(9)
の頭部(9a)と絶縁膜(3)の対向間隔は数10μmの
幅狭領域Aである。本実施例では、相対的に流動性の高
い第1のポジ形フォトレジスト(10)を幅狭領域Aに充
填した後、相対的に流動性の低い第2のポジ形フォトレ
ジスト(11)を塗布して、大きなレジスト膜厚を確保し
且つ幅狭領域Aにフォトレジストを良好に充填すること
ができる。
Next, as shown in FIG. 6, a first positive photoresist (10) is formed on the entire upper surface of the semiconductor substrate (1).
And a second positive photoresist (11) are sequentially applied.
Both the first positive photoresist (10) and the second positive photoresist (11) are photoresists whose exposed areas are soluble in a developing solution. Copper plating layer (9)
The facing interval between the head portion (9a) and the insulating film (3) is a narrow region A of several tens of μm. In this embodiment, after filling the narrow region A with the first positive photoresist (10) having relatively high fluidity, the second positive photoresist (11) having relatively low fluidity is applied. By coating, a large resist film thickness can be secured and the narrow region A can be filled with the photoresist well.

【0014】図6のように、フォトレジストは頭部(9
b)の外周側で相対的に厚く形成され、頭部(9b)の外
周側から離間するにつれて薄くなる。
As shown in FIG. 6, the photoresist has a head (9
It is formed relatively thick on the outer peripheral side of b) and becomes thinner as it is separated from the outer peripheral side of the head (9b).

【0015】次に、フォトレジスト(10)(11)に対し
て半導体基板(1)の表面に直交する図6の矢印B方向
に紫外線を一定時間照射する。幅狭領域Aに充填された
フォトレジスト(10)(11)には、銅メッキ層(9)の
頭部(9b)が遮光マスクとなり紫外線が照射されない。
したがって、後に現像したとき、フォトレジスト(10)
(11)が感光して、エッチングにより除去されるが、幅
狭領域のフォトレジスト(10)(11)は残存する。ま
た、頭部(9b)の外周側では、フォトレジストが相対的
に厚く形成されるので、適切な露光量と現像時間を選択
すると、図7に示すように頭部(9b)の外周側を覆うよ
うにバンプ電極の周辺側にもフォトレジスト(10)(1
1)が一部残存する。
Next, the photoresists (10) and (11) are irradiated with ultraviolet rays for a certain period of time in the direction of arrow B in FIG. 6 which is orthogonal to the surface of the semiconductor substrate (1). The photoresist (10) (11) filled in the narrow region A is protected from ultraviolet rays by the head portion (9b) of the copper plating layer (9) serving as a light shielding mask.
Therefore, when developed later, photoresist (10)
Although (11) is exposed to light and removed by etching, the photoresists (10) and (11) in the narrow region remain. Further, since the photoresist is formed relatively thick on the outer peripheral side of the head (9b), if an appropriate exposure amount and development time are selected, the outer peripheral side of the head (9b) will be changed as shown in FIG. Photoresist (10) (1) also on the peripheral side of the bump electrode so as to cover it.
1) remains partially.

【0016】次に、残存したフォトレジスト(10)(1
1)をマスクにしてバンプ電極にエッチングを施す。バ
ンプ電極の側面及び頭部(9b)の外周側にフォトレジス
ト(10)(11)が残存しているから、図8のように、バ
ンプ電極の頭部(9b)が縦方向にのみエッチングされ、
頭部(9b)の径(最大横幅)は実質的に小さくならな
い。
Next, the remaining photoresist (10) (1
Using 1) as a mask, the bump electrode is etched. Since the photoresists (10) and (11) remain on the side surface of the bump electrode and the outer peripheral side of the head portion (9b), the head portion (9b) of the bump electrode is etched only in the vertical direction as shown in FIG. ,
The diameter (maximum width) of the head (9b) does not become substantially smaller.

【0017】次に、図8の半導体基板(1)にニッケル
(Ni)メッキを施して、銅メッキ層(9)の頭部(9b)
上面に0.5μm程度の厚みのニッケルメッキ層(12)
を金属膜として形成する。フォトレジスト(10a)(11
a)によって被覆された頭部(9b)の下面、支持部(9
a)、クロム層(5a)及び銅層(6a)の側面にはニッケ
ルメッキ層(12)が形成されない。特に、フォトレジス
ト(10a)(11a)は、クロム層(5a)及び銅層(6a)に
対するニッケルメッキ層(12)の付着を有効に阻止す
る。二酸化珪素からなる絶縁膜(3)は、フォトレジス
ト(10a)(11a)によってニッケルメッキ層(12)に対
して完全に分断され、ニッケルメッキが付着しない。
Next, nickel (Ni) plating is applied to the semiconductor substrate (1) of FIG. 8 to form a head portion (9b) of the copper plating layer (9).
Nickel plating layer (12) with a thickness of about 0.5 μm on the top surface
Is formed as a metal film. Photoresist (10a) (11
The underside of the head (9b) covered by a), the support (9
a), the nickel plating layer (12) is not formed on the side surfaces of the chromium layer (5a) and the copper layer (6a). In particular, the photoresists (10a) (11a) effectively prevent the nickel plating layer (12) from adhering to the chromium layer (5a) and the copper layer (6a). The insulating film (3) made of silicon dioxide is completely separated from the nickel plating layer (12) by the photoresists (10a) (11a), and the nickel plating does not adhere.

【0018】最後に、図10に示すように、ニッケルメ
ッキ層(12)を介して銅メッキ層(9)の上面にメッキ
等によって選択的に半田を付着させて、鉛(Pb)と錫
(Sn)を成分とする半球状の半田層(13)を形成し、
バンプ電極を完成する。ニッケルメッキ層(12)の厚み
は、機械的応力の低減のために1μm以下が望ましい
が、銅メッキ層(9)と半田層(13)間の金属成分の相
互拡散を十分に抑制するため、0.3μm以上が良い。
Finally, as shown in FIG. 10, solder is selectively adhered to the upper surface of the copper plating layer (9) through the nickel plating layer (12) by plating or the like to obtain lead (Pb) and tin (Pb). Forming a hemispherical solder layer (13) containing Sn) as a component,
Complete the bump electrodes. The thickness of the nickel plating layer (12) is preferably 1 μm or less in order to reduce mechanical stress, but in order to sufficiently suppress mutual diffusion of metal components between the copper plating layer (9) and the solder layer (13), 0.3 μm or more is preferable.

【0019】本実施例によって形成されたバンプ電極に
よれば以下の効果が得られる。
According to the bump electrode formed in this embodiment, the following effects can be obtained.

【0020】(1) フォトレジスト(10)(11)によっ
て、パンプ電極の径方向のエッチングを抑制して、バン
プ電極の径を減少させずに低い高さで形成することがで
きる。
(1) The photoresists (10) and (11) can suppress the etching of the bump electrode in the radial direction, and can form the bump electrode at a low height without reducing the diameter.

【0021】(2) 銅メッキ層(9)と半田層(13)との
間にニッケルメッキ層(12)が介在するので、銅メッキ
層(9)の銅と半田層(13)の鉛又は錫の相互拡散が抑
制され、合金層成長に伴うバンプ電極の層間剥離を防止
できる。
(2) Since the nickel plating layer (12) is interposed between the copper plating layer (9) and the solder layer (13), copper of the copper plating layer (9) and lead of the solder layer (13) or Mutual diffusion of tin is suppressed, and delamination of the bump electrodes due to alloy layer growth can be prevented.

【0022】(3) 銅メッキ層(9)の上面にのみニッケ
ルメッキ層(12)を形成するので、ニッケルメッキ層
(12)の膨張率の差異等に起因する機械的応力による影
響を絶縁膜(3)及び半導体基板(1)に与えない。
(3) Since the nickel plating layer (12) is formed only on the upper surface of the copper plating layer (9), the influence of mechanical stress caused by the difference in the expansion coefficient of the nickel plating layer (12) and the like is prevented from occurring in the insulating film. Do not apply to (3) and semiconductor substrate (1).

【0023】本発明の実施態様は前記の実施例に限定さ
れず、更に変更が可能である。例えば、電力用ショット
キバリアダイオード及びその他の半導体装置に本発明を
適用することが可能である。また、アルミニウム層
(2)、クロム層(5)及び銅層(6)により導電層を構
成したが、導電層を省略して銅メッキ層(9)を半導体
基板(1)に直接固着したり、所望数の層を介して銅メ
ッキ層(9)を半導体基板(1)に固着することができ
る。更に、突起状電極層として銅メッキ層(9)を形成
する例を示したが、アルミニウム等他の金属のメッキ層
でもよい。
The embodiment of the present invention is not limited to the above embodiment, and can be modified. For example, the present invention can be applied to a power Schottky barrier diode and other semiconductor devices. Further, although the conductive layer is composed of the aluminum layer (2), the chromium layer (5) and the copper layer (6), the conductive layer may be omitted and the copper plating layer (9) may be directly fixed to the semiconductor substrate (1). The copper plating layer (9) can be fixed to the semiconductor substrate (1) through a desired number of layers. Furthermore, although the example in which the copper plating layer (9) is formed as the protruding electrode layer is shown, a plating layer of another metal such as aluminum may be used.

【0024】[0024]

【発明の効果】前述のように、本発明では、バンプ電極
の最大横幅を減少させずに、バンプ電極の高さを低くす
ることができる。
As described above, according to the present invention, the height of the bump electrode can be lowered without reducing the maximum lateral width of the bump electrode.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明によるバンプ電極の形成方法に使用す
る半導体基板にアルミニウム層を形成した状態を示す断
面図
FIG. 1 is a cross-sectional view showing a state in which an aluminum layer is formed on a semiconductor substrate used in the method for forming bump electrodes according to the present invention.

【図2】 図1において絶縁層を形成した状態を示す断
面図
FIG. 2 is a sectional view showing a state in which an insulating layer is formed in FIG.

【図3】 図2において中間金属層を形成した状態を示
す断面図
FIG. 3 is a cross-sectional view showing a state in which an intermediate metal layer is formed in FIG.

【図4】 図3において銅メッキ層を突起状電極層とし
て形成した状態を示す断面図
FIG. 4 is a cross-sectional view showing a state in which a copper plating layer is formed as a protruding electrode layer in FIG.

【図5】 図4において中間金属層の周縁部をエッチン
グ除去した状態を示す断面図
FIG. 5 is a cross-sectional view showing a state in which the peripheral edge portion of the intermediate metal layer is removed by etching in FIG.

【図6】 図5においてフォトレジストを塗布した状態
を示す断面図
FIG. 6 is a cross-sectional view showing a state in which a photoresist is applied in FIG.

【図7】 図6において紫外線の照射後、突起状電極層
の周囲のフォトレジストを除去した状態を示す断面図
FIG. 7 is a cross-sectional view showing a state in which the photoresist around the protruding electrode layer has been removed after irradiation with ultraviolet rays in FIG.

【図8】 突起状金属の頭部の上面をエッチング除去し
た状態を示す断面図
FIG. 8 is a cross-sectional view showing a state in which the upper surface of the protruding metal head is removed by etching.

【図9】 エッチング除去した突起状金属の上面にニッ
ケルメッキ層を形成した状態を示す断面図
FIG. 9 is a cross-sectional view showing a state where a nickel plating layer is formed on the upper surface of the protruding metal removed by etching.

【図10】 ニッケルメッキ層の上に半田層を形成した
状態を示す断面図
FIG. 10 is a sectional view showing a state in which a solder layer is formed on a nickel plating layer.

【符号の説明】[Explanation of symbols]

(1)...半導体基板、 (2)...アルミニウム
層、(3)...絶縁層、(4)...開口、
(5)...クロム層(導電層)、(6)...銅層(導
電層)、(7)...開口、(8)...フォトレジスト
膜、(9)...銅メッキ層、(9a)...支持部、(9
b)...頭部、(10)、(11)...フォトレジス
ト、(12)...ニッケルメッキ層(金属膜)、(1
3)...半田層、
(1). . . Semiconductor substrate, (2). . . An aluminum layer, (3). . . Insulating layer, (4). . . Opening,
(Five). . . Chrome layer (conductive layer), (6). . . Copper layer (conductive layer), (7). . . Opening, (8). . . Photoresist film, (9). . . Copper plating layer, (9a). . . Support, (9
b). . . Head, (10), (11). . . Photoresist, (12). . . Nickel plating layer (metal film), (1
3). . . Solder layer,

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板に直接固着され又は導電層を
介して間接的に固着された支持部及び該支持部の側部か
ら外側に突出して前記支持部の上部に形成された頭部と
を備えた突起状金属層を形成する工程と、 前記突起状金属層をポジ形のフォトレジストで被覆する
工程と、 前記突起状金属層の頭部の上部を被覆するフォトレジス
トをエッチングにより選択的に除去する工程と、 前記フォトレジストから露出する前記突起状電極層の頭
部を一定厚さだけエッチングにより除去する工程と、 を含むことを特徴とするバンプ電極の形成方法。
1. A support portion directly fixed to a semiconductor substrate or indirectly fixed via a conductive layer, and a head portion protruding outward from a side portion of the support portion and formed on an upper portion of the support portion. A step of forming a protruding metal layer provided, a step of coating the protruding metal layer with a positive photoresist, and selectively etching the photoresist covering the top of the head of the protruding metal layer by etching. A method of forming a bump electrode, comprising: a step of removing; and a step of removing a head portion of the protruding electrode layer exposed from the photoresist by a predetermined thickness by etching.
【請求項2】 更に、前記頭部の上面に選択的に金属膜
を形成する工程を含む「請求項1」に記載のバンプ電極
の形成方法。
2. The bump electrode forming method according to claim 1, further comprising the step of selectively forming a metal film on the upper surface of the head.
【請求項3】 前記フォトレジストを被覆する工程は相
対的に流動性の高い第1のポジ形フォトレジストと、相
対的に流動性の低い第2のポジ形フォトレジストを前記
第1のフォトレジストの表面に形成する工程とを含む
「請求項1」に記載のバンプ電極の形成方法。
3. The step of coating the photoresist comprises applying a first positive photoresist having a relatively high fluidity and a second positive photoresist having a relatively low fluidity to the first photoresist. The method of forming a bump electrode according to claim 1, further comprising the step of forming the bump electrode on the surface of the bump electrode.
JP20540692A 1992-07-31 1992-07-31 Formation method of bump electrode Pending JPH0653222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20540692A JPH0653222A (en) 1992-07-31 1992-07-31 Formation method of bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20540692A JPH0653222A (en) 1992-07-31 1992-07-31 Formation method of bump electrode

Publications (1)

Publication Number Publication Date
JPH0653222A true JPH0653222A (en) 1994-02-25

Family

ID=16506316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20540692A Pending JPH0653222A (en) 1992-07-31 1992-07-31 Formation method of bump electrode

Country Status (1)

Country Link
JP (1) JPH0653222A (en)

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