JPH05144823A - High density bump forming method - Google Patents

High density bump forming method

Info

Publication number
JPH05144823A
JPH05144823A JP3326886A JP32688691A JPH05144823A JP H05144823 A JPH05144823 A JP H05144823A JP 3326886 A JP3326886 A JP 3326886A JP 32688691 A JP32688691 A JP 32688691A JP H05144823 A JPH05144823 A JP H05144823A
Authority
JP
Japan
Prior art keywords
forming method
bump
wafer
bump forming
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3326886A
Other languages
Japanese (ja)
Inventor
Hiroshi Yanagihara
浩 柳原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
Original Assignee
Tanaka Kikinzoku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Kikinzoku Kogyo KK filed Critical Tanaka Kikinzoku Kogyo KK
Priority to JP3326886A priority Critical patent/JPH05144823A/en
Publication of JPH05144823A publication Critical patent/JPH05144823A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

PURPOSE:To easily form the bump of a conductive circuit in high density by a technique in which a sleeper-like cushion part is formed using photosensitive polyimide in the vicinity of a plurality of pad parts, and a conductive circuit is formed on the region ranging from the surface of each pad part to the surface of a cushion part. CONSTITUTION:A bump height cushion part 6, having sleeper-like cross section, is formed of photosensitive polyimide in the vicinity of the outside or inside of a plurality of pad parts 3 which are arranged on the circumference of each chip 2 on a wafer 1. Then, after a conductive film has been formed on the whole surface of the wafer 1 by sputtering, a bump 11 is obtained by forming a conductive circuit 10 on the region from the surface of each pad part 3 to the surface of the cushion part 6 by conducting a photo process and an etching treatment on the conductive film. After formation of a cushion part 6 of 20mum in height and 100mum in width, for example, a conductive film is formed by sputtering Ti of 1000Angstrom , Pd of 3000Angstrom and Au of 30002r, and a conductive circuit 10 is formed by patterning the above-mentioned conductive film, and a bump 11 is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、LSI等の半導体素子
を、プリント基板に実装する為に、TAB、フリップチ
ップ方式におけるバンプをウェハー上に高密度に形成す
る方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming bumps in a TAB or flip-chip method on a wafer at a high density for mounting a semiconductor element such as an LSI on a printed board.

【0002】[0002]

【従来の技術】従来、バンプをウェハー上に形成するに
は、完成後の半導体素子からなるウェハー上の各チップ
の周辺に配設された電気的接続部であるパッド上に、密
着力保持、金属間の拡散防止等の目的のバリヤーメタル
層を形成し、そのバリヤーメタル層の上に電解メッキ法
によりAu、Pb−Sn、Cu等のメタルバンプを形成
していた。
2. Description of the Related Art Conventionally, in order to form bumps on a wafer, adhesion is maintained on a pad, which is an electrical connection portion arranged around each chip on a wafer composed of completed semiconductor elements, A barrier metal layer for the purpose of preventing diffusion between metals is formed, and metal bumps of Au, Pb-Sn, Cu or the like are formed on the barrier metal layer by electrolytic plating.

【0003】他にガラス基板等に、予めメタルバンプを
形成し、これをTABテープに写す方法もあった。ま
た、ストレートバンプの形成方法として、バンプ高さ以
上の厚膜レジストをウェハー上にコーティングし、露
光、現像工程で凹パターンを形成する方法もあった。こ
れら従来のバンプ形成方法で、高密度のバンプを形成し
ようとすると、バンプサイズの微小化、狭ピッチ化を進
めることになる。しかし、従来のバンプ形成方法では、
メッキ用レジストの形成工程において、例えば幅20μ
m、深さ25μmの凹部を形成すること及び隣りの凹部と
の壁の厚みを10μmに形成することは不可能で、幅50μ
m、深さ25μm、ピッチ80μmが限界で、今後要求され
るバンプの高密度化への対応ができない。
Another method is to previously form metal bumps on a glass substrate or the like and copy them onto a TAB tape. Further, as a method of forming a straight bump, there is also a method of coating a thick film resist having a bump height or more on a wafer and forming a concave pattern in the exposure and development steps. If high-density bumps are to be formed by these conventional bump forming methods, the bump size will be made smaller and the pitch will be made narrower. However, in the conventional bump forming method,
In the plating resist formation process, for example, a width of 20μ
It is impossible to form a recess with a depth of 25 m and a depth of 25 μm and to form a wall with the adjacent recess to a thickness of 10 μm.
m, depth 25 μm, pitch 80 μm are the limits, and we cannot meet the demand for higher density bumps in the future.

【0004】[0004]

【発明が解決しようとする課題】そこで本発明は、ウェ
ハー上のパッド部に導電回路のバンプを高密度に形成す
る方法を提供しようとするものである。
Therefore, the present invention is intended to provide a method for forming conductive circuit bumps at a high density on a pad portion on a wafer.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
の本発明の高密度バンプ形成方法は、ウェハー上の各チ
ップの周辺に配設された多数のパッド部の外側又は内側
付近に、感光性ポリイミドにより断面枕木状のバンプ高
さのクッション部を形成し、次にウェハー全面にスパッ
タリングにより導電膜を形成し、然る後この導電膜をフ
ォトプロセス、エッチングして各パッド部の表面からク
ッション部の表面まで導電回路を形成してバンプを得る
ことを特徴とするものである。
A high density bump forming method of the present invention for solving the above problems is to expose a plurality of pads arranged around each chip on a wafer to the outside or inside of a plurality of pads. Cushion part with cross-section sleeper-shaped bump height is formed with a conductive polyimide, and then a conductive film is formed on the entire surface of the wafer by sputtering, and then this conductive film is photoprocessed and etched to form a cushion from the surface of each pad part. A bump is obtained by forming a conductive circuit up to the surface of the portion.

【0006】[0006]

【作用】上記のように本発明の高密度バンプ形成方法で
は、多数のパッド部の外側又は内側付近に、感光性ポリ
イミドにより断面枕木状のバンプ高さのクッション部を
形成するので、このクッション部はなだらかであり、次
にウェハー全面にスパッタリングにより導電膜を形成し
た際、下地に対する追従性が良く、クッション部に良好
に密着する。また、この導電膜をフォトプロセス、エッ
チングして各パッド部の表面からクッション部の表面ま
で導電回路に形成するのであるから、この導電回路のバ
ンプは、通常の薄い感光性レジストを用いる技術で高密
度化できる。しかも湿式メッキを行わないので、バンプ
のばらつきが少なく、しかも工程が短縮されて能率良く
安価にバンプを形成できる。
As described above, in the high-density bump forming method of the present invention, since a cushion portion having a cross-section sleeper-like bump height is formed of photosensitive polyimide on the outside or inside of a large number of pad portions, this cushion portion is formed. When the conductive film is formed on the entire surface of the wafer by sputtering, it follows the underlying layer well and adheres well to the cushion portion. Further, since the conductive film is photoprocessed and etched to form a conductive circuit from the surface of each pad portion to the surface of the cushion portion, the bumps of the conductive circuit are formed by a technique using a normal thin photosensitive resist. Can be densified. Moreover, since wet plating is not performed, there is little variation in bumps, and the steps can be shortened to efficiently and inexpensively form bumps.

【0007】[0007]

【実施例】本発明の高密度バンプ形成方法の一実施例を
図によって説明すると、図1に示すようにシリコンウェ
ハー1の各チップ2の周辺にAl−Si1wt%のパッド
部(LSI回路の終端電気的接続部)3が多数設けられ
ている。このシリコンウェハー1上に図2に示すように
感光性ポリイミド4を40μmスピンコートし、次に図3
に示すように各チップ2の周辺のパッド部3を、透明石
英ガラス板にCrによりパターンを形成したマスク・パ
ターン5にてマスキングし、図4に示すように紫外線ラ
ンプによりUV光を照射して露光した後、図5に示すよ
うに現像し、次いでN2 雰囲気中で1時間焼成(キュ
ア)して図6に示すように収縮により高さ20μm、幅 1
00μmとなった断面枕木状のクッション部6を形成し
た。次にウェハー1全面にTi1000Å、Pd3000Å、A
u3000Åをスパッタリングして図7に示すように導電膜
7を形成した。次いでこの導電膜7上に図8に示すよう
にフォトレジスト8を 1.3μmスピンコートし、次に図
9に示すように各パッド部3からクッション部6の表面
まで、透明石英ガラス板にCrによりパターンを形成し
たマスクパターン9にてマスキングし、紫外線ランプに
よりUV光を照射して露光した後、図10に示すように現
像し、次いでエッチングして不要部の導電膜7を図11に
示すように除去し、然る後図12に示すようにレジスト8
を剥離し、各パッド部3の表面からクッション部6の表
面まで導電回路10を形成してバンプ11を得た。こうして
得たバンプ11のチップ2における配列、形状は図13に示
す通りである。尚、図13中の区画線lはウェハー1にお
けるチップ2の切断線である。このようにしてウェハー
1上の各チップの周辺のパッド部3に形成したバンプ11
は、幅25μm、高さ20.7μm、ピッチ40μmで、高密度
化できた。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A high density bump forming method according to an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a pad portion (an end of an LSI circuit) of Al-Si 1 wt% is provided around each chip 2 of a silicon wafer 1. A large number of electrical connection parts 3 are provided. As shown in FIG. 2, photosensitive polyimide 4 was spin-coated on this silicon wafer 1 by 40 μm, and then, as shown in FIG.
As shown in FIG. 4, the pad portion 3 around each chip 2 is masked by a mask pattern 5 in which a pattern is formed on the transparent quartz glass plate by Cr, and UV light is irradiated by an ultraviolet lamp as shown in FIG. After exposure, it was developed as shown in FIG. 5 and then baked (cured) in an N 2 atmosphere for 1 hour and contracted to a height of 20 μm and a width of 1 as shown in FIG.
A cushion section 6 having a sleeper shape with a cross section of 00 μm was formed. Next, Ti1000Å, Pd3000Å, A on the entire surface of wafer 1.
u3000Å was sputtered to form a conductive film 7 as shown in FIG. Next, as shown in FIG. 8, a photoresist 8 is spin-coated on the conductive film 7 by 1.3 μm, and then, as shown in FIG. 9, from the respective pad portions 3 to the surface of the cushion portion 6, a transparent quartz glass plate is coated with Cr. After masking with a mask pattern 9 on which a pattern has been formed, exposing by irradiating UV light with an ultraviolet lamp, developing is performed as shown in FIG. 10, and then etching is performed to remove unnecessary portions of the conductive film 7 as shown in FIG. And then remove the resist 8 as shown in FIG.
Then, the conductive circuit 10 was formed from the surface of each pad portion 3 to the surface of the cushion portion 6 to obtain bumps 11. The arrangement and shape of the bumps 11 thus obtained on the chip 2 are as shown in FIG. A partition line 1 in FIG. 13 is a cutting line of the chip 2 on the wafer 1. The bumps 11 thus formed on the pad portion 3 around each chip on the wafer 1
With a width of 25 μm, a height of 20.7 μm and a pitch of 40 μm, it was possible to increase the density.

【0008】一方、従来のバンプ形成方法を図によって
説明すると、図1に示すように多数のチップ2の周辺に
夫々Al−Si1wt%のパッド部3が設けられているシ
リコンウェハー1の全面に、図14に示すようにTi1000
Å、Pd3000Å、Au3000Åをスパッタリングしてバリ
ヤーメタル層12を形成した。次にその上に図15に示すよ
うに感光性レジスト13を25μmスピンコートし、パッド
部3のみを開口させるようにフォトリソグラフにより図
16に示すように感光性レジスト13をパターニングした。
次いで図17に示すようにバリヤーメタル層12をメッキ用
電極として湿式メッキ法により開口部に20μm厚のAu
バンプ14を形成した。次に図18に示すように感光性レジ
スト13を剥離し、図19に示すように全面に感光性レジス
ト15を塗布し、Auバンプ14を被うようにフォトリソグ
ラフにより図20に示すように感光性レジスト15をパター
ニングした。次いでパターニングされた感光性レジスト
15をマスクに、バリヤーメタル層12を図21に示すように
エッチングした。然る後Auバンプ14を被っていた感光
性レジスト15を剥離して図22に示すようにAuバンプ14
の形成を完了させた。このAuバンプ14のチップ2に於
ける配列、形状は図23に示す通りである。尚、図23中の
区画線lはウェハー1におけるチップ2の切断線であ
る。
On the other hand, a conventional bump forming method will be described with reference to the drawings. As shown in FIG. 1, the entire surface of a silicon wafer 1 on which a plurality of chips 2 are provided with pad portions 3 of Al-Si 1 wt% respectively. As shown in Figure 14, Ti1000
Barrier metal layer 12 was formed by sputtering Å, Pd3000Å and Au3000Å. Next, as shown in FIG. 15, a photosensitive resist 13 is spin-coated on it to a thickness of 25 μm, and a photolithographic process is performed so that only the pad portion 3 is opened.
The photosensitive resist 13 was patterned as shown in 16.
Then, as shown in FIG. 17, the barrier metal layer 12 is used as a plating electrode to form an Au film having a thickness of 20 μm in the opening by a wet plating method.
The bump 14 was formed. Next, as shown in FIG. 18, the photosensitive resist 13 is peeled off, the entire surface is coated with the photosensitive resist 15 as shown in FIG. 19, and the Au bumps 14 are covered by photolithography as shown in FIG. The resist 15 was patterned. Then patterned photosensitive resist
The barrier metal layer 12 was etched using 15 as a mask as shown in FIG. After that, the photosensitive resist 15 covering the Au bumps 14 is peeled off to remove the Au bumps 14 as shown in FIG.
Formation was completed. The arrangement and shape of the Au bumps 14 on the chip 2 are as shown in FIG. The partition line 1 in FIG. 23 is a cutting line of the chip 2 on the wafer 1.

【0009】このようにしてウェハー1上の各周辺のパ
ッド部3上に形成したバンプ14は、幅50μm、高さ20.7
μm、ピッチ80μmが限界で、これ以下にバンプサイズ
の微小化、狭ピッチ化は不可能であった。
The bumps 14 thus formed on the peripheral pad portions 3 on the wafer 1 have a width of 50 μm and a height of 20.7.
The limit is μm and the pitch is 80 μm, and it is impossible to make the bump size smaller and the pitch smaller than this.

【0010】尚、前記実施例では各チップ2の周辺のパ
ッド部3の外側にクッション部6を形成したが、パッド
部3の内側に形成しても良いものである。また前記実施
例ではクッション部6がパッド部3の外周側で連続して
いるが、各パッド部3毎に外側又は内側で独立していて
も良いものである。
Although the cushion portion 6 is formed outside the pad portion 3 around each chip 2 in the above embodiment, it may be formed inside the pad portion 3. Further, although the cushion portion 6 is continuous on the outer peripheral side of the pad portion 3 in the above-described embodiment, it may be independent on the outer side or the inner side of each pad portion 3.

【0011】[0011]

【発明の効果】以上の説明で判るように本発明の高密度
バンプ形成方法によると、通常の薄い感光性レジストを
用いる技術で導電回路のバンプを容易に高密度に形成で
きる。また湿式メッキ工程が無いので、バンプのばらつ
きが少なく、しかも工程が短縮されて能率良く且つ安価
にバンプを形成できる。さらに導電回路の下側にクッシ
ョン部を形成しているので、弾性変形が可能で、ガラス
エポキシのプリント基板に半導体素子からなるウェハー
のチップを実装した後熱膨張、収縮に伴う歪の吸収が可
能で、剪断による破断も抑制でき、長寿命化を達成でき
るバンプを得ることができる。
As can be seen from the above description, according to the method for forming high density bumps of the present invention, the bumps of the conductive circuit can be easily formed in high density by the usual technique using a thin photosensitive resist. Further, since there is no wet plating process, there is little variation in bumps, and the process can be shortened to form bumps efficiently and at low cost. Furthermore, since the cushion part is formed on the lower side of the conductive circuit, elastic deformation is possible, and after mounting the chip of the wafer consisting of semiconductor elements on the glass epoxy printed circuit board, it is possible to absorb the strain due to thermal expansion and contraction. Thus, it is possible to suppress the breakage due to shearing and obtain a bump that can achieve a long life.

【図面の簡単な説明】[Brief description of drawings]

【図1】各チップの周辺にパッド部が多数設けられたシ
リコンウェハーを示す斜視図である。
FIG. 1 is a perspective view showing a silicon wafer in which a large number of pad portions are provided around each chip.

【図2】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 2 is a diagram showing a process of an embodiment of a high density bump forming method of the present invention.

【図3】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 3 is a diagram showing a process of an embodiment of the high-density bump forming method of the present invention.

【図4】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 4 is a diagram showing a process of an embodiment of the high-density bump forming method of the present invention.

【図5】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 5 is a diagram showing the steps of an embodiment of the high-density bump forming method of the present invention.

【図6】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 6 is a diagram showing a process of an embodiment of the high-density bump forming method of the present invention.

【図7】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 7 is a diagram showing steps of an embodiment of the high-density bump forming method of the present invention.

【図8】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 8 is a diagram showing a process of an embodiment of the high-density bump forming method of the present invention.

【図9】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 9 is a diagram showing steps of an embodiment of the high-density bump forming method of the present invention.

【図10】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 10 is a diagram showing steps of an embodiment of the high-density bump forming method of the present invention.

【図11】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 11 is a diagram showing a process of an embodiment of the high-density bump forming method of the present invention.

【図12】本発明の高密度バンプ形成方法の一実施例の工
程を示す図である。
FIG. 12 is a diagram showing steps of an embodiment of the high-density bump forming method of the present invention.

【図13】本発明の高密度バンプ形成方法によって得られ
たバンプのシリコンウェハーのチップにおける配列、形
状を示す斜視図である。
FIG. 13 is a perspective view showing the arrangement and shape of bumps obtained by the high-density bump forming method of the present invention on a chip of a silicon wafer.

【図14】従来のバンプ形成方法の工程を示す図である。FIG. 14 is a diagram showing steps of a conventional bump forming method.

【図15】従来のバンプ形成方法の工程を示す図である。FIG. 15 is a diagram showing steps of a conventional bump forming method.

【図16】従来のバンプ形成方法の工程を示す図である。FIG. 16 is a diagram showing steps of a conventional bump forming method.

【図17】従来のバンプ形成方法の工程を示す図である。FIG. 17 is a diagram showing steps of a conventional bump forming method.

【図18】従来のバンプ形成方法の工程を示す図である。FIG. 18 is a diagram showing steps of a conventional bump forming method.

【図19】従来のバンプ形成方法の工程を示す図である。FIG. 19 is a diagram showing steps of a conventional bump forming method.

【図20】従来のバンプ形成方法の工程を示す図である。FIG. 20 is a diagram showing steps of a conventional bump forming method.

【図21】従来のバンプ形成方法の工程を示す図である。FIG. 21 is a diagram showing steps of a conventional bump forming method.

【図22】従来のバンプ形成方法の工程を示す図である。FIG. 22 is a diagram showing steps of a conventional bump forming method.

【図23】従来のバンプ形成方法によって得られたバンプ
のシリコンウェハーのチップにおける配列、形状を示す
斜視図である。
FIG. 23 is a perspective view showing an arrangement and shape of bumps obtained by a conventional bump forming method on a chip of a silicon wafer.

【符号の説明】[Explanation of symbols]

1 ウェハー 2 チップ 3 パッド部 4 感光性ポリイミド 5 マスク・パターン 6 クッション部 7 導電膜 8 フォトレジスト 9 マスクパターン 10 導電回路 11 バンプ 1 Wafer 2 Chip 3 Pad Part 4 Photosensitive Polyimide 5 Mask Pattern 6 Cushion Part 7 Conductive Film 8 Photoresist 9 Mask Pattern 10 Conductive Circuit 11 Bump

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ウェハー上の各チップの周辺に配設され
た多数のパッド部の外側又は内側付近に、感光性ポリイ
ミドにより断面枕木状のバンプ高さのクッション部を形
成し、次にウェハー全面にスパッタリングにより導電膜
を形成し、然る後この導電膜をフォトプロセス、エッチ
ングして各パッド部の表面からクッション部の表面まで
導電回路を形成してバンプを得ることを特徴とする高密
度バンプ形成方法。
1. A cushion portion having a cross-section sleeper-like bump height is formed of a photosensitive polyimide on the outside or inside of a large number of pads arranged around each chip on the wafer, and then the entire surface of the wafer is formed. A high-density bump characterized in that a conductive film is formed by sputtering on the film, and then the conductive film is photoprocessed and etched to form a conductive circuit from the surface of each pad portion to the surface of the cushion portion to obtain a bump. Forming method.
JP3326886A 1991-11-15 1991-11-15 High density bump forming method Pending JPH05144823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3326886A JPH05144823A (en) 1991-11-15 1991-11-15 High density bump forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3326886A JPH05144823A (en) 1991-11-15 1991-11-15 High density bump forming method

Publications (1)

Publication Number Publication Date
JPH05144823A true JPH05144823A (en) 1993-06-11

Family

ID=18192846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3326886A Pending JPH05144823A (en) 1991-11-15 1991-11-15 High density bump forming method

Country Status (1)

Country Link
JP (1) JPH05144823A (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0689240A1 (en) * 1994-05-06 1995-12-27 Industrial Technology Research Institute Bonded structure and methods for forming this structure
US5668410A (en) * 1994-01-31 1997-09-16 Casio Computer Co., Ltd. Projecting electrode structure having a double-layer conductive layer
US5707902A (en) * 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
WO1998052225A1 (en) * 1997-05-13 1998-11-19 Chipscale, Inc. An electronic component package with posts on the active surface
US5874782A (en) * 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
US6414585B1 (en) 1997-05-13 2002-07-02 Chipscale, Inc. Integrated passive components and package with posts
DE10126296A1 (en) * 2001-05-30 2002-12-12 Infineon Technologies Ag Production of an electronic component, especially a chip, mounted on a support comprises spraying or casting an elastic material using a spray or casting mold to form elastic material
US6555415B2 (en) 1999-06-17 2003-04-29 Infineon Technologies Ag Electronic configuration with flexible bonding pads
US6936928B2 (en) 2000-03-23 2005-08-30 Infineon Technologies Ag Semiconductor component and method for its production
JP2006098637A (en) * 2004-09-29 2006-04-13 Seiko Epson Corp Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus
JP2007059514A (en) * 2005-08-23 2007-03-08 Seiko Epson Corp Semiconductor device
DE102005056569A1 (en) * 2005-11-25 2007-06-06 Infineon Technologies Ag Interconnection for flip-chip in package constructions
JP2007149865A (en) * 2005-11-25 2007-06-14 Seiko Epson Corp Semiconductor device and method of manufacturing electronic apparatus
DE10045043B4 (en) * 1999-09-13 2008-01-10 Sharp K.K. Semiconductor component and method for its production
US7462940B2 (en) * 2006-01-11 2008-12-09 Infineon Technologies Ag Semiconductor component comprising flip chip contacts with polymer cores and method of producing the same
US7576424B2 (en) 2005-08-03 2009-08-18 Seiko Epson Corporation Semiconductor device

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668410A (en) * 1994-01-31 1997-09-16 Casio Computer Co., Ltd. Projecting electrode structure having a double-layer conductive layer
EP0689240A1 (en) * 1994-05-06 1995-12-27 Industrial Technology Research Institute Bonded structure and methods for forming this structure
US5707902A (en) * 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
US5874782A (en) * 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
US6051489A (en) * 1997-05-13 2000-04-18 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
GB2341277A (en) * 1997-05-13 2000-03-08 Chipscale Inc An electronic component package with posts on the active surface
US6954130B2 (en) 1997-05-13 2005-10-11 Chipscale, Inc. Integrated passive components and package with posts
US6414585B1 (en) 1997-05-13 2002-07-02 Chipscale, Inc. Integrated passive components and package with posts
GB2341277B (en) * 1997-05-13 2002-08-21 Chipscale Inc An electronic component package with posts on the active surface
US6833986B2 (en) 1997-05-13 2004-12-21 Chipscale, Inc. Integrated passive components and package with posts
WO1998052225A1 (en) * 1997-05-13 1998-11-19 Chipscale, Inc. An electronic component package with posts on the active surface
US6946734B2 (en) 1997-05-13 2005-09-20 Chipscale, Inc. Integrated passive components and package with posts
US6555415B2 (en) 1999-06-17 2003-04-29 Infineon Technologies Ag Electronic configuration with flexible bonding pads
DE10045043B4 (en) * 1999-09-13 2008-01-10 Sharp K.K. Semiconductor component and method for its production
US6936928B2 (en) 2000-03-23 2005-08-30 Infineon Technologies Ag Semiconductor component and method for its production
DE10126296A1 (en) * 2001-05-30 2002-12-12 Infineon Technologies Ag Production of an electronic component, especially a chip, mounted on a support comprises spraying or casting an elastic material using a spray or casting mold to form elastic material
DE10126296B4 (en) * 2001-05-30 2008-04-17 Qimonda Ag Method for producing an electronic component
JP2006098637A (en) * 2004-09-29 2006-04-13 Seiko Epson Corp Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus
JP4539268B2 (en) * 2004-09-29 2010-09-08 セイコーエプソン株式会社 Mounting structure
US7576424B2 (en) 2005-08-03 2009-08-18 Seiko Epson Corporation Semiconductor device
JP2007059514A (en) * 2005-08-23 2007-03-08 Seiko Epson Corp Semiconductor device
DE102005056569A1 (en) * 2005-11-25 2007-06-06 Infineon Technologies Ag Interconnection for flip-chip in package constructions
JP2007149865A (en) * 2005-11-25 2007-06-14 Seiko Epson Corp Semiconductor device and method of manufacturing electronic apparatus
DE102005056569B4 (en) * 2005-11-25 2008-01-10 Qimonda Ag Interconnection for flip-chip in package constructions
US7462940B2 (en) * 2006-01-11 2008-12-09 Infineon Technologies Ag Semiconductor component comprising flip chip contacts with polymer cores and method of producing the same

Similar Documents

Publication Publication Date Title
JPH05144823A (en) High density bump forming method
US5935763A (en) Self-aligned pattern over a reflective layer
US4293637A (en) Method of making metal electrode of semiconductor device
KR960016007B1 (en) Manufacturing method of semiconductor chip bump
JP3258740B2 (en) Method for manufacturing semiconductor device having bump electrode
TWI239608B (en) Semiconductor device and the manufacturing method thereof, and semiconductor wafer
US5200300A (en) Methods for forming high density multi-chip carriers
KR100432794B1 (en) Process for the formation of wiring pattern
JP2806370B2 (en) Pattern formation method
JP2001156093A (en) Manufacturing method for semiconductor device
JPH0298139A (en) Formation of gold bump
KR950001298B1 (en) Manufacturing method of wire bonding pad
JP2625967B2 (en) Printed wiring board
JP2000232092A (en) Manufacture of semiconductor device and semiconductor device
JPH05315732A (en) Manufacture of wiring board
JPS62245251A (en) Resist pattern forming method
JPH09232321A (en) Bump electrode and manufacture thereof
JP3526529B2 (en) Method for manufacturing semiconductor device
JPH06151351A (en) Method of electrode formation
KR100326430B1 (en) Method for forming photo resist in semiconductor device
JPH05190545A (en) Formation of viahole
JPH07254643A (en) Semiconductor integrated circuit device and fabrication thereof
JP2008258439A (en) Method for manufacturing semiconductor device
JP2833315B2 (en) TAB tape carrier
JPH0653222A (en) Formation method of bump electrode