JPH06349675A - Manufacture of multilayered ceramic capacitor - Google Patents
Manufacture of multilayered ceramic capacitorInfo
- Publication number
- JPH06349675A JPH06349675A JP16399693A JP16399693A JPH06349675A JP H06349675 A JPH06349675 A JP H06349675A JP 16399693 A JP16399693 A JP 16399693A JP 16399693 A JP16399693 A JP 16399693A JP H06349675 A JPH06349675 A JP H06349675A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layers
- internal electrode
- ceramic sheets
- laminated
- inner electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000003985 ceramic capacitor Substances 0.000 title claims description 6
- 239000000919 ceramic Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000010304 firing Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 17
- 239000003990 capacitor Substances 0.000 abstract description 17
- 238000007796 conventional method Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、積層型セラミックコン
デンサ（以下、単に「コンデンサ」という）の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated ceramic capacitor (hereinafter, simply referred to as "capacitor").
【０００２】[0002]
【従来の技術】従来、一般にこの種のコンデンサの製造
は、図７に示すように、先ず、複数枚の未焼成のセラミ
ックシート（グリーンシート）Ａ1’，Ａ2’，Ａ3’，
Ａ4’の表面に、各々内部電極層Ｂ1’，Ｂ2’，Ｂ3’，
Ｂ4’を交互にずらせて印刷により形成した後、これら
各セラミックシートＡ1’，Ａ2’，Ａ3’，Ａ4’を、図
８に示すように、重ね合わせて積層すると共に、最上面
のセラミックシートＡ1’における内部電極層Ｂ1’を覆
うための未焼成のセラミックシートカバーＣ’を 重ね
合わせて積層し、次いで、この積層体を、縦横格子状の
切断線Ｄ1’，Ｄ2’に沿って切断して積層チップ片１’
ごとに分割し、この各積層チップ片１’を焼成し、そし
て、この各積層チップ片１’の左右両端面１ａ’，１
ｂ’に対して、図９に示すように、端面電極層２’を形
成することによって行われている。2. Description of the Related Art Conventionally, as shown in FIG. 7, generally, in manufacturing a capacitor of this type, first, a plurality of unfired ceramic sheets (green sheets) A 1 ′, A 2 ′, A 3 ′,
Internal electrode layers B 1 ′, B 2 ′, B 3 ′, on the surface of A 4 ′,
After B 4 ′ is alternately formed by printing, the respective ceramic sheets A 1 ′, A 2 ′, A 3 ′ and A 4 ′ are stacked and laminated as shown in FIG. unfired ceramic sheet cover C of to cover the 'inner electrode layer B 1' in the ceramic sheet a 1 of upper surface 'are stacked by overlapping, then the laminate, the aspect lattice cutting line D 1', D 2 'laminated chip component 1 is cut along a'
Each of the laminated chip pieces 1'is fired, and the left and right end surfaces 1a ', 1 of the laminated chip pieces 1'are divided.
For b ′, as shown in FIG. 9, it is performed by forming an end face electrode layer 2 ′.
【０００３】通常、コンデンサは、用途により異なる電
気容量値（容量値）のものが使用されるために、種々電
気容量値を持ったものが要求される。Normally, capacitors having different electric capacitance values (capacitance values) are used depending on the application, and therefore capacitors having various electric capacitance values are required.
【０００４】上記コンデンサの電気容量値は、誘電体の
種類、内部電極間距離、内部電極面積及び内部電極層数
（内部電極重ね枚数）の組み合わせにより決定される。
一般に、上記誘電体の種類、内部電極間距離及び内部電
極面積が標準化されていることから、電気容量値の調整
は、内部電極層数を変えて行われているのが実状であ
る。The electric capacitance value of the capacitor is determined by a combination of the type of dielectric material, the distance between internal electrodes, the internal electrode area, and the number of internal electrode layers (the number of internal electrode layers).
Generally, since the types of the dielectrics, the distance between the internal electrodes, and the internal electrode area are standardized, the adjustment of the electric capacitance value is actually performed by changing the number of internal electrode layers.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記の
ように内部電極層数により容量値の調整を行う場合に
は、ある幅で容量値を違えたものについては製造できる
が、最近のますます高精度化される技術において、より
細分化して容量値調整されたものをという市場の要求に
は対応できなくなってきている。すなわち、内部電極層
数の整数において製造可能なものであれば問題ないのだ
が、内部電極層数を小数点以下の端数にまでしないと製
造できないような容量値のものについては内部電極層の
形成位置をずらせるか形成面積を変えない限り実現不可
能となる。[Problems to be Solved by the Invention] However, in the case of adjusting the capacitance value by the number of internal electrode layers as described above, it is possible to manufacture a capacitor having a different capacitance value within a certain width, but recently it is getting higher and higher. It is becoming difficult to meet the market demand for more precise and more finely adjusted capacitance values. That is, there is no problem as long as it can be manufactured with an integer number of internal electrode layers, but for the capacitance value that cannot be manufactured unless the number of internal electrode layers is a fractional part, the formation position of internal electrode layers It will not be possible unless the displacement is changed or the formation area is changed.
【０００６】しかし、容量値を小さくするべく、図８に
示す内部電極層の重なり面積（有効電極面積）の幅
Ｌ1’を、図１０に示すように、Ｌ2’まで内部電極層Ｂ
2’，Ｂ4’の形成位置をずらせるとなると、所々で使用
できない部分Ｆが生じてしまい生産効率が低下してしま
う。また、内部電極層の形成面積を変えるとなると、そ
れに必要な印刷形成用のパターンの種類が増えると共
に、所望の容量値を得るためのパターンの組み合わせが
複雑となり作業の標準化が困難である。However, in order to reduce the capacitance value, the width L 1 of the overlapping area of the internal electrode layer shown in FIG. 8 (effective electrode area) 'a, as shown in FIG. 10, L 2' inner electrode layer B to
2 ', B 4' when it comes shifting the formation position of, the production efficiency will occur a portion F can not be used in places decreases. Further, when the formation area of the internal electrode layer is changed, the number of types of patterns for print formation required for it is increased, and the combination of patterns for obtaining a desired capacitance value is complicated, and it is difficult to standardize the work.
【０００７】一方、種々の容量値を得るべく、内部電極
層の形成していない未焼成のセラミックシート（ダミー
層）を内部電極層の形成された未焼成のセラミックシー
ト間に挟むことにより内部電極間距離を長くして容量値
を調整する方法も考えられ行ってみたが、容量値にばら
つきが見られ正確さに欠けるという問題があった。On the other hand, in order to obtain various capacitance values, an unfired ceramic sheet (dummy layer) without an internal electrode layer is sandwiched between unfired ceramic sheets with an internal electrode layer formed therein. A method of adjusting the capacitance value by increasing the distance between them was also considered and tried, but there was a problem in that the capacitance value varied and the accuracy was insufficient.
【０００８】本発明は、同一の内部電極層の形成パター
ン且つ同一の内部電極層数で効率よく種々の容量値のコ
ンデンサを作り出すことを目的とする。An object of the present invention is to efficiently produce capacitors having various capacitance values with the same formation pattern of internal electrode layers and the same number of internal electrode layers.
【０００９】[0009]
【課題を解決するための手段】本発明者は、単一の内部
電極層パターンで、しかも同一の内部電極層数で無駄な
く複数種の容量値のコンデンサを製造できれば、より容
量値の細分化が可能で、製造方法の標準化をも図れるこ
とに着目し、鋭意研究を重ねた結果、内部電極層を、以
後の積層体の縦切断幅より短い形成長さで所定間隔ごと
に形成した複数枚の未焼成のセラミックシートを、上記
内部電極層が交互にずれるようにして積層し積層体と
し、この積層体の上記内部電極層の全てが平面重合する
部分で、該平面重合する部分の一つおきに切断したとき
は、上記各未焼成のセラミックシートの内部電極層の形
成位置をずらして積層するだけで種々の容量値のコンデ
ンサが得られることを見出した。Means for Solving the Problems If the present inventor can manufacture capacitors of plural kinds of capacitance values with a single internal electrode layer pattern and with the same number of internal electrode layers without waste, the capacitance value can be further subdivided. As a result of intensive research, focusing on the fact that it is possible to standardize the manufacturing method, a plurality of internal electrode layers are formed at predetermined intervals with a formation length shorter than the vertical cutting width of the subsequent laminated body. Of unfired ceramic sheets are laminated so that the internal electrode layers are alternately displaced to form a laminated body, and a portion where all the internal electrode layers of the laminated body are superposed on each other is one of the flattened portions. It has been found that when cut into pieces, capacitors having various capacitance values can be obtained only by shifting the formation positions of the internal electrode layers of the respective unfired ceramic sheets and stacking them.
【００１０】即ち、本発明は、（ａ）内部電極層を一定
間隔ごとに隔て形成した所定枚数の未焼成セラミックシ
ートを上記内部電極層が交互にずらされて積層された積
層体を形成する積層工程、（ｂ）上記積層体を所定幅ご
とに縦横に切断して多数個の積層チップ片に分割する分
割工程、（ｃ）上記積層チップ片を焼成する焼成工程、
及び（ｄ）上記焼成された積層チップ片の端面に電極層
を形成する端面電極形成工程を有する積層型セラミック
コンデンサの製造方法において、上記（ａ）の積層工程
において、内部電極層が略同一のパターンで形成された
所定枚数の未焼成のセラミックシートを交互にずらせて
積層し、上記（ｂ）の分割工程において、上記各未焼成
のセラミックシートにおける上記内部電極層の全てが平
面重合する領域で等間隔ごとに切断することを特徴とす
る積層型セラミックコンデンサの製造方法に係るもので
ある。That is, according to the present invention, (a) a laminate for forming a laminate in which a predetermined number of unfired ceramic sheets having internal electrode layers formed at regular intervals are alternately stacked and laminated. A step of dividing the laminated body into a large number of laminated chip pieces by cutting the laminated body vertically and horizontally into a plurality of laminated chip pieces, and (c) a firing step of firing the laminated chip pieces.
And (d) a method of manufacturing a multilayer ceramic capacitor having an end face electrode forming step of forming an electrode layer on an end face of the fired multilayer chip piece, wherein in the laminating step (a), the internal electrode layers are substantially the same. A predetermined number of unfired ceramic sheets formed in a pattern are alternately staggered and laminated, and in the dividing step (b), all the internal electrode layers in each of the unfired ceramic sheets are flatly overlapped in a region. The present invention relates to a method for manufacturing a monolithic ceramic capacitor, which is characterized in that it is cut at regular intervals.
【００１１】[0011]
【作用】未焼成のセラミックシート及び内部電極層から
なる積層体を縦横に切断する縦切断線の間隔よりも短い
形成長さの内部電極層を、同一形成パターンで形成した
未焼成のセラミックシートの複数枚を、上記各セラミッ
クシートの内部電極層を交互にずらし有効電極面積を変
えて積層する。この積層体を各セラミックシートの内部
電極層の全てが平面重合する平面領域において縦切断す
る。従って、上記有効電極面積の違いにより異なった容
量値のコンデンサが連続して得られる。The function of the unfired ceramic sheet in which the internal electrode layers having the formation length shorter than the interval between the vertical cutting lines for vertically and horizontally cutting the laminate composed of the unfired ceramic sheet and the internal electrode layers are formed in the same formation pattern A plurality of sheets are laminated by alternately shifting the internal electrode layers of each of the above ceramic sheets and changing the effective electrode area. This laminated body is longitudinally cut in a flat area where all the internal electrode layers of each ceramic sheet are superposed. Therefore, capacitors having different capacitance values can be continuously obtained due to the difference in the effective electrode area.
【００１２】[0012]
【実施例】以下、本発明の実施例を、図１〜図６の図面
について説明する。Embodiments of the present invention will be described below with reference to the drawings of FIGS.
【００１３】先ず、図１に示すように、複数枚の未焼成
のセラミックシート（グリーンシート）Ａ1，Ａ2，
Ａ3，Ａ4の表面に、各々内部電極層Ｂ1，Ｂ2，Ｂ3，Ｂ4
を交互にずらせて形成する。上記セラミックシート
Ａ1，Ａ2，Ａ3，Ａ4における内部電極層Ｂ1，Ｂ2，
Ｂ3，Ｂ4の形成パターンは全て同じで、例えば導電性ペ
ーストを用いてスクリーン印刷等の印刷法により行うこ
とができる。First, as shown in FIG. 1, a plurality of unfired ceramic sheets (green sheets) A 1 , A 2 ,
Internal electrode layers B 1 , B 2 , B 3 , B 4 are formed on the surfaces of A 3 , A 4 , respectively.
Are formed alternately. The internal electrode layers B 1 , B 2 , in the ceramic sheets A 1 , A 2 , A 3 , A 4
The formation patterns of B 3 and B 4 are all the same and can be performed by a printing method such as screen printing using a conductive paste.
【００１４】次いで、図２に示すように、これら各セラ
ミックシートＡ1，Ａ2，Ａ3，Ａ4を、セラミックシート
Ａ1，Ａ3における内部電極層Ｂ1，Ｂ3とセラミックシー
トＡ2，Ａ4における内部電極層Ｂ2，Ｂ4とがその形成位
置を所定寸法ずれた状態に重ね合わせて積層すると共
に、最上面のセラミックシートＡ1における内部電極層
Ｂ1を覆うための未焼成のセラミックシートカバーＣを
重ね合わせて、図３に示 すような断面構造の積層体と
する。Then, as shown in FIG. 2, these ceramic sheets A 1 , A 2 , A 3 and A 4 are respectively attached to the internal electrode layers B 1 and B 3 and the ceramic sheet A 2 in the ceramic sheets A 1 and A 3 . , A 4 of the internal electrode layers B 2 and B 4 are stacked in such a manner that the formation positions thereof are deviated by a predetermined dimension, and unfired to cover the internal electrode layer B 1 of the uppermost ceramic sheet A 1 . The ceramic sheet covers C are laminated to form a laminated body having a sectional structure as shown in FIG.
【００１５】そして、上記積層体を、縦横格子状の縦横
切断線Ｄ1，Ｄ2に沿って各未焼成のセラミックシートＡ
1，Ａ2，Ａ3，Ａ4における上記内部電極層Ｂ1，Ｂ2，Ｂ
3，Ｂ4の全てが平面重合する領域で等間隔ごとに切断し
て積層チップ片１ごとに分 割し、この各積層チップ片
１を焼成し、図４に示すように、この各積層チップ片１
の左右両端面１ａ，１ｂに対して端面電極層２を形成し
てコンデンサが得られる。Then, the unfired ceramic sheet A is formed by stacking the above-mentioned laminated body along vertical and horizontal cut lines D 1 and D 2 in a vertical and horizontal lattice pattern.
The internal electrode layers B 1 , B 2 , B in 1 , A 2 , A 3 , A 4
In the region where all 3 and B 4 are planarly overlapped, they are cut at equal intervals and divided into laminated chip pieces 1, each laminated chip piece 1 is fired, and as shown in FIG. Piece 1
Capacitors are obtained by forming the end face electrode layers 2 on the left and right end faces 1a and 1b.
【００１６】図１において、上記内部電極層の長さｂ
は、上記積層チップ片１の幅ａ（セラミックシートの縦
切断線Ｄ1の間隔）よりも短く、且つ連続する一つの内
部電極層はその一方端部のみ縦切断線Ｄ1を跨ぐように
形成される。また、縦切断線Ｄ1において、積層状態の
内部電極層Ｂ1，Ｂ2，Ｂ3，Ｂ4は、全て重合するように
形成されている。換言すれば、上記積層体は各セラミッ
クシートＡ1，Ａ2，Ａ3， Ａ4の内部電極層Ｂ1，Ｂ2，
Ｂ3，Ｂ4の全てが平面重合する平面領域Ｅにおいて 縦
切断され（図３参照）、得られるコンデンサにおける内
部電極層Ｂ1，Ｂ2，Ｂ3，Ｂ4は、積層チップ片１の左右
両端面１ａ，１ｂに跨るように形成されており、上記左
端面１ａから右端面１ｂの途中において一部途切れた箇
所があり不連続となっている。In FIG. 1, the length b of the internal electrode layer is
Is shorter than the width a of the laminated chip piece 1 (distance between the vertical cutting lines D 1 of the ceramic sheet), and one continuous internal electrode layer is formed so that only one end thereof crosses the vertical cutting line D 1. To be done. Further, at the vertical cutting line D 1 , the internal electrode layers B 1 , B 2 , B 3 , B 4 in the laminated state are all formed so as to be superposed. In other words, the above-mentioned laminated body is the internal electrode layers B 1 , B 2 , and B 1 of each ceramic sheet A 1 , A 2 , A 3 , A 4 .
The internal electrode layers B 1 , B 2 , B 3 and B 4 in the resulting capacitor are vertically cut in the plane area E where all of B 3 and B 4 overlap in plane (see FIG. 3). It is formed so as to straddle both end faces 1a and 1b, and there is a discontinuity at a part of the left end face 1a to the right end face 1b, which is partially interrupted.
【００１７】以上のように内部電極層を積層すれば、無
駄な積層チップ片は生じず、生産効率をより容易な方法
において向上し得る。By laminating the internal electrode layers as described above, useless laminated chip pieces are not generated, and the production efficiency can be improved by a simpler method.
【００１８】図５及び図６に、上記セラミックシートＡ
1，Ａ3における内部電極層Ｂ1，Ｂ3とセラミックシート
Ａ2，Ａ4における内部電極層Ｂ2，Ｂ4との形成位置のず
らす寸法を変えたときの例を示す。図３に示すように、
上記実施例におけるコンデンサの有効電極面積の幅Ｌ1
を１とすると、図５のものの有効電極面積の幅Ｌ2は２
／３、図６のものの有効電極面積の幅Ｌ3は１／３とな
っている。このように、内部電極層を同一形成パターン
で形成したセラミックシートの同じ枚数を用いて違った
容量値のコンデンサを得ることができる。5 and 6, the above-mentioned ceramic sheet A is shown.
An example of a case of changing the dimensions of shifting the formation position of the internal electrode layer B 2, B 4 in the internal electrode layers B 1, B 3 and the ceramic sheet A 2, A 4 in 1, A 3. As shown in FIG.
Width L 1 of the effective electrode area of the capacitor in the above embodiment
Is 1, the effective electrode area width L 2 in FIG. 5 is 2
/ 3, the width L 3 of the effective electrode area of FIG. 6 is ⅓. In this way, capacitors having different capacitance values can be obtained by using the same number of ceramic sheets in which the internal electrode layers are formed in the same formation pattern.
【００１９】上記本発明の方法を利用して、前記したよ
うな内部電極層数を変えれば、内部電極層の形成パター
ンを変えたりダミー層を用いるという煩雑な作業を行う
必要なく、コンデンサの容量値をより細かく調整でき
る。By changing the number of internal electrode layers as described above by using the method of the present invention, it is not necessary to change the formation pattern of the internal electrode layers or use a dummy layer to perform the complicated work, and the capacitance of the capacitor The value can be adjusted more finely.
【００２０】[0020]
【発明の効果】以上説明したように、本発明によれば、
単一の内部電極層パターンで、しかも同一の内部電極層
数で無駄なく複数種の容量値のコンデンサを製造でき
る。As described above, according to the present invention,
Capacitors having a plurality of capacitance values can be manufactured with a single internal electrode layer pattern and with the same number of internal electrode layers without waste.
【００２１】また、複数種の容量値を得るのに単一のマ
スクで内部電極層を形成できるので、作業の標準化が容
易で生産管理上のメリットも大きい。Further, since the internal electrode layer can be formed with a single mask in order to obtain a plurality of kinds of capacitance values, standardization of work is easy and there is a great merit in production control.
【図１】本発明の実施例において各セラミックシートに
内部電極層を形成した状態の斜視図である。FIG. 1 is a perspective view showing a state where an internal electrode layer is formed on each ceramic sheet in an example of the present invention.
【図２】本発明の実施例において前記セラミックシート
を積層して積層体にした状態の斜視図である。FIG. 2 is a perspective view showing a state where the ceramic sheets are laminated to form a laminated body in the embodiment of the present invention.
【図３】図２のＩ−Ｉ断面図である。3 is a cross-sectional view taken along the line I-I of FIG.
【図４】本発明の実施例における積層チップ片の端面に
端面電極層を形成した状態の断面図である。FIG. 4 is a cross-sectional view showing a state where an end face electrode layer is formed on an end face of a laminated chip piece in an example of the present invention.
【図５】本発明の他の実施例の積層体の断面図である。FIG. 5 is a cross-sectional view of a laminated body according to another embodiment of the present invention.
【図６】本発明の他の実施例の積層体の断面図である。FIG. 6 is a cross-sectional view of a laminated body according to another embodiment of the present invention.
【図７】従来の方法において各セラミックシートに内部
電極層を形成した状態の斜視図である。FIG. 7 is a perspective view showing a state in which an internal electrode layer is formed on each ceramic sheet by a conventional method.
【図８】従来の方法における積層チップ片の端面に端面
電極層を形成した状態の断面図である。FIG. 8 is a cross-sectional view showing a state where an end face electrode layer is formed on an end face of a laminated chip piece according to a conventional method.
【図９】従来の方法における積層チップ片の端面に端面
電極層を形成した状態の断面図である。FIG. 9 is a cross-sectional view showing a state where an end face electrode layer is formed on an end face of a laminated chip piece according to a conventional method.
【図１０】図８において内部電極層のずらす寸法を変え
たときの状態の断面図である。FIG. 10 is a cross-sectional view showing a state in which the displacement size of the internal electrode layers in FIG. 8 is changed.
１ 積層チップ片 ２ 端面電極層 Ａ1，Ａ2，Ａ3，Ａ4，Ｃ セラミックシート Ｂ1，Ｂ2，Ｂ3，Ｂ4 内部電極層 Ｄ1 縦切断線 Ｄ2 横切断線1 laminated chip piece 2 end face electrode layer A 1 , A 2 , A 3 , A 4 , C ceramic sheet B 1 , B 2 , B 3 , B 4 internal electrode layer D 1 vertical cutting line D 2 horizontal cutting line
Claims (1)
した所定枚数の未焼成セラミックシートの積層体を形成
する積層工程、（ｂ）上記積層体を所定幅ごとに縦横に
切断して多数個の積層チップ片に分割する分割工程、
（ｃ）上記積層チップ片を焼成する焼成工程、及び
（ｄ）上記焼成された積層チップ片の端面に電極層を形
成する端面電極形成工程を有する積層型セラミックコン
デンサの製造方法において、上記（ａ）の積層工程にお
いて、内部電極層が略同一のパターンで形成された所定
枚数の未焼成のセラミックシートを交互にずらせて積層
し、上記（ｂ）の分割工程において、上記各未焼成のセ
ラミックシートにおける上記内部電極層の全てが平面重
合する領域で等間隔ごとに切断することを特徴とする積
層型セラミックコンデンサの製造方法。1. A laminating step of forming a laminated body of a predetermined number of unfired ceramic sheets formed by alternately shifting internal electrode layers, and (b) cutting the laminated body vertically and horizontally at a predetermined width. A dividing step of dividing into a large number of laminated chip pieces,
In the method for manufacturing a multilayer ceramic capacitor, which comprises (c) a firing step of firing the laminated chip piece, and (d) an end face electrode forming step of forming an electrode layer on an end face of the fired laminated chip piece, ), A predetermined number of unfired ceramic sheets having internal electrode layers formed in substantially the same pattern are alternately staggered and stacked, and in the dividing step (b), each of the unfired ceramic sheets is stacked. 2. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein all of the internal electrode layers are cut at equal intervals in a region where they are superposed.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16399693A JPH06349675A (en) | 1993-06-07 | 1993-06-07 | Manufacture of multilayered ceramic capacitor |
| GB9406165A GB2278957A (en) | 1993-06-07 | 1994-03-29 | Method of manufacturing multi-layer ceramic capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16399693A JPH06349675A (en) | 1993-06-07 | 1993-06-07 | Manufacture of multilayered ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06349675A true JPH06349675A (en) | 1994-12-22 |
Family
ID=15784782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16399693A Pending JPH06349675A (en) | 1993-06-07 | 1993-06-07 | Manufacture of multilayered ceramic capacitor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH06349675A (en) |
| GB (1) | GB2278957A (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3617834A (en) * | 1970-08-31 | 1971-11-02 | Illinois Tool Works | Monolithic capacitor components and process for producing same |
| GB2084800B (en) * | 1981-07-28 | 1985-06-05 | Avx Corp | Method of making marginless multi-layer ceramic capacitors |
| JP2504223B2 (en) * | 1989-10-11 | 1996-06-05 | 株式会社村田製作所 | Manufacturing method of multilayer capacitor |
-
1993
- 1993-06-07 JP JP16399693A patent/JPH06349675A/en active Pending
-
1994
- 1994-03-29 GB GB9406165A patent/GB2278957A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| GB2278957A (en) | 1994-12-14 |
| GB9406165D0 (en) | 1994-05-18 |
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