JPH0837129A - Production of monolithic electronic parts - Google Patents

Production of monolithic electronic parts

Info

Publication number
JPH0837129A
JPH0837129A JP19219794A JP19219794A JPH0837129A JP H0837129 A JPH0837129 A JP H0837129A JP 19219794 A JP19219794 A JP 19219794A JP 19219794 A JP19219794 A JP 19219794A JP H0837129 A JPH0837129 A JP H0837129A
Authority
JP
Japan
Prior art keywords
electrode
electronic component
laminated
internal
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19219794A
Other languages
Japanese (ja)
Other versions
JP3610985B2 (en
Inventor
Hiromichi Tokuda
博道 徳田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP19219794A priority Critical patent/JP3610985B2/en
Publication of JPH0837129A publication Critical patent/JPH0837129A/en
Application granted granted Critical
Publication of JP3610985B2 publication Critical patent/JP3610985B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To efficiently produce a monolithic electronic part of three-terminal type by using an electrode added with one kind of electrode pattern. CONSTITUTION:A dielectric sheet 13 is provided with a plurality of first electrode patterns 11 for first internal electrode that are prepared approximately in parallel at a specified interval and a plurality of second electrode patterns 12 for second internal electrodes are prepared facing each other with the pattern 11 in between, and the length L of the pattern 12 in a direction perpendicular to the pattern 11 is approximately the same as the length of a gap G between the facing patterns 12 with the pattern 11 interposed therein. Therefore, the sheet 13 is plurally stacked to form a multilayered block at such a specified position that the patterns 11 and 12 may be allowed to construct first and second internal electrodes in respective electronic parts, and the respective electronic part elements are cut off by cutting the sheets 13 at the specified positions.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子部品の製造方法に
関し、詳しくは、3端子型の積層電子部品の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic component, and more particularly to a method of manufacturing a three-terminal type laminated electronic component.

【0002】[0002]

【従来の技術】代表的な積層電子部品の一つである積層
セラミックコンデンサ(この例では3端子型の積層セラ
ミックコンデンサ)は、例えば、図4,図5に示すよう
に、誘電体層33を介してアース用の電極(アース電
極)31と、容量形成用の電極(容量電極)32とを交
互に積層し、かつ、上下にダミー層(電極が形成されて
いないシート)34を積層した構造を有する積層素子3
5の両端側に、容量電極32と導通する外部電極6a,
6b(図4)を配設するとともに、積層素子35の中央
部を一周するように、アース電極31と導通するアース
用外部電極7(図4)を配設してなる構造を有してい
る。
2. Description of the Related Art A monolithic ceramic capacitor (a three-terminal type monolithic ceramic capacitor in this example), which is one of typical monolithic electronic components, has a dielectric layer 33 as shown in FIGS. 4 and 5, for example. A structure in which an electrode for grounding (earth electrode) 31 and an electrode for forming capacitance (capacitance electrode) 32 are alternately laminated, and dummy layers (sheets on which electrodes are not formed) 34 are laminated above and below. Laminated element 3 having
5, the external electrodes 6a, which are electrically connected to the capacitive electrode 32,
6b (FIG. 4) and a structure in which a grounding external electrode 7 (FIG. 4) that is electrically connected to the grounding electrode 31 is arranged so as to surround the central portion of the laminated element 35. .

【0003】ところで、上記のような構造を有する3端
子型の積層セラミックコンデンサを製造する場合、図6
(a),(b)に示すように、所定の方向にアース電極形成
用の複数の第1の電極パターン21が形成された誘電体
層形成用の第1の誘電体シート(セラミックグリーンシ
ート)23と、前記第1の電極パターン21と直交する
方向に容量電極形成用の複数の第2の電極パターン(グ
ランドパターン)22が形成された第2の誘電体シート
(セラミックグリーンシート)24の2種類の誘電体シ
ート(電極シート)を用意し、この2種類の誘電体シー
ト23,24を交互に積層して、積層ブロック(図示せ
ず)を形成し、これを所定の位置で切断し、切り出され
た個々の積層素子を焼成した後、外部電極6a,6b、
及び7を形成することにより、図4に示すような3端子
型の積層電子部品を製造している。
By the way, in the case of manufacturing a three-terminal type monolithic ceramic capacitor having the above structure, FIG.
As shown in (a) and (b), a first dielectric sheet for forming a dielectric layer (ceramic green sheet) in which a plurality of first electrode patterns 21 for forming a ground electrode are formed in a predetermined direction. 2 and a second dielectric sheet (ceramic green sheet) 24 in which a plurality of second electrode patterns (ground patterns) 22 for forming capacitive electrodes are formed in a direction orthogonal to the first electrode pattern 21. Dielectric sheets (electrode sheets) of different types are prepared, the two types of dielectric sheets 23 and 24 are alternately laminated to form a laminated block (not shown), which is cut at a predetermined position, After firing the cut-out individual laminated elements, the external electrodes 6a, 6b,
By forming 7 and 7, a three-terminal type laminated electronic component as shown in FIG. 4 is manufactured.

【0004】[0004]

【発明が解決しようとする課題】ところで、上述のよう
に、2種類の誘電体シート23,24を使用して3端子
型の積層電子部品を製造する場合、
By the way, as described above, in the case of manufacturing a three-terminal type laminated electronic component using the two types of dielectric sheets 23 and 24,

【0005】第1及び第2の電極パターン21,22
を、それぞれ異なる誘電体シート23,24に印刷しな
ければならず、そのための印刷段取りの切換えが必要で
手間がかかる 第1の電極パターン21が形成された第1の誘電体シ
ート23と第2の電極パターン22が形成された第2の
誘電体シート24が交互に積層されていることを確認す
ることが必要で、その監視を確実に行うためにはコスト
がかかる というような問題点がある。
First and second electrode patterns 21, 22
Must be printed on different dielectric sheets 23 and 24, and it takes time and labor to change the print setup for that purpose. The first dielectric sheet 23 and the second dielectric sheet 23 on which the first electrode pattern 21 is formed are time-consuming. It is necessary to confirm that the second dielectric sheets 24 having the electrode patterns 22 are alternately laminated, and there is a problem that it is costly to reliably monitor the second dielectric sheets 24. .

【0006】本発明は、上記問題点を解決するものであ
り、1種類の電極パターンが付与された誘電体シートを
用いて3端子型の積層電子部品を効率よく製造すること
が可能な積層電子部品の製造方法を提供することを目的
とする。
The present invention solves the above problems and is capable of efficiently manufacturing a three-terminal type laminated electronic component using a dielectric sheet provided with one kind of electrode pattern. An object is to provide a method of manufacturing a component.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の積層電子部品の製造方法は、一方の端部
から他方の端部に至る第1の内部電極と、前記第1の内
部電極と略直交する方向に形成され、一方の端部から他
方の端部に至る第2の内部電極が、誘電体層を介して交
互に積層された構造を有する3端子型の積層電子部品の
製造方法であって、前記積層電子部品の第1の内部電極
となる第1の電極パターンが所定の間隔をおいて略平行
に複数配設されているとともに、前記第1の電極パター
ンをはさんで互に対向する位置に、前記積層電子部品の
第2の内部電極となる第2の電極パターンが所定のピッ
チで複数配設され、かつ第2の電極パターンの前記第1
の電極パターンと直交する方向の長さが、前記第1の電
極パターンをはさんで対向する2つの第2の電極パター
ンの間隔と略同一である誘電体シートを形成する工程
と、前記誘電体シートを複数枚積層して所定の位置で切
断することにより個々の電子部品素子を切り出したとき
に、前記第1及び第2の電極パターンが、個々の電子部
品素子において前記第1及び第2の内部電極を構成する
ように、互に隣接する誘電体シートのうちの一方の誘電
体シートの第1の電極パターンが、他方の誘電体シート
の第2の電極パターンに、また、一方の誘電体シートの
第2の電極パターンが、他方の誘電体シートの第1の電
極パターンに、誘電体シートを介して直交するような状
態で重なり合うように、所定の位置関係で誘電体シート
を複数枚積層することにより積層ブロックを形成する工
程と、前記積層ブロックを所定の位置で切断することに
より、前記第1及び第2の内部電極が誘電体層を介して
交互に積層された構造を有する個々の電子部品素子を切
り出す工程とを具備することを特徴としている。
In order to achieve the above-mentioned object, a method of manufacturing a laminated electronic component according to the present invention comprises a first internal electrode extending from one end to the other end and the first internal electrode. Three-terminal type stacked electron having a structure in which second internal electrodes formed in a direction substantially orthogonal to the internal electrodes of the above and extending from one end to the other end are alternately stacked via a dielectric layer. In the method of manufacturing a component, a plurality of first electrode patterns, which are first internal electrodes of the multilayer electronic component, are arranged substantially parallel to each other at a predetermined interval, and the first electrode pattern is A plurality of second electrode patterns serving as the second internal electrodes of the laminated electronic component are arranged at a predetermined pitch at positions facing each other and the first electrode of the second electrode pattern is provided.
Forming a dielectric sheet whose length in the direction orthogonal to the electrode pattern is substantially the same as the interval between two second electrode patterns facing each other across the first electrode pattern; When the individual electronic component elements are cut out by laminating a plurality of sheets and cutting the sheets at predetermined positions, the first and second electrode patterns have the first and second electrode patterns in the individual electronic component elements. The first electrode pattern of one of the dielectric sheets adjacent to each other forms the second electrode pattern of the other dielectric sheet so as to form the internal electrode, and the one dielectric sheet of the other dielectric sheet. A plurality of dielectric sheets are laminated in a predetermined positional relationship so that the second electrode pattern of the sheet overlaps the first electrode pattern of the other dielectric sheet in a state of being orthogonal to each other through the dielectric sheet. To do And an individual electronic component having a structure in which the first and second internal electrodes are alternately laminated with a dielectric layer interposed therebetween by cutting the laminated block at a predetermined position. And a step of cutting out the element.

【0008】また、前記第1及び第2の内部電極のう
ち、アース用の電極となる方の内部電極が、互に近接す
る2本の略平行な電極から構成されており、かつ、前記
第1及び第2の電極パターンのいずれか一方が、前記2
本の略平行な電極からなる内部電極を構成することがで
きるように、互に近接して配設された2本の略平行な電
極から構成されていることを特徴としている。
In addition, of the first and second internal electrodes, the internal electrode that serves as a ground electrode is composed of two substantially parallel electrodes that are close to each other, and Either one of the first and second electrode patterns is the above-mentioned 2
It is characterized in that it is composed of two substantially parallel electrodes arranged close to each other so that an internal electrode composed of two substantially parallel electrodes can be composed.

【0009】[0009]

【作用】本発明の積層電子部品の製造方法においては、
前記所定の要件を満たすような第1及び第2の電極パタ
ーンを配設した誘電体シートを前記所定の態様で複数枚
積層し、これを所定の位置で切断して個々の電子部品素
子を切り出すことにより、前記第1及び第2の電極パタ
ーンが、個々の電子部品素子の第1及び第2の内部電極
となる。したがって、1種類の電極パターンが付与され
た誘電体シートを用いて、第1の内部電極及びこれと直
交する第2の内部電極が誘電体層を介して交互に積層さ
れた構造を有する3端子型の積層電子部品を効率よく製
造することが可能になる。
In the method of manufacturing a laminated electronic component of the present invention,
A plurality of dielectric sheets provided with the first and second electrode patterns satisfying the predetermined requirements are laminated in the predetermined mode, and cut at predetermined positions to cut out individual electronic component elements. As a result, the first and second electrode patterns become the first and second internal electrodes of each electronic component element. Therefore, a three-terminal structure having a structure in which a first internal electrode and a second internal electrode orthogonal to the first internal electrode are alternately laminated using a dielectric sheet provided with one type of electrode pattern It becomes possible to efficiently manufacture a laminated electronic component of a mold.

【0010】なお、本発明の積層電子部品の製造方法に
おいては、誘電体シートの第1及び第2の電極パターン
のうちの任意の一方を積層電子部品の第1の内部電極と
し、他方を第2の内部電極とすることが可能である。ま
た、積層電子部品においては、第1及び第2の内部電極
のうちの任意の一方を、例えば容量形成用の電極(容量
電極)とし、他方をアース用の電極(アース電極)とす
ることができる。
In the method for manufacturing a laminated electronic component of the present invention, any one of the first and second electrode patterns of the dielectric sheet is used as the first internal electrode of the laminated electronic component, and the other is the first internal electrode. It is possible to have two internal electrodes. In the laminated electronic component, one of the first and second internal electrodes may be, for example, a capacitance forming electrode (capacitance electrode), and the other may be an earth electrode (earth electrode). it can.

【0011】また、前記第1及び第2の電極パターンの
いずれか一方を、互に近接して配設された2本の略平行
な電極から構成することにより、2本の略平行な電極
(分割電極)からなる内部電極を有する積層電子部品を
製造することが可能になる。なお、例えば、2本の略平
行な電極からなる分割電極をアース電極(内部電極)と
した3端子型の積層コンデンサにおいては、ノイズ除去
性能が向上するという効果が得られる。
Further, by constructing either one of the first and second electrode patterns from two substantially parallel electrodes arranged close to each other, two substantially parallel electrodes ( It becomes possible to manufacture a laminated electronic component having an internal electrode composed of divided electrodes. Note that, for example, in a three-terminal type multilayer capacitor having a ground electrode (internal electrode) that is a divided electrode formed of two substantially parallel electrodes, an effect of improving noise removal performance can be obtained.

【0012】[0012]

【実施例】以下、本発明の実施例を図に基づいて説明す
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0013】なお、この実施例では、図3,図4に示す
ように、誘電体層3を介してアース用の電極(アース電
極)1と容量形成用の電極(容量電極)2が交互に積層
され、かつ、上下にダミー層(電極が形成されていない
シート)4が積層された構造を有する積層素子5の両端
側に、容量電極2と導通する外部電極6a,6b(図
4)を配設するとともに、積層素子5の中央部を一周す
るように、アース電極1と導通するアース用外部電極7
(図4)を配設してなる構造を有する3端子型の積層電
子部品を製造する場合を例にとって説明する。
In this embodiment, as shown in FIGS. 3 and 4, the ground electrode (ground electrode) 1 and the capacitance forming electrode (capacitance electrode) 2 are alternately arranged via the dielectric layer 3. External electrodes 6a and 6b (FIG. 4) that are electrically connected to the capacitor electrode 2 are provided on both end sides of a laminated element 5 that has a structure in which dummy layers (sheets on which electrodes are not formed) 4 are laminated one above the other. A grounding external electrode 7 which is disposed and which is electrically connected to the grounding electrode 1 so as to go around the central portion of the multilayer element 5
A case of manufacturing a three-terminal type laminated electronic component having a structure in which (FIG. 4) is arranged will be described as an example.

【0014】図1は、この実施例において、積層電子部
品(この実施例では3端子型の積層セラミックコンデン
サ)を製造するのに用いた誘電体シート(電極シート)
を示す平面図である。
FIG. 1 shows a dielectric sheet (electrode sheet) used to manufacture a laminated electronic component (a three-terminal type laminated ceramic capacitor in this embodiment) in this embodiment.
FIG.

【0015】この実施例で用いた誘電体シート(電極シ
ート)(図1)13は、セラミックグリーンシート14
に、積層セラミックコンデンサ(積層電子部品)の第1
の内部電極(アース電極)1となる平行する2本の帯状
電極11a,11bから構成される第1の電極パターン
11を所定の間隔をおいて略平行に複数配設するととも
に、第1の電極パターン11をはさんで互に対向する位
置に、積層電子部品の第2の内部電極(この実施例では
容量電極)2となる第2の電極パターン12を所定のピ
ッチで複数配設することにより形成されており、第2の
電極パターン12の、第1の電極パターン11と直交す
る方向の長さLが、第1の電極パターン11をはさんで
対向する2つの第2の電極パターン12の間隔(ギャッ
プ)Gと略同一になるように構成されている。
The dielectric sheet (electrode sheet) 13 (FIG. 1) used in this example is a ceramic green sheet 14.
The first of the multilayer ceramic capacitors (multilayer electronic components)
A plurality of first electrode patterns 11 composed of two parallel strip-shaped electrodes 11a and 11b which will be internal electrodes (ground electrodes) 1 of the first electrode pattern 11 are arranged substantially parallel to each other at a predetermined interval. By arranging a plurality of second electrode patterns 12 to be the second internal electrodes (capacitor electrodes in this embodiment) 2 of the laminated electronic component at a predetermined pitch, at positions facing each other across the pattern 11. The length L of the formed second electrode pattern 12 in the direction orthogonal to the first electrode pattern 11 is equal to that of the two second electrode patterns 12 that face each other across the first electrode pattern 11. It is configured to be substantially the same as the gap (gap) G.

【0016】そして、図2に示すように、互に隣接する
誘電体シート13及び13(13a)の第1及び第2の
電極パターン11,12の相対位置についてみた場合
に、第2の電極パターン12の位置が、第1の電極パタ
ーン11に略直交する方向(矢印AまたはBの方向に)
に、距離L(すなわち、第1の電極パターン11をはさ
んで対向する2つの第2の電極パターン12の間隔(ギ
ャップ)Gと略同一距離)だけ交互にずれるような態様
で、誘電体シート13,13(13a)を交互に複数枚
積層することにより、一つの誘電体シート13(または
13(13a))に形成された第1の電極パターン11
が、隣接する誘電体シート13(または13(13
a))に形成された第2の電極パターン12と直交する
ような状態で誘電体シート13(または13(13
a))を介して対向し、これが積層方向に交互に繰り返
されているような構造(図3参照)の積層ブロック(図
示せず)を形成する。
Then, as shown in FIG. 2, when the relative positions of the first and second electrode patterns 11 and 12 of the dielectric sheets 13 and 13 (13a) adjacent to each other are examined, the second electrode pattern is formed. The position of 12 is in a direction substantially orthogonal to the first electrode pattern 11 (in the direction of arrow A or B).
And the dielectric sheet is alternately displaced by a distance L (that is, substantially the same distance as a gap G between two second electrode patterns 12 that face each other across the first electrode pattern 11). The first electrode pattern 11 formed on one dielectric sheet 13 (or 13 (13a)) by alternately laminating a plurality of 13 and 13 (13a)
But the adjacent dielectric sheet 13 (or 13 (13
a)) so as to be orthogonal to the second electrode pattern 12 formed on the dielectric sheet 13 (or 13 (13
a)), and a laminated block (not shown) having a structure (see FIG. 3) in which they face each other and are alternately repeated in the laminating direction.

【0017】なお、誘電体シート13及び13(13
a)を、交互に位置をずらせて積層する方法としては、
誘電体シート自体を距離Lだけずらせる方法や、例え
ば、誘電体シート13または13(13a)を180゜
回転させた場合に所定の位置関係になるように、第1及
び第2の電極パターン11,12を所定の位置に配設し
ておき、各誘電体シート13,13(13a)を1層ご
とに180゜回転させて積層することによる方法など、
種々の方法を用いることが可能である。
The dielectric sheets 13 and 13 (13
As a method of stacking a) by alternately shifting the positions,
A method of shifting the dielectric sheet itself by a distance L, or a first and second electrode pattern 11 so that the dielectric sheet 13 or 13 (13a) has a predetermined positional relationship when rotated by 180 °, for example. , 12 are arranged at predetermined positions, and each of the dielectric sheets 13, 13 (13a) is rotated by 180 ° and laminated for each layer.
Various methods can be used.

【0018】それから、積層ブロックを所定の位置(図
2の線C及びDで示す位置)で切断することにより、図
3に示すように、一方の端部から他方の端部に至る第1
の内部電極1と、該第1の内部電極1と略直交する方向
に形成され、一方の端部から他方の端部に至る第2の内
部電極2が、誘電体層3を介して交互に積層された構造
を有する積層素子(3端子型の積層電子部品素子)5が
切り出される。
Then, by cutting the laminated block at a predetermined position (positions shown by lines C and D in FIG. 2), as shown in FIG. 3, a first portion from one end to the other end is obtained.
Internal electrodes 1 and second internal electrodes 2 formed in a direction substantially orthogonal to the first internal electrode 1 and extending from one end to the other end are alternately provided with a dielectric layer 3 interposed therebetween. A laminated element (three-terminal type laminated electronic component element) 5 having a laminated structure is cut out.

【0019】そして、この積層素子5を焼成した後、図
4に示すように、積層素子5の両端側に容量電極2(図
3)と導通する外部電極6a,6bを形成するととも
に、積層素子5の中央部を一周するように、アース電極
1(図3)と導通するアース用外部電極7を配設するこ
とにより、3端子型の積層セラミック電子部品が得られ
る。
After firing the laminated element 5, as shown in FIG. 4, external electrodes 6a and 6b are formed on both ends of the laminated element 5 so as to be electrically connected to the capacitive electrode 2 (FIG. 3), and the laminated element 5 is formed. By arranging the grounding external electrode 7 which is electrically connected to the grounding electrode 1 (FIG. 3) so as to go around the central portion of the circuit 5, a three-terminal type laminated ceramic electronic component can be obtained.

【0020】上述のように、この実施例の製造方法によ
れば、1種類の電極パターンが付与された誘電体シート
を用いて、第1及び第2の内部電極(すなわちアース電
極及び容量電極)が誘電体層を介して交互に積層された
構造を有する個々の素子を複数含有する積層ブロックを
容易に形成することができるとともに、この積層ブロッ
クを所定の位置で切断することにより、3端子型の積層
電子部品(この実施例では3端子型の積層セラミックコ
ンデンサ)を容易かつ効率よく製造することができる。
As described above, according to the manufacturing method of this embodiment, the first and second internal electrodes (that is, the ground electrode and the capacitor electrode) are formed by using the dielectric sheet provided with one kind of electrode pattern. It is possible to easily form a laminated block containing a plurality of individual elements each having a structure in which the layers are alternately laminated via a dielectric layer, and cut the laminated block at a predetermined position to form a three-terminal type. The laminated electronic component (3 terminal type laminated ceramic capacitor in this embodiment) can be manufactured easily and efficiently.

【0021】また、上記実施例では、アース電極となる
第1の電極パターンを、互に近接して配設された2本の
略平行な電極からなる電極パターンとしているので、2
本の略平行な電極(分割電極)からなる内部電極を有す
る積層電子部品を容易かつ効率よく製造することが可能
になる。なお、アース電極を2本の略平行な電極からな
る分割電極とした3端子型の積層コンデンサにおいて
は、ノイズ除去性能が向上するという効果が得られる。
Further, in the above embodiment, the first electrode pattern serving as the ground electrode is an electrode pattern comprising two substantially parallel electrodes arranged close to each other.
It becomes possible to easily and efficiently manufacture a laminated electronic component having an internal electrode composed of substantially parallel electrodes (divided electrodes) of a book. In addition, in the three-terminal type multilayer capacitor in which the ground electrode is a divided electrode composed of two substantially parallel electrodes, the effect of improving the noise removal performance can be obtained.

【0022】但し、本発明は、アース電極となる第1の
電極パターンを、互に近接して配設された2本の略平行
な電極からなるパターンとする場合に限られるものでは
なく、1本の帯状のパターンやさらにその他のパターン
とすることも可能である。
However, the present invention is not limited to the case where the first electrode pattern serving as the ground electrode is a pattern composed of two substantially parallel electrodes arranged close to each other. It is also possible to use a strip-shaped pattern of a book or another pattern.

【0023】また、上記実施例では、3端子型の積層セ
ラミックコンデンサを製造する場合を例にとって説明し
たが、本発明はこれに限らず、さらにその他の3端子型
の積層電子部品を製造する場合にも適用することが可能
である。
In the above embodiment, the case of manufacturing a three-terminal type monolithic ceramic capacitor has been described as an example. However, the present invention is not limited to this, and in the case of manufacturing another three-terminal type monolithic electronic component. Can also be applied to.

【0024】さらに、本発明は、一つの素子の中に複数
のコンデンサ部(容量電極)を備え、かつ、一つのアー
ス電極を共用するアレイタイプのコンデンサの製造方法
にも適用することが可能である。
Further, the present invention can be applied to a method of manufacturing an array type capacitor having a plurality of capacitor parts (capacitance electrodes) in one element and sharing one ground electrode. is there.

【0025】本発明は、さらにその他の点においても上
記実施例に限定されるものではなく、発明の要旨の範囲
内において種々の応用、変形を加えることが可能であ
る。
The present invention is not limited to the above-mentioned embodiments in other points, and various applications and modifications can be made within the scope of the invention.

【0026】[0026]

【発明の効果】上述のように、本発明の積層電子部品の
製造方法は、上記所定の要件を満たすような第1及び第
2の電極パターンを配設した誘電体シートを、所定の態
様で複数枚積層し、これを切断して個々の電子部品素子
を切り出すようにしているので、従来のように、異なる
電極パターンが形成された複数の誘電体シートを用意す
る必要がなくなり、3端子型の積層電子部品を効率よく
製造することが可能になる。
As described above, in the method for manufacturing a laminated electronic component of the present invention, the dielectric sheet provided with the first and second electrode patterns satisfying the above-mentioned predetermined requirements is provided in a predetermined manner. Since a plurality of laminated sheets are cut and the individual electronic component elements are cut out by cutting them, there is no need to prepare a plurality of dielectric sheets having different electrode patterns as in the conventional case, and the three-terminal type It is possible to efficiently manufacture the above laminated electronic component.

【0027】また、前記第1及び第2の電極パターンの
いずれか一方を、互に近接して配設された2本の略平行
な電極から構成することにより、2本の略平行な電極
(分割電極)からなる内部電極を有する積層電子部品を
製造することが可能になる。したがって、2本の略平行
な電極からなる分割電極をアース電極(内部電極)とす
るノイズ除去性能に優れた3端子型の積層コンデンサな
どを効率よく製造することが可能になる。
Further, by constructing one of the first and second electrode patterns from two substantially parallel electrodes arranged close to each other, two substantially parallel electrodes ( It becomes possible to manufacture a laminated electronic component having an internal electrode composed of divided electrodes. Therefore, it is possible to efficiently manufacture a three-terminal type multilayer capacitor or the like, which has a ground electrode (internal electrode), which is a divided electrode composed of two substantially parallel electrodes, and which is excellent in noise removal performance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例において積層電子部品(積層セ
ラミックコンデンサ)を製造するのに用いた誘電体シー
トを示す平面図である。
FIG. 1 is a plan view showing a dielectric sheet used for manufacturing a multilayer electronic component (multilayer ceramic capacitor) in an example of the present invention.

【図2】本発明の実施例において誘電体シートを積層し
たときの電極パターンの重なり状態を示す平面図であ
る。
FIG. 2 is a plan view showing an overlapping state of electrode patterns when dielectric sheets are laminated in an example of the present invention.

【図3】本発明の実施例において誘電体シートを積層し
たときの個々の素子における内部電極(電極パターン)
の配設状態を示す分解斜視図である。
FIG. 3 is an internal electrode (electrode pattern) in each element when dielectric sheets are laminated in an example of the present invention.
FIG. 3 is an exploded perspective view showing an arrangement state of FIG.

【図4】3端子型の積層電子部品(積層セラミックコン
デンサ)の外部構造を示す斜視図である。
FIG. 4 is a perspective view showing an external structure of a three-terminal type multilayer electronic component (multilayer ceramic capacitor).

【図5】一般的な3端子型の積層電子部品(積層セラミ
ックコンデンサ)の内部電極の配設状態を示す分解斜視
図である。
FIG. 5 is an exploded perspective view showing an arrangement state of internal electrodes of a general three-terminal type multilayer electronic component (multilayer ceramic capacitor).

【図6】(a),(b)は、従来の積層電子部品(積層セラ
ミックコンデンサ)の製造に用いられている誘電体シー
トを示す平面図である。
6A and 6B are plan views showing a dielectric sheet used for manufacturing a conventional laminated electronic component (multilayer ceramic capacitor).

【符号の説明】[Explanation of symbols]

1 第1の内部電極(アース電極) 2 第2の内部電極(容量電極) 3 誘電体層 5 積層素子 6a,6b 外部電極 7 アース用外部電極 11a,11b 帯状電極 11 第1の電極パターン 12 第2の電極パターン 13,13a 誘電体シート(電極シート) 14 セラミックグリーンシート 1 1st internal electrode (ground electrode) 2 2nd internal electrode (capacitance electrode) 3 Dielectric layer 5 Laminated elements 6a, 6b External electrode 7 Grounding external electrodes 11a, 11b Strip electrode 11 First electrode pattern 12th 2 electrode pattern 13,13a Dielectric sheet (electrode sheet) 14 Ceramic green sheet

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 一方の端部から他方の端部に至る第1の
内部電極と、前記第1の内部電極と略直交する方向に形
成され、一方の端部から他方の端部に至る第2の内部電
極が、誘電体層を介して交互に積層された構造を有する
3端子型の積層電子部品の製造方法であって、 前記積層電子部品の第1の内部電極となる第1の電極パ
ターンが所定の間隔をおいて略平行に複数配設されてい
るとともに、前記第1の電極パターンをはさんで互に対
向する位置に、前記積層電子部品の第2の内部電極とな
る第2の電極パターンが所定のピッチで複数配設され、
かつ第2の電極パターンの前記第1の電極パターンと直
交する方向の長さが、前記第1の電極パターンをはさん
で対向する2つの第2の電極パターンの間隔と略同一で
ある誘電体シートを形成する工程と、 前記誘電体シートを複数枚積層して所定の位置で切断す
ることにより個々の電子部品素子を切り出したときに、
前記第1及び第2の電極パターンが、個々の電子部品素
子において前記第1及び第2の内部電極を構成するよう
に、互に隣接する誘電体シートのうちの一方の誘電体シ
ートの第1の電極パターンが、他方の誘電体シートの第
2の電極パターンに、また、一方の誘電体シートの第2
の電極パターンが、他方の誘電体シートの第1の電極パ
ターンに、誘電体シートを介して直交するような状態で
重なり合うように、所定の位置関係で誘電体シートを複
数枚積層することにより積層ブロックを形成する工程
と、 前記積層ブロックを所定の位置で切断することにより、
前記第1及び第2の内部電極が誘電体層を介して交互に
積層された構造を有する個々の電子部品素子を切り出す
工程とを具備することを特徴とする積層電子部品の製造
方法。
1. A first internal electrode extending from one end to the other end and a first internal electrode formed in a direction substantially orthogonal to the first internal electrode and extending from one end to the other end. A method of manufacturing a three-terminal type laminated electronic component having a structure in which two internal electrodes are alternately laminated via a dielectric layer, the first electrode being a first internal electrode of the laminated electronic component. A plurality of patterns are arranged substantially parallel to each other at a predetermined interval, and a second internal electrode of the laminated electronic component is provided at a position facing each other across the first electrode pattern. A plurality of electrode patterns of are arranged at a predetermined pitch,
And the dielectric in which the length of the second electrode pattern in the direction orthogonal to the first electrode pattern is substantially the same as the interval between the two second electrode patterns that face each other across the first electrode pattern. A step of forming a sheet, and when cutting out individual electronic component elements by stacking a plurality of the dielectric sheets and cutting at a predetermined position,
The first and second electrode patterns are formed so as to form the first and second internal electrodes in the individual electronic component elements, and the first dielectric sheet of one of the dielectric sheets adjacent to each other is formed. Of the second electrode pattern of the other dielectric sheet and the second electrode pattern of the other dielectric sheet.
By laminating a plurality of dielectric sheets in a predetermined positional relationship so that the electrode pattern of is overlapped with the first electrode pattern of the other dielectric sheet in a state of being orthogonal to each other through the dielectric sheet. A step of forming a block, and by cutting the laminated block at a predetermined position,
And a step of cutting out individual electronic component elements having a structure in which the first and second internal electrodes are alternately laminated with a dielectric layer in between, and a method of manufacturing a laminated electronic component.
【請求項2】 前記第1及び第2の内部電極のうち、ア
ース用の電極となる方の内部電極が、互に近接する2本
の略平行な電極から構成されており、かつ、前記第1及
び第2の電極パターンのいずれか一方が、前記2本の略
平行な電極からなる内部電極を構成することができるよ
うに、互に近接して配設された2本の略平行な電極から
構成されていることを特徴とする請求項1記載の積層電
子部品の製造方法。
2. The one of the first and second internal electrodes, which serves as an electrode for grounding, is composed of two substantially parallel electrodes that are close to each other, and Two substantially parallel electrodes arranged close to each other so that one of the first and second electrode patterns can form an internal electrode composed of the two substantially parallel electrodes. The method for manufacturing a laminated electronic component according to claim 1, wherein
JP19219794A 1994-07-22 1994-07-22 Manufacturing method of laminated electronic component Expired - Lifetime JP3610985B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19219794A JP3610985B2 (en) 1994-07-22 1994-07-22 Manufacturing method of laminated electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19219794A JP3610985B2 (en) 1994-07-22 1994-07-22 Manufacturing method of laminated electronic component

Publications (2)

Publication Number Publication Date
JPH0837129A true JPH0837129A (en) 1996-02-06
JP3610985B2 JP3610985B2 (en) 2005-01-19

Family

ID=16287299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19219794A Expired - Lifetime JP3610985B2 (en) 1994-07-22 1994-07-22 Manufacturing method of laminated electronic component

Country Status (1)

Country Link
JP (1) JP3610985B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010080745A (en) * 2008-09-26 2010-04-08 Tdk Corp Method for manufacturing feedthrough capacitor
JP2010097994A (en) * 2008-10-14 2010-04-30 Tdk Corp Method of manufacturing laminated feedthrough capacitor
US9922765B2 (en) 2013-10-28 2018-03-20 Murata Manufacturing Co., Ltd. Manufacturing method for laminated electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010080745A (en) * 2008-09-26 2010-04-08 Tdk Corp Method for manufacturing feedthrough capacitor
JP2010097994A (en) * 2008-10-14 2010-04-30 Tdk Corp Method of manufacturing laminated feedthrough capacitor
US9922765B2 (en) 2013-10-28 2018-03-20 Murata Manufacturing Co., Ltd. Manufacturing method for laminated electronic component

Also Published As

Publication number Publication date
JP3610985B2 (en) 2005-01-19

Similar Documents

Publication Publication Date Title
KR20080055697A (en) Feedthrough capacitor array
JP2003051729A (en) Layered filter array
JPH08124795A (en) Multilayered capacitor
KR19990036692A (en) Piezoelectric Resonators and Electronic Components Using the Same
JPH09153433A (en) Manufacture of laminated electronic component
JPH11204314A (en) Laminated electronic component array
JPH0837129A (en) Production of monolithic electronic parts
JP2000277382A (en) Multi-laminated ceramic capacitor and manufacturing method of the same
JPH08273973A (en) Method for manufacturing laminated ceramic electronic component
JPH08124800A (en) Capacitor array
JP2784863B2 (en) Multilayer capacitors
JP2003272945A (en) Laminated ceramic electronic component and its manufacturing method
JP3786243B2 (en) Manufacturing method of laminated electronic component
JPH03178112A (en) Compound chip part
JP2784862B2 (en) Multilayer capacitors
JPH11354326A (en) Laminated inductor and its manufacture
JPH0897603A (en) Laminated dielectric filter
JP3642462B2 (en) Manufacturing method of laminated parts
JPH0440265Y2 (en)
US6215228B1 (en) Stacked piezoelectric resonator, characteristics-adjusting method thereof, and ladder-type filter including the same
JP2001044059A (en) Multilayer ceramic capacitor
JP2000294452A (en) Laminated ceramic electronic part array and manufacture thereof
JP2781095B2 (en) Method for manufacturing surface mount components
JPH04139710A (en) Laminated ceramic capacitor and manufacture thereof
JPH0660134U (en) Multilayer chip EMI removal filter

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20020226

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040806

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041012

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071029

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081029

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091029

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101029

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101029

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111029

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121029

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131029

Year of fee payment: 9

EXPY Cancellation because of completion of term