JP2000277382A - Multi-laminated ceramic capacitor and manufacturing method of the same - Google Patents

Multi-laminated ceramic capacitor and manufacturing method of the same

Info

Publication number
JP2000277382A
JP2000277382A JP8582399A JP8582399A JP2000277382A JP 2000277382 A JP2000277382 A JP 2000277382A JP 8582399 A JP8582399 A JP 8582399A JP 8582399 A JP8582399 A JP 8582399A JP 2000277382 A JP2000277382 A JP 2000277382A
Authority
JP
Japan
Prior art keywords
internal electrode
layer
ceramic capacitor
electrodes
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8582399A
Other languages
Japanese (ja)
Inventor
Takeki Kamata
雄樹 鎌田
Satoshi Endo
悟司 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8582399A priority Critical patent/JP2000277382A/en
Publication of JP2000277382A publication Critical patent/JP2000277382A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable muti-laminated ceramic capacitor which has a large effective area for internal electrodes, is free of capacitance loss, and is superior in thermal shock resistance, and a method of manufacturing the same. SOLUTION: A multi-laminated ceramic capacitor is formed by alternately laminating an internal electrode layer 2, in which each internal electrode 2a is provided with a connecting part 4 at one of the edges of each internal electrode 2a and a dielectric ceramic layer 1 repeatedly to form a plurality of laminated layers which are sintered. In the sintered body, in which a plurality of capacitor elements are integrated side by side, pairs of outer electrodes 5 are formed on the opposed side surfaces, wherein the number of pairs corresponds to the number of the capacitor elements. The edge of each connecting part 4 is exposed on the respective opposed outer surface alternately on every other layer across each dielectric layer in the laminated direction, and the internal electrodes 2a are electrically connected to respective outer electrodes 5 via exposed edges of the connecting parts 4. Here, the widths of the inner electrodes 2a, connecting parts 4 and outer electrodes 5 are such that they satisfy those relation: inner electrode 2a > outer electrode 5 > connecting part 4, and the film thickness of the connecting parts 4 is larger than that of the internal electrodes 2a, and moreover the connecting boundary part between the inner electrode 2a and the connecting part 4 are constituted of circular arc shapes 6.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は各種電子機器に利用
される多連型積層セラミックコンデンサ及びその製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor used for various electronic devices and a method of manufacturing the same.

【0002】[0002]

【従来の技術】昨今のコンピュータや携帯電話に代表さ
れる情報通信機器の小型化に伴い、電子部品の高密度実
装化が進行する中で積層セラミックコンデンサにおいて
も小型化、大容量化が望まれている。また実装面積を低
減するために積層コンデンサを単一素体内に複数個並設
した多連型積層セラミックコンデンサが市場から要望さ
れている。
2. Description of the Related Art With the recent miniaturization of information communication devices such as computers and mobile phones, high-density mounting of electronic components has been progressing, and miniaturization and large capacity of multilayer ceramic capacitors have been desired. ing. In order to reduce the mounting area, a multi-layered multilayer ceramic capacitor in which a plurality of multilayer capacitors are juxtaposed in a single body is demanded from the market.

【0003】従来の多連型積層セラミックコンデンサ8
は図4から図6に示すように、外部電極5の幅より狭
く、その平面方向の厚みがほぼ均一な内部電極層2と誘
電体セラミック層1を交互に複数層積層した構造となっ
ていた。また、外部電極5の幅は、多連型積層セラミッ
クコンデンサ8を回路基板に実装した際に、隣り合う外
部電極5間で半田等による短絡を防止するため、その幅
が規格化されている。
[0003] Conventional multi-layer monolithic ceramic capacitor 8
4 to 6, as shown in FIGS. 4 to 6, had a structure in which a plurality of internal electrode layers 2 and dielectric ceramic layers 1 having a width smaller than the width of the external electrode 5 and substantially uniform in the planar direction were alternately laminated. . The width of the external electrodes 5 is standardized in order to prevent a short circuit between adjacent external electrodes 5 due to soldering or the like when the multiple-layer ceramic capacitor 8 is mounted on a circuit board.

【0004】以下に従来の多連型積層セラミックコンデ
ンサ8及びその製造方法について図4から図6を参照し
ながら説明する。
Hereinafter, a conventional multiple-layer ceramic capacitor 8 and a method of manufacturing the same will be described with reference to FIGS.

【0005】先ず、チタン酸バリウムを主成分とする誘
電体セラミック粉末と、有機バインダー等からなるスラ
リーをドクターブレード法によりキャリアフィルム上に
塗布後乾燥し、誘電体セラミック層1のグリーンシート
を作製する。
First, a slurry comprising a dielectric ceramic powder containing barium titanate as a main component and an organic binder or the like is applied on a carrier film by a doctor blade method and then dried to produce a green sheet of the dielectric ceramic layer 1. .

【0006】次に、グリーンシートを所定枚数、加熱積
層を繰返し無効層3ブロックを作製する。
[0006] Next, a predetermined number of green sheets are repeatedly heated and laminated to produce three blocks of invalid layers.

【0007】次いで、無効層3のブロック面にパラジウ
ム等の金属粉末を主成分とする電極ペーストをスクリー
ン印刷等により、同一平面に複数個の内部電極層2を形
成した第一層目の内部電極層2を形成する。続いて第一
層目の内部電極層2面にグリーンシートを積層した後第
二層目の内部電極層2を印刷形成する。更に第二層目の
内部電極層2面にグリーンシートを積層した後第三層目
の内部電極層2を印刷形成する。
Next, an electrode paste mainly composed of a metal powder such as palladium is screen-printed on the block surface of the ineffective layer 3 by screen printing or the like to form a plurality of internal electrode layers 2 on the same plane. The layer 2 is formed. Subsequently, a green sheet is laminated on the surface of the first internal electrode layer 2, and then the second internal electrode layer 2 is formed by printing. Further, after a green sheet is laminated on the surface of the second internal electrode layer 2, the third internal electrode layer 2 is formed by printing.

【0008】このようにしてグリーンシートと内部電極
層2を交互に所定数積層した後、最後に無効層3のブロ
ックを積層し多連型積層セラミックコンデンサ用の積層
体グリーンブロック(図示せず)を作製する。この時、
内部電極層2の厚みは平面方向に均一となるように形成
すると共に、偶数層目の内部電極層2は奇数層目の内部
電極層2に対し、印刷した内部電極層2の長手方向に所
定寸法ずらしグリーンシートを挟んでそれぞれが対にな
るように印刷を行う。
After a predetermined number of green sheets and internal electrode layers 2 are alternately laminated in this manner, finally, a block of an ineffective layer 3 is laminated to form a laminated green block (not shown) for a multi-layered multilayer ceramic capacitor. Is prepared. At this time,
The thickness of the internal electrode layer 2 is formed so as to be uniform in the plane direction, and the even-numbered internal electrode layer 2 has a predetermined length in the longitudinal direction of the printed internal electrode layer 2 with respect to the odd-numbered internal electrode layer 2. Printing is performed so that each of the green sheets is a pair with the green sheets shifted in dimension.

【0009】その後、グリーン積層体を所定寸法に切
断、分離し複数個のコンデンサ素子を並設した多連型積
層セラミックコンデンサ8のグリーンチップを作製す
る。得られたグリーンチップは、コンデンサ素子毎に内
部電極層2の一方の端部が誘電体セラミック層1のグリ
ーンシートを挟んで一層おき交互に相対向する側面に複
数群等間隔に露出した構造となっている。
Thereafter, the green laminate is cut into predetermined dimensions and separated to produce a green chip of a multiple-layer ceramic capacitor 8 in which a plurality of capacitor elements are juxtaposed. The obtained green chip has a structure in which one end of the internal electrode layer 2 is provided for each capacitor element and one side of the green sheet of the dielectric ceramic layer 1 is alternately exposed on opposite side surfaces at equal intervals. Has become.

【0010】次に、グリーンチップを脱脂後、所定温度
で焼成し多連型積層セラミックコンデンサ8の焼結体
(図示せず)を作製する。
Next, after the green chip is degreased, it is fired at a predetermined temperature to produce a sintered body (not shown) of the multilayer ceramic capacitor 8.

【0011】次いで、内部に複数個のコンデンサ素子を
並設した焼結体の内部電極層2が露出した相対向する側
面に、内部電極層2と電気的に接続する外部電極5をコ
ンデンサ素子に対応し複数対設け、多連型積層セラミッ
クコンデンサ8を完成させる。
Next, external electrodes 5 electrically connected to the internal electrode layers 2 are formed on the opposing side surfaces of the sintered body in which a plurality of capacitor elements are juxtaposed to expose the internal electrode layers 2 to the capacitor elements. Correspondingly, a plurality of pairs are provided to complete the multilayer ceramic capacitor 8.

【0012】[0012]

【発明が解決しようとする課題】しかしながら上記従来
の方法では、焼結体の相対向する側面に露出した内部電
極層2の一方の端部と電気的に接続する外部電極5を形
成する際、隣合う外部電極5間の短絡を防止し、しかも
露出した内部電極層2の端部全体を覆うように形成する
ことが困難で、内部電極層2が外部電極5よりはみ出す
不良が発生し、完成品歩留を低下させるという問題があ
った。
However, in the above-mentioned conventional method, when forming the external electrode 5 electrically connected to one end of the internal electrode layer 2 exposed on the opposite side surface of the sintered body, It is difficult to prevent a short circuit between the adjacent external electrodes 5 and to form the internal electrode layer 2 so as to cover the entire end of the exposed internal electrode layer 2. There was a problem that the product yield was reduced.

【0013】また、図4に示すように外部電極5の幅よ
りも狭い内部電極層2は有効面積が小さくなり、誘電体
セラミック層1の積層数を同じにした場合コンデンサ素
子の大容量化には不利となる。この対応策として有効面
積を大きくするために内部電極層2の幅を広くすると、
これに接続する外部電極5の幅が広くなり、隣合うコン
デンサ素子の外部電極5との間隔が狭くなり電気的に短
絡するおそれがあり、これを精度よく形成しないと内部
電極層2の露出部が外部電極5からはみ出したりするた
め作業性を極めて低下させるという問題があった。
Further, as shown in FIG. 4, the effective area of the internal electrode layer 2 which is smaller than the width of the external electrode 5 becomes small, and when the number of laminated dielectric ceramic layers 1 is the same, the capacity of the capacitor element can be increased. Is disadvantageous. As a countermeasure, if the width of the internal electrode layer 2 is increased to increase the effective area,
The width of the external electrode 5 connected thereto becomes large, the interval between the external electrodes 5 of the adjacent capacitor elements becomes narrow, and there is a possibility that an electrical short circuit occurs. However, there is a problem that the workability is extremely reduced because the material protrudes from the external electrode 5.

【0014】[0014]

【課題を解決するための手段】前記課題を解決するため
に本発明は、同一平面に複数個形成した内部電極層と誘
電体セラミック層とを交互に複数層積層、焼成して単一
素体内に複数個のコンデンサ素子を並設した焼結体の相
対向する側面にコンデンサ素子に対応する複数対の外部
電極を設けた多連型積層セラミックコンデンサにおい
て、前記内部電極層の一方の端部を積層方向に前記誘電
体セラミック層を挟んで一層おきに交互に相対向する側
面に露出させると共に、前記内部電極の一方の端部に、
これを介して前記外部電極と電気的に接続する接続部を
設け、この接続部の幅を前記内部電極の幅及び前記外部
電極の幅より狭く構成することにより作業性の向上と信
頼性に富んだものが得られるものである。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to a single element body in which a plurality of internal electrode layers and dielectric ceramic layers formed on the same plane are alternately laminated and fired. In a multiple-layer monolithic ceramic capacitor in which a plurality of pairs of external electrodes corresponding to capacitor elements are provided on opposing side surfaces of a sintered body in which a plurality of capacitor elements are juxtaposed, one end of the internal electrode layer is Along with being exposed on alternately facing side surfaces alternately with the dielectric ceramic layer interposed therebetween in the stacking direction, and at one end of the internal electrode,
A connection portion electrically connected to the external electrode is provided through the connection portion, and the width of the connection portion is smaller than the width of the internal electrode and the width of the external electrode, thereby improving workability and enhancing reliability. Is what you get.

【0015】[0015]

【発明の実施の形態】本発明の請求項1に記載の発明
は、同一平面に形成した複数個の内部電極層と誘電体セ
ラミック層とを交互に複数層積層、焼成して複数個のコ
ンデンサ素子を単一素体内に並設した焼結体の相対向す
る側面に前記コンデンサ素子の数に対応する複数対の外
部電極を設けた多連型積層セラミックコンデンサにおい
て、前記内部電極層は内部電極の一方の端部に接続部を
設け、その接続部の端部を前記誘電体セラミック層を挟
んで積層方向に一層おきに交互に相対向する側面に露出
させるとともに、接続部を介して内部電極を前記外部電
極と電気的に接続させ、接続部の幅は前記内部電極の幅
及び前記外部電極の幅より狭く構成したものであり、内
部電極及び外部電極の幅より狭い接続部を設けることに
よって、内部電極の幅を広くしても外部電極の幅を内部
電極層の幅に合わせることなく、接続部の幅より広く外
部電極を形成することで接続部のはみだしを防ぐと共
に、隣合うコンデンサ素子の外部電極の間隔が広くな
り、お互いの短絡が防止できる外部電極を容易に形成す
ることができるという作用を有するものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a plurality of capacitors are formed by alternately laminating and firing a plurality of internal electrode layers and a dielectric ceramic layer formed on the same plane. In a multiple-layered multilayer ceramic capacitor in which a plurality of pairs of external electrodes corresponding to the number of the capacitor elements are provided on opposing side surfaces of a sintered body in which elements are juxtaposed in a single element body, the internal electrode layer is an internal electrode. A connection portion is provided at one end of the substrate, and the end portion of the connection portion is alternately exposed on the side opposite to each other alternately in the stacking direction with the dielectric ceramic layer interposed therebetween, and the internal electrode is connected via the connection portion. Is electrically connected to the external electrode, and the width of the connection portion is configured to be smaller than the width of the internal electrode and the width of the external electrode, and by providing a connection portion narrower than the width of the internal electrode and the external electrode. Of the internal electrode Even if the width of the external electrode is wider than the width of the internal electrode layer, forming the external electrode wider than the width of the connection part prevents the connection part from protruding, and also sets the distance between the external electrodes of adjacent capacitor elements. Has an effect that external electrodes that can prevent short circuit between each other can be easily formed.

【0016】本発明の請求項2に記載の発明は、内部電
極の幅を外部電極の幅よりも広く構成したものであり、
これによって内部電極の幅を外部電極の幅よりも広く有
効面積を大きくしても、請求項1で説明したように内部
電極の幅より狭い接続部を介しこれより幅の広い外部電
極と接続させるため、接続部が外部電極よりはみ出させ
ることがなく、また隣合う外部電極どうしの短絡を防止
することができる外部電極を容易に形成することがで
き、しかも内部電極と外部電極の電気的導通を確保した
多連型積層セラミックコンデンサの大容量化を可能にす
るという作用を有するものである。
According to a second aspect of the present invention, the width of the internal electrode is wider than the width of the external electrode.
Accordingly, even if the width of the internal electrode is wider than the width of the external electrode and the effective area is increased, the internal electrode is connected to the external electrode wider than the internal electrode through the connection portion smaller than the width of the internal electrode. Therefore, it is possible to easily form an external electrode that does not protrude the connection portion from the external electrode, and that can prevent a short circuit between adjacent external electrodes, and furthermore, establishes electrical continuity between the internal electrode and the external electrode. This has the function of increasing the capacity of the secured multilayer ceramic capacitor.

【0017】本発明の請求項3に記載の発明は、内部電
極と接続部の接続境界部を円弧状にしたものであり、幅
の異なる内部電極と接続部との接続境界部を円弧状にす
ることにより、完成品を回路基板に半田付けする際に接
続境界部に熱応力の集中を避けサーマルショックによる
焼結体内部のクラックの発生を抑制することが可能とな
るものである。
According to a third aspect of the present invention, the connection boundary between the internal electrode and the connection portion is formed in an arc shape, and the connection boundary between the internal electrode and the connection portion having different widths is formed in an arc shape. By doing so, it is possible to avoid concentration of thermal stress at the connection boundary when soldering the finished product to the circuit board, and to suppress the occurrence of cracks inside the sintered body due to thermal shock.

【0018】本発明の請求項4に記載の発明は、接続部
の厚さを内部電極の厚さより厚く形成したものであり、
接続部の厚さを内部電極の厚さより厚く形成することに
より接続部の断面積が大きくなり、外部電極と接続する
接続部の幅を狭くしても両者の接続が確実となり容量抜
けの防止や内部電極と外部電極との接触抵抗を低減させ
る効果を有するものであるとするものである。
According to a fourth aspect of the present invention, the connection portion is formed to be thicker than the internal electrode.
By making the thickness of the connection part thicker than the thickness of the internal electrode, the cross-sectional area of the connection part becomes large, and even if the width of the connection part to be connected to the external electrode is made narrow, the connection between the two is ensured, and the loss of capacity can be prevented. It has an effect of reducing the contact resistance between the internal electrode and the external electrode.

【0019】本発明の請求項5に記載の発明は、同一平
面に複数個の内部電極とこれに接続した接続部の形成す
るスクリーン印刷版に、接続部分を内部電極部分の開口
率、紗厚または乳剤厚みの少なくとも一つを替えたスク
リーン印刷版を用い、内部電極部より接続部を厚く印刷
形成した内部電極層と誘電体セラミック層を複数層積
層、焼成した焼結体の接続部が露出した相対向する側面
に接続部を介して内部電極層と電気的に接続する外部電
極を形成する製造方法であり、これによって形成された
接続部は外部電極との接続が確実となり、容量抜けの防
止や内部電極と外部電極との接触抵抗を低減させた優れ
た性能の多連型積層セラミックコンデンサの作製を容易
にすることが可能となるものである。
According to a fifth aspect of the present invention, there is provided a screen printing plate in which a plurality of internal electrodes and a connection portion connected thereto are formed on the same plane. Alternatively, using a screen printing plate in which at least one of the emulsion thicknesses is changed, a plurality of internal electrode layers and a dielectric ceramic layer are formed by printing the connection portion thicker than the internal electrode portion, and the connection portion of the fired sintered body is exposed. Is a method of forming external electrodes electrically connected to the internal electrode layer via the connection portions on the opposite side surfaces, and the connection portions formed by this are reliably connected to the external electrodes, and the capacity loss is caused. This makes it possible to easily manufacture a multi-layer type multilayer ceramic capacitor having excellent performance, which prevents or reduces the contact resistance between the internal electrode and the external electrode.

【0020】以下、本発明の一実施の形態について図1
から図3を用いて説明する。
FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG.

【0021】図1は本発明の一実施の形態の多連型積層
セラミックコンデンサ7の上面図、図2は同側面断面
図、図3は同正面図である。図において1は誘電体セラ
ミック層、2は内部電極層、2aは内部電極、3は無効
層、4は接続部、5は外部電極、6は内部電極2と接続
部4の接続境界部に形成する円弧、7は多連型積層セラ
ミックコンデンサを示す。
FIG. 1 is a top view of a multilayer ceramic capacitor 7 according to an embodiment of the present invention, FIG. 2 is a side sectional view of the same, and FIG. 3 is a front view of the same. In the figure, 1 is a dielectric ceramic layer, 2 is an internal electrode layer, 2a is an internal electrode, 3 is an ineffective layer, 4 is a connection part, 5 is an external electrode, and 6 is a connection boundary between the internal electrode 2 and the connection part 4. The circle 7 indicates a multiple-layer ceramic capacitor.

【0022】先ず、チタン酸バリウムを主成分とする誘
電体セラミック粉末と、有機バインダ、可塑剤及び有機
溶剤をそれぞれ所定量混合してスラリーを作製する。次
に、ドクターブレード法によりキャリアフィルム上にス
ラリーを塗布後乾燥し誘電体セラミック層1のグリーン
シートを作製する。
First, a predetermined amount of dielectric ceramic powder containing barium titanate as a main component, an organic binder, a plasticizer, and an organic solvent are mixed to prepare a slurry. Next, a slurry is applied to the carrier film by a doctor blade method and then dried to produce a green sheet of the dielectric ceramic layer 1.

【0023】次いで、グリーンシートを所定枚数、積
層、加熱圧着し無効層3ブロックを作製する。その後、
無効層3のブロック面にパラジウムを主成分とする電極
ペーストをスクリーン印刷法により、同一平面に複数個
の内部電極2aとその一方の端部に接続部4を形成した
第一層の内部電極層2を印刷形成する。続いて第一層目
の内部電極層2面にグリーンシートを積層した後、第二
層目の内部電極層2を印刷形成する。更に第二層目の内
部電極層2面にグリーンシートを積層した後第三層目の
内部電極層2を印刷形成する。
Next, a predetermined number of green sheets are laminated and heat-pressed to prepare three blocks of invalid layers. afterwards,
A first internal electrode layer in which a plurality of internal electrodes 2a and connection portions 4 are formed at one end thereof on the same plane by a screen printing method using an electrode paste containing palladium as a main component on the block surface of the ineffective layer 3. 2 is formed by printing. Subsequently, after laminating a green sheet on the surface of the first internal electrode layer 2, the second internal electrode layer 2 is formed by printing. Further, after a green sheet is laminated on the surface of the second internal electrode layer 2, the third internal electrode layer 2 is formed by printing.

【0024】このようにしてグリーンシートと内部電極
層2を交互に所定数積層した後、最後に無効層3ブロッ
クを積層し多連型セラミックコンデンサ用の積層体グリ
ーンブロック(図示せず)を作製する。この時スクリー
ン印刷版は(表1)に示すように接続部4の幅が0.1
50mm、内部電極2aの幅が0.200,0.500
mmまたは内部電極2aの厚さが1.5μm、接続部4
の厚さが1.5,2.0μm、内部電極2aと接続部4
との接続境界部の円弧6の曲率半径0,0.025,
0.100mmとなるものを用いた。
After a predetermined number of green sheets and internal electrode layers 2 are alternately stacked in this way, three blocks of ineffective layers are finally stacked to produce a stacked green block (not shown) for a multiple ceramic capacitor. I do. At this time, as shown in Table 1, the screen printing plate has a width of the connecting portion 4 of 0.1.
50 mm, the width of the internal electrode 2a is 0.200, 0.500
mm or the thickness of the internal electrode 2a is 1.5 μm,
Of the internal electrode 2a and the connecting portion 4
Radius of curvature of the arc 6 at the boundary of the connection with 0, 0.025,
One having a thickness of 0.100 mm was used.

【0025】尚、内部電極2aと接続部4はスクリーン
印刷版の乳剤の厚さを部分的にコントロールしたものを
用いて印刷を行った。また、偶数層目の内部電極層2は
奇数層目の内部電極層2に対し、印刷した内部電極層2
の長手方向に所定寸法ずらしグリーンシートを挟んでそ
れぞれが対になるように印刷を行う。
The internal electrodes 2a and the connection portions 4 were printed by using a screen printing plate in which the emulsion thickness was partially controlled. The even-numbered internal electrode layer 2 is different from the odd-numbered internal electrode layer 2 by the printed internal electrode layer 2.
Are printed so as to form a pair with the green sheets shifted by a predetermined dimension in the longitudinal direction.

【0026】[0026]

【表1】 [Table 1]

【0027】次に、グリーン積層体を所定寸法に切断、
分離し四個のコンデンサ素子を並設した多連型積層セラ
ミックコンデンサ7のグリーンチップを作製する。得ら
れたグリーンチップは、コンデンサ素子毎に内部電極層
2の一方の端部に接続した接続部4が誘電体セラミック
層1のグリーンシートを挟んで一層おきに交互に相対向
する側面に複数群等間隔に露出した構造となっている。
Next, the green laminate is cut into predetermined dimensions.
A green chip of a multiple-layer ceramic capacitor 7 having four separated capacitor elements arranged in parallel is manufactured. In the obtained green chip, a plurality of connecting portions 4 connected to one end of the internal electrode layer 2 are alternately opposed to each other across the green sheet of the dielectric ceramic layer 1 for each capacitor element. The structure is exposed at equal intervals.

【0028】次いで、グリーンチップを脱脂後、所定温
度で焼成し多連型積層セラミックコンデンサ7の焼結体
(図示せず)を作製する。その後、内部に四個のコンデ
ンサ素子を並設した焼結体の接続部4が露出した相対向
する側面に、接続部4を介して内部電極2aと電気的に
接続する外部電極5を四個のコンデンサ素子に対応し四
対設け、図1に示すような多連型積層セラミックコンデ
ンサ7を完成させた。
Next, the green chip is degreased and fired at a predetermined temperature to produce a sintered body (not shown) of the multilayer ceramic capacitor 7. Thereafter, four external electrodes 5 electrically connected to the internal electrodes 2a via the connection portions 4 are provided on opposite side surfaces where the connection portions 4 of the sintered body in which four capacitor elements are juxtaposed are exposed. In this case, four pairs were provided in correspondence with the above-mentioned capacitor elements to complete a multiple-layer ceramic capacitor 7 as shown in FIG.

【0029】本実施の形態において作製した四連型積層
セラミックコンデンサは外形寸法が縦3.2×横1.6
×高さ0.85mmで、接続部4が露出した相対向する
側面に幅0.4mmの外部電極5を0.4mmの外部電
極5を0.4mm間隔で形成した。
The external dimensions of the quadruple-type multilayer ceramic capacitor manufactured in this embodiment are 3.2 × 1.6.
× External electrodes 5 having a height of 0.85 mm and a width of 0.4 mm were formed at opposing side surfaces where the connecting portions 4 were exposed, and external electrodes 5 having a width of 0.4 mm were formed at intervals of 0.4 mm.

【0030】作製したそれぞれの多連型積層セラミック
コンデンサ7について接続部4の外部電極5からのはみ
出しと、従来方法で作成した多連型積層セラミックコン
デンサ8の内部電極層2の外部電極5からのはみ出しの
外部電極5の形成不良率及び従来品の内部電極層2の幅
を0.200mmとしたときの内部電極の有効面積10
0とした時の本実施の形態の内部電極の有効面積比、更
にハンダ付け時のサーマルショックによるクラックの発
生率、外部電極5と接続部4及び内部電極層2の接続不
良による静電容量不良の発生率を評価し、その結果を併
せて(表1)に示した。
Each of the manufactured multilayer ceramic capacitors 7 protrudes from the external electrode 5 of the connecting portion 4 and the external electrode 5 of the internal electrode layer 2 of the multilayer ceramic capacitor 8 manufactured by the conventional method. The defective formation rate of the protruding external electrode 5 and the effective area 10 of the internal electrode when the width of the internal electrode layer 2 of the conventional product is 0.200 mm
0, the effective area ratio of the internal electrodes according to the present embodiment, the rate of occurrence of cracks due to thermal shock during soldering, and the poor capacitance due to poor connection between the external electrodes 5 and the connection portions 4 and the internal electrode layer 2 Was evaluated, and the results are shown in Table 1 together.

【0031】(表1)に示すように、従来品と比較した
本発明品は接続部4のはみ出しによる外部電極5の形成
不良率が非常に少ない。また、内部電極の有効面積が本
発明においては従来品の2.5倍となり静電容量が大き
くなる。更に、静電容量不良は接続部4の厚さを内部電
極2aと同じ1.5μmにした場合、外部電極5と接続
部4との接続幅が小さくなるがサーマルクラックや容量
抜けなどが低減できた。また、接続部4の厚さを2μm
にすると静電容量不良の発生は極めて少なくなり、更に
内部電極2aと接続部4との接続境界を円弧状にするこ
とでサーマルショックによるクラックの発生が皆無とな
ることが分かる。
As shown in Table 1, the product of the present invention has a very low rate of defective formation of the external electrode 5 due to the protrusion of the connection portion 4 as compared with the conventional product. In the present invention, the effective area of the internal electrode is 2.5 times that of the conventional product, and the capacitance is increased. Further, when the thickness of the connection portion 4 is set to 1.5 μm, which is the same as the thickness of the internal electrode 2a, the connection width between the external electrode 5 and the connection portion 4 becomes small, but thermal cracks and loss of capacitance can be reduced. Was. Further, the thickness of the connection part 4 is 2 μm.
It can be seen that the occurrence of the capacitance failure is extremely reduced, and that the cracks due to the thermal shock are completely eliminated by making the connection boundary between the internal electrode 2a and the connection portion 4 arc-shaped.

【0032】尚、本実施の形態において縦3.2,横
1.6、高さ0.85mmの4個のコンデンサ素子を並
設した多連型積層セラミックコンデンサ7について述べ
たが、これ以外の外形寸法まはたはコンデンサ素子の並
設数においても有効である。また、内部電極2aと接続
部4の厚み差を設けるためスクリーン印刷版の乳剤厚み
をコントロールしたが、紗厚みや開口率等を変化させて
膜厚を制御することも可能であると共に、スクリーン印
刷に替えて凹版印刷等の他の方法を用いることもでき
る。
In this embodiment, the description has been given of the multi-layer type multilayer ceramic capacitor 7 in which four capacitor elements 3.2 × 1.6 and 0.85 mm in height are arranged in parallel. This is also effective for the external dimensions or the number of capacitor elements arranged in parallel. In addition, the emulsion thickness of the screen printing plate was controlled to provide a thickness difference between the internal electrode 2a and the connection portion 4. However, it is also possible to control the film thickness by changing the gauze thickness, the aperture ratio, and the like. Instead, another method such as intaglio printing can be used.

【0033】[0033]

【発明の効果】以上本発明の多連型積層セラミックコン
デンサ及びその製造方法は、同一平面に形成した複数個
の内部電極層と、その一方の端部に接続部を形成した内
部電極層と誘電体セラミック層とを交互に複数層積層、
焼成して単一素体内に複数個のコンデンサ素子を並設し
た焼結体の相対向する側面にコンデンサ素子に対応する
複数対の外部電極を設けた多連型積層セラミックコンデ
ンサにおいて、接続部の端部を、積層方向に前記誘電体
セラミック層を挟んで一層おきに交互に相対向する側面
に露出させると共に、これを介して内部電極を外部電極
と電気的に接続する。
As described above, the multi-layered multilayer ceramic capacitor and the method of manufacturing the same according to the present invention comprise a plurality of internal electrode layers formed on the same plane, an internal electrode layer having a connection formed at one end thereof, and a dielectric. Multiple layers alternately with body ceramic layers,
In a multi-layer monolithic ceramic capacitor in which a plurality of capacitor elements are juxtaposed in a single body and a plurality of pairs of external electrodes corresponding to the capacitor elements are provided on opposite sides of a sintered body, The end portions are alternately exposed on opposite side surfaces alternately with the dielectric ceramic layer interposed therebetween in the stacking direction, and the internal electrodes are electrically connected to the external electrodes via the exposed side surfaces.

【0034】この時本発明は内部電極、接続部及び外部
電極のそれぞれの幅を内部電極>外部電極>接続部とす
る。これによって外部電極の幅を内部電極の幅に関係な
く接続部より大きくすることで接続部のはみ出しを防ぐ
と共に、多連型積層セラミックコンデンサを回路基板に
実装した際に隣合うコンデンサ素子の外部電極どうしの
短絡を防止できる適切な間隔を有したものとなり、その
形成は非常に容易なものとなる。また内部電極は外部電
極の幅に制約されずに、隣合うコンデンサ素子の内部電
極との絶縁距離のみを考慮し有効面積を大きくすること
が可能となり高容量化が図れる。更に接続部の膜厚を内
部電極より厚くすることで、内部電極は接続部を介して
外部電極との接続面積が大きくなり、電気的接続の信頼
性を確保し容量抜けがなくなる。また、更に内部電極と
接続部の接続境界部を円弧状に構成することで、完成品
を回路基板等に半田付けの際のヒートショックにも強い
多連型積層セラミックコンデンサを作製することができ
る。これによって大容量のコンデンサ素子を複数個並設
した信頼性の高い多連型積層セラミックコンデンサの提
供が容易となり工業的に有効な手段となる。
At this time, according to the present invention, the width of each of the internal electrode, the connection portion, and the external electrode is set as internal electrode> external electrode> connection portion. This makes the width of the external electrode larger than the connection regardless of the width of the internal electrode, preventing the connection part from protruding and, when mounting the multilayer ceramic capacitor on the circuit board, the external electrode of the adjacent capacitor element Appropriate intervals are provided so as to prevent short circuit between them, and the formation thereof is very easy. Further, the internal electrode is not limited by the width of the external electrode, and the effective area can be increased in consideration of only the insulation distance between the internal electrodes of adjacent capacitor elements, so that the capacity can be increased. Further, by making the thickness of the connection part thicker than that of the internal electrode, the connection area of the internal electrode to the external electrode via the connection part is increased, and the reliability of the electrical connection is ensured and the capacity loss does not occur. Further, by forming the connection boundary between the internal electrode and the connection portion in an arc shape, it is possible to manufacture a multi-layer monolithic ceramic capacitor that is resistant to heat shock when soldering the finished product to a circuit board or the like. . As a result, it is easy to provide a highly reliable multi-layered ceramic capacitor having a plurality of large-capacity capacitor elements arranged in parallel, which is an industrially effective means.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態の四連型積層セラミック
コンデンサの上面図
FIG. 1 is a top view of a quadruple-type multilayer ceramic capacitor according to an embodiment of the present invention.

【図2】同側面断面図FIG. 2 is a side sectional view of the same.

【図3】同正面図FIG. 3 is a front view of the same.

【図4】従来の四連型積層セラミックコンデンサの上面
FIG. 4 is a top view of a conventional quadruple-type multilayer ceramic capacitor.

【図5】断面図FIG. 5 is a sectional view

【図6】同正面図FIG. 6 is a front view of the same.

【符号の説明】[Explanation of symbols]

1 誘電体セラミック層 2 内部電極層 2a 内部電極 3 無効層 4 接続部 5 外部電極 6 内部電極と接続部の接続境界部に形成した円弧R 7 多連型積層セラミックコンデンサ DESCRIPTION OF SYMBOLS 1 Dielectric ceramic layer 2 Internal electrode layer 2a Internal electrode 3 Invalid layer 4 Connection part 5 External electrode 6 Arc R formed in the connection boundary of internal electrode and connection part 7 Multi-layer type multilayer ceramic capacitor

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E082 AA01 AB03 BC33 BC36 BC38 CC03 EE04 EE12 EE16 EE23 EE35 FG06 FG26 FG27 FG46 FG54 GG10 HH43 JJ03 LL01 LL02 LL03 MM22 MM24  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E082 AA01 AB03 BC33 BC36 BC38 CC03 EE04 EE12 EE16 EE23 EE35 FG06 FG26 FG27 FG46 FG54 GG10 HH43 JJ03 LL01 LL02 LL03 MM22 MM24

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 同一平面に形成した複数個の内部電極層
と誘電体セラミック層とを交互に複数層積層、焼成して
複数個のコンデンサ素子を単一素体内に並設した焼結体
の相対向する側面に前記コンデンサ素子の数に対応する
複数対の外部電極を設けた多連型積層セラミックコンデ
ンサにおいて、前記内部電極層は内部電極の一方の端部
に接続部を設け、その接続部の端部を前記誘電体セラミ
ック層を挟んで積層方向に一層おきに交互に相対向する
側面に露出させるとともに、接続部を介して内部電極を
前記外部電極と電気的に接続させ、接続部の幅は前記内
部電極の幅及び前記外部電極の幅より狭く構成した多連
型積層セラミックコンデンサ。
1. A sintered body in which a plurality of internal electrode layers and a dielectric ceramic layer formed on the same plane are alternately laminated and fired, and a plurality of capacitor elements are juxtaposed in a single element body. In a multiple-layer monolithic ceramic capacitor in which a plurality of pairs of external electrodes corresponding to the number of the capacitor elements are provided on opposing side surfaces, the internal electrode layer has a connection portion at one end of the internal electrode, and the connection portion End portions are alternately exposed on opposite side surfaces alternately in the stacking direction with the dielectric ceramic layer interposed therebetween, and an internal electrode is electrically connected to the external electrode via a connection portion. A multiple monolithic ceramic capacitor having a width smaller than a width of the internal electrode and a width of the external electrode.
【請求項2】 内部電極の幅を外部電極の幅よりも広く
構成した請求項1に記載の多連型積層セラミックコンデ
ンサ。
2. The multiple-layer ceramic capacitor according to claim 1, wherein the width of the internal electrode is wider than the width of the external electrode.
【請求項3】 内部電極と接続部の接続境界部を円弧状
にした請求項1に記載の多連型積層セラミックコンデン
サ。
3. The multilayer ceramic capacitor according to claim 1, wherein a connection boundary between the internal electrode and the connection portion is formed in an arc shape.
【請求項4】 接続部の厚さを内部電極の厚さより厚く
形成した請求項1に記載の多連型積層セラミックコンデ
ンサ。
4. The multilayer ceramic capacitor according to claim 1, wherein the thickness of the connecting portion is formed to be thicker than the thickness of the internal electrode.
【請求項5】 同一平面に複数個の内部電極と、これに
接続した接続部の形成するスクリーン印刷版に、接続部
分を内部電極部分の開口率、紗厚または乳剤厚みの少な
くとも一つを替えたスクリーン印刷版を用い、内部電極
部より接続部を厚く印刷形成した内部電極層と誘電体セ
ラミック層を複数層積層、焼成した焼結対の接続部が露
出した相対向する側面に接続部を介して内部電極層と電
気的に接続する外部電極を形成する多連型積層セラミッ
クコンデンサの製造方法。
5. A screen printing plate formed by a plurality of internal electrodes and a connection portion connected to the plurality of internal electrodes on the same plane, wherein the connection portion is replaced by at least one of the aperture ratio of the internal electrode portion, the gauze thickness or the emulsion thickness. Using a screen printing plate, a plurality of internal electrode layers and a dielectric ceramic layer were formed by printing the connection part thicker than the internal electrode part, and a connection part was formed on the opposing side surfaces where the connection part of the fired sintered pair was exposed. A method of manufacturing a multiple-layer ceramic capacitor, in which external electrodes electrically connected to internal electrode layers are formed via the external electrodes.
JP8582399A 1999-03-29 1999-03-29 Multi-laminated ceramic capacitor and manufacturing method of the same Pending JP2000277382A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8582399A JP2000277382A (en) 1999-03-29 1999-03-29 Multi-laminated ceramic capacitor and manufacturing method of the same

Publications (1)

Publication Number Publication Date
JP2000277382A true JP2000277382A (en) 2000-10-06

Family

ID=13869586

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000277382A (en)

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US8649156B2 (en) 2007-12-17 2014-02-11 Murata Manufacturing Co., Ltd. Multilayer capacitor having low equivalent series inductance and controlled equivalent series resistance
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