JPH03178112A - Compound chip part - Google Patents
Compound chip partInfo
- Publication number
- JPH03178112A JPH03178112A JP1316841A JP31684189A JPH03178112A JP H03178112 A JPH03178112 A JP H03178112A JP 1316841 A JP1316841 A JP 1316841A JP 31684189 A JP31684189 A JP 31684189A JP H03178112 A JPH03178112 A JP H03178112A
- Authority
- JP
- Japan
- Prior art keywords
- dielectrics
- substrate mounting
- capacitor element
- capacitors
- different temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title abstract 2
- 239000003990 capacitor Substances 0.000 claims abstract description 30
- 239000003989 dielectric material Substances 0.000 claims abstract description 16
- 239000002131 composite material Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010304 firing Methods 0.000 description 3
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子機器に用いられる積層セラミックコンデ
ンサを利用した複合チップ部品に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a composite chip component using a multilayer ceramic capacitor used in electronic equipment.
従来の技術
従来、この種の複合チップ部品は、第2図に示すような
構成であり、誘電体5と内部電極6を交互に重ね合わせ
て所定の厚みまで積層した後、厚み方向から切断処理し
て焼成したものの両端に、内部電極6と電気的に接続さ
れた外部電極7を設けた構造となっていた。その為、内
部電極6が幅方向と平行な構造となっている。Conventional technology Conventionally, this type of composite chip component has a structure as shown in FIG. 2, in which dielectrics 5 and internal electrodes 6 are alternately stacked to a predetermined thickness, and then cut from the thickness direction. The structure was such that external electrodes 7 electrically connected to internal electrodes 6 were provided at both ends of the fired product. Therefore, the internal electrode 6 has a structure parallel to the width direction.
発明が解決しようとする課題
このような従来の構成では、厚み方向に誘電体と内部電
極を交互に積層した後、厚み方向から切断処理して1形
状の中に複数個のコンデンサを形成するため、異なった
温度特性のコンデンサを1形状の中に形成することがで
きても、基板実装時にコンデンサ中の内部電極と基板の
ランド間に浮遊容量が発生するという問題があった。Problems to be Solved by the Invention In such a conventional configuration, dielectrics and internal electrodes are alternately laminated in the thickness direction and then cut in the thickness direction to form a plurality of capacitors in one shape. Even if capacitors with different temperature characteristics can be formed in one shape, there is a problem in that stray capacitance occurs between the internal electrodes of the capacitor and the land of the board when mounted on the board.
本発明は、このような問題点を解決するもので、l形状
の中に複数の異なった温度特性のコンデンサを容易に形
成することができ、かつ基板実装時に浮遊容量の発生を
少なくすることができる複合チップ部品を提供すること
を目的とするものである。The present invention solves these problems, and makes it possible to easily form a plurality of capacitors with different temperature characteristics in an L shape, and to reduce the occurrence of stray capacitance when mounted on a board. The purpose is to provide a composite chip component that can be used.
課題を解決するための手段
この問題点を解決するため本発明は、基板実装面に対し
垂直状態で誘電体と内部電極を交互に積層した第1コン
デンサ素子部と、この第1コンデンサ素子部の積層方向
に積層され、上記第1コンデンサ素子部と同様に誘電体
と内部電極を交互に基板実装面に対し垂直状態で積層し
た第2コンデンサ素子部とを備え、第1.第2のコンデ
ンサ素子部を異なった温度特性のコンデンサとして形成
したものである。Means for Solving the Problems In order to solve this problem, the present invention provides a first capacitor element portion in which dielectrics and internal electrodes are alternately laminated in a state perpendicular to the board mounting surface, and a first capacitor element portion of the first capacitor element portion. The second capacitor element part is stacked in the stacking direction and has dielectrics and internal electrodes alternately stacked perpendicularly to the board mounting surface similarly to the first capacitor element part. The second capacitor element portion is formed as a capacitor having different temperature characteristics.
作用
この構成により、1形状の中に複数の異なった温度特性
のコンデンサを容易に形成することが可能となり、特に
基板実装時の浮遊容量が問題となる5pF以下の仕様の
コンデンサについては、複合の自由度が大きくなる。Effect This configuration makes it possible to easily form multiple capacitors with different temperature characteristics in one shape. Especially for capacitors with specifications of 5 pF or less, where stray capacitance when mounted on a board is a problem, it is possible to easily form multiple capacitors with different temperature characteristics. Greater freedom.
実施例
第1図は本発明の一実施例による複合チップ部品の斜視
図及び断面図であり、1形状の中に異なる温度特性のコ
ンデンサを2個複合した例である。第1図において、誘
電体1はCK特性、誘電体2は誘電体lとは異なる温度
特性であるUJ特性であり、それぞれ内部電極3と交互
に積層された後、厚み方向から切断処理して焼成後、外
部電極4を設けた構造となっている。ここで、誘電体l
をベースとするコンデンサ素子と誘電体2をベースとす
るコンデンサ素子とはその内部電極3が基板実装面に対
し垂直状態となるように積層されたものであり、内部電
極3と基板実装面との対向面積は極めて小さい。Embodiment FIG. 1 is a perspective view and a cross-sectional view of a composite chip component according to an embodiment of the present invention, and is an example in which two capacitors having different temperature characteristics are combined in one shape. In Fig. 1, dielectric 1 has CK characteristics, and dielectric 2 has UJ characteristics, which is a temperature characteristic different from that of dielectric 1. After being laminated alternately with internal electrodes 3, they are cut from the thickness direction. After firing, the structure is such that an external electrode 4 is provided. Here, the dielectric l
A capacitor element based on a dielectric material 2 and a capacitor element based on a dielectric material 2 are stacked so that their internal electrodes 3 are perpendicular to the board mounting surface. The facing area is extremely small.
又、焼成時の収縮を考慮して2種の誘電体1゜2は、焼
成時の収縮率がほぼ同じものを使用し、2種の誘電体の
接合部分のデラミネーション及び素子の変形を極力抑え
るように考慮されることが望ましい。In addition, in consideration of shrinkage during firing, we used two types of dielectrics 1゜2 with approximately the same shrinkage rate during firing to minimize delamination at the joint between the two types of dielectrics and deformation of the element. It is desirable that consideration be given to suppressing this.
発明の効果
以上のように本発明によれば、基板実装面に対して垂直
状態で誘電体と内部電極を交互に積層した複数のコンデ
ンサを形成するため、異なった温度特性のコンデンサの
複合化が容易に行え、より回路の高密度が可能になり、
かつ基板に対する各コンデンサの内部電極の対向面積が
小さく基板実装時の浮遊容量の発生も少なくなるように
抑制することができる。Effects of the Invention As described above, according to the present invention, since a plurality of capacitors are formed in which dielectrics and internal electrodes are alternately laminated perpendicular to the board mounting surface, it is possible to combine capacitors with different temperature characteristics. It is easy to perform and enables higher circuit density.
Furthermore, since the opposing area of the internal electrodes of each capacitor with respect to the substrate is small, it is possible to suppress the generation of stray capacitance when mounted on the substrate.
第1図は本発明の複合チップ部品の一実施例を示し、(
a)は斜視図、(b)はAn、断面図、<c)はB線断
面図、Id)はC線断面図、第2図は従来の複合チップ
部品を示し、(a)は斜視図、 k (b)
はA線断面図、(C)はB線断面図、(d)はC線断面
図である。
1.2・・・・・・誘電体、3・・・・・・内部電極、
4・・・・・・外部電極。FIG. 1 shows an embodiment of the composite chip component of the present invention, (
a) is a perspective view, (b) is an An, cross-sectional view, <c) is a cross-sectional view taken along line B, Id) is a cross-sectional view taken along line C, Figure 2 shows a conventional composite chip component, and (a) is a perspective view. , k (b)
is a cross-sectional view taken along line A, (C) is a cross-sectional view taken along line B, and (d) is a cross-sectional view taken along line C. 1.2... Dielectric, 3... Internal electrode,
4...External electrode.
Claims (1)
部電極が交互に積層された第1コンデンサ素子部と、こ
の第1コンデンサ素子部の積層方向に重ね合わされ、か
つ上記第1コンデンサ素子部と同様に基板実装面に対し
垂直状態となるように誘電体と内部電極が交互に積層さ
れた第2コンデンサ素子部とを備え、上記第1,第2コ
ンデンサ素子部は温度特性を異にする様に構成した複合
チップ部品。a first capacitor element section in which dielectrics and internal electrodes are alternately stacked so as to be perpendicular to the board mounting surface; and a first capacitor element section overlapping in the stacking direction of the first capacitor element sections, and and a second capacitor element part in which dielectrics and internal electrodes are alternately stacked so as to be perpendicular to the board mounting surface, and the first and second capacitor element parts have different temperature characteristics. Composite chip parts configured in a similar manner.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1316841A JPH03178112A (en) | 1989-12-06 | 1989-12-06 | Compound chip part |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1316841A JPH03178112A (en) | 1989-12-06 | 1989-12-06 | Compound chip part |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03178112A true JPH03178112A (en) | 1991-08-02 |
Family
ID=18081514
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1316841A Pending JPH03178112A (en) | 1989-12-06 | 1989-12-06 | Compound chip part |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03178112A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5583738A (en) * | 1993-03-29 | 1996-12-10 | Murata Manufacturing Co., Ltd. | Capacitor array |
WO2006110411A1 (en) * | 2005-03-31 | 2006-10-19 | Intel Corporation | Itfc with optimized c(t) |
US7453144B2 (en) | 2005-06-29 | 2008-11-18 | Intel Corporation | Thin film capacitors and methods of making the same |
US7629269B2 (en) | 2005-03-31 | 2009-12-08 | Intel Corporation | High-k thin film grain size control |
US7687366B2 (en) | 2005-06-23 | 2010-03-30 | Intel Corporation | Pre-patterned thin film capacitor and method for embedding same in a package substrate |
US7733626B2 (en) | 2004-10-21 | 2010-06-08 | Intel Corporation | Passive device structure |
US20150016016A1 (en) * | 2013-07-15 | 2015-01-15 | Samsung Electro-Mechanics Co., Ltd. | Array-type multilayer ceramic electronic component and mounting board therefor |
WO2020026481A1 (en) * | 2018-07-30 | 2020-02-06 | 株式会社村田製作所 | Reader/writer device |
-
1989
- 1989-12-06 JP JP1316841A patent/JPH03178112A/en active Pending
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5583738A (en) * | 1993-03-29 | 1996-12-10 | Murata Manufacturing Co., Ltd. | Capacitor array |
US7733626B2 (en) | 2004-10-21 | 2010-06-08 | Intel Corporation | Passive device structure |
JP2008535274A (en) * | 2005-03-31 | 2008-08-28 | インテル・コーポレーション | Integrated thin film capacitors with optimized temperature characteristics |
US7375412B1 (en) | 2005-03-31 | 2008-05-20 | Intel Corporation | iTFC with optimized C(T) |
US7629269B2 (en) | 2005-03-31 | 2009-12-08 | Intel Corporation | High-k thin film grain size control |
US7656644B2 (en) | 2005-03-31 | 2010-02-02 | Intel Corporation | iTFC with optimized C(T) |
WO2006110411A1 (en) * | 2005-03-31 | 2006-10-19 | Intel Corporation | Itfc with optimized c(t) |
US7755165B2 (en) | 2005-03-31 | 2010-07-13 | Intel Corporation | iTFC with optimized C(T) |
DE112006000519B4 (en) * | 2005-03-31 | 2011-12-15 | Intel Corporation | Integrated thin-film capacitor with optimized temperature characteristic |
US7687366B2 (en) | 2005-06-23 | 2010-03-30 | Intel Corporation | Pre-patterned thin film capacitor and method for embedding same in a package substrate |
US7453144B2 (en) | 2005-06-29 | 2008-11-18 | Intel Corporation | Thin film capacitors and methods of making the same |
US7547957B2 (en) | 2005-06-29 | 2009-06-16 | Intel Corporation | Thin film capacitors and methods of making the same |
US8499426B2 (en) | 2005-06-29 | 2013-08-06 | Intel Corporation | Methods of making thin film capacitors |
US20150016016A1 (en) * | 2013-07-15 | 2015-01-15 | Samsung Electro-Mechanics Co., Ltd. | Array-type multilayer ceramic electronic component and mounting board therefor |
WO2020026481A1 (en) * | 2018-07-30 | 2020-02-06 | 株式会社村田製作所 | Reader/writer device |
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