JPH08130160A - Manufacture of multilayer ceramic electronic component - Google Patents

Manufacture of multilayer ceramic electronic component

Info

Publication number
JPH08130160A
JPH08130160A JP6292196A JP29219694A JPH08130160A JP H08130160 A JPH08130160 A JP H08130160A JP 6292196 A JP6292196 A JP 6292196A JP 29219694 A JP29219694 A JP 29219694A JP H08130160 A JPH08130160 A JP H08130160A
Authority
JP
Japan
Prior art keywords
ceramic
laminated
layers
electronic component
outer layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6292196A
Other languages
Japanese (ja)
Inventor
Masahiro Tajima
正広 田島
Takaaki Kawai
孝明 河合
Masashi Morimoto
正士 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP6292196A priority Critical patent/JPH08130160A/en
Publication of JPH08130160A publication Critical patent/JPH08130160A/en
Withdrawn legal-status Critical Current

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  • Devices For Post-Treatments, Processing, Supply, Discharge, And Other Processes (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE: To manufacture a multilayer ceramic electronic component which facilitates the relief of an internal stress produced in a baking process and which does not have a structural defect such as a delamination. CONSTITUTION: A plurality of layers of iner electrodes 2 and a plurality of ceramic layers 1 are alternately provided so as to have the inner electrodes 2 face each other with the ceramic layers 1 therebetween to constitute a multilayer part 3. On both the upper and lower sides of the multilayer part 3, outer layers 4a and 4b in which inner electrodes 2 are not provided and whose thickness ratio is within a range of 1:2-1:3 are formed to constitute a multilayer ceramic unit 5. The multilayer ceramic unit 5 is baked and a minute warpage in a required direction is created in the baked unit 5a to relieve an internal stress which is caused by the partial difference in contraction factors when the multilayer ceramic unit 5 is baked.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子部品の製造方法に関
し、詳しくは、積層セラミックコンデンサ、積層セラミ
ックフィルタなどの積層セラミック電子部品の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic component, and more particularly to a method for manufacturing a laminated ceramic electronic component such as a laminated ceramic capacitor and a laminated ceramic filter.

【0002】[0002]

【従来の技術及び発明が解決しようとする課題】例え
ば、代表的な積層セラミック電子部品の一つである積層
セラミックコンデンサは、図4に示すように、セラミッ
ク層1を介して内部電極2が互に対向するように、複数
層の内部電極2とセラミック層1とを交互に配設してな
る積層部3と、積層部3の上下両面側に配設された、内
部電極が配設されていないセラミック層からなる外層部
4a,4bとを備えてなるセラミック積層体5の両端側
に、交互に異なる側の端面に引き出された内部電極2と
導通する外部電極6a,6bを配設することにより形成
されており、上下両面側の外層部4a,4bの厚みは通
常同じになるように設計されている。
2. Description of the Related Art For example, in a monolithic ceramic capacitor, which is one of typical monolithic ceramic electronic components, as shown in FIG. So as to face each other, a laminated portion 3 in which a plurality of layers of the internal electrodes 2 and the ceramic layers 1 are alternately arranged, and internal electrodes disposed on the upper and lower surfaces of the laminated portion 3 are arranged. The external electrodes 6a and 6b, which are electrically connected to the internal electrodes 2 that are drawn out to the end faces of the different sides alternately, are arranged at both ends of the ceramic laminated body 5 that is provided with the outer layer portions 4a and 4b made of non-ceramic layers. The outer layer portions 4a and 4b on the upper and lower surfaces are usually designed to have the same thickness.

【0003】ところで、上記従来の積層セラミックコン
デンサを製造する場合、セラミック積層体5の焼成時
に、外層部4a,4bと積層部3の収縮率に差が生じ
る。これは、積層部3を構成するセラミック層(セラミ
ックグリーンシート)1の表面に導電ペーストを塗布す
ることにより内部電極2が形成されているため、焼成時
に生じる収縮が内部電極2の影響を受けて、内部電極が
配設されていない外層部4a,4bよりも平面的に収縮
率が大きくなることによるものであり、積層部3を構成
するセラミック層1と外層部4a,4bが同一材料から
形成されている場合にも生じるものである。
By the way, when manufacturing the above-mentioned conventional monolithic ceramic capacitor, when the ceramic laminate 5 is fired, a difference occurs in the shrinkage rate between the outer layer portions 4a and 4b and the laminate portion 3. This is because the internal electrode 2 is formed by applying a conductive paste on the surface of the ceramic layer (ceramic green sheet) 1 that constitutes the laminated portion 3, so that the shrinkage that occurs during firing is affected by the internal electrode 2. This is because the contraction rate in the plane is larger than that of the outer layer portions 4a and 4b in which the internal electrodes are not arranged, and the ceramic layer 1 and the outer layer portions 4a and 4b forming the laminated portion 3 are formed of the same material. It also occurs when it is done.

【0004】このように、焼成時に、外層部4a,4b
と積層部3の収縮率に差が生じると、積層部3にデラミ
ネーションなどの構造欠陥が発生し、所望の特性を得る
ことができなくなるという問題点がある。
Thus, during firing, the outer layer portions 4a, 4b
If there is a difference in shrinkage ratio between the laminated portion 3 and the laminated portion 3, a structural defect such as delamination occurs in the laminated portion 3 and desired characteristics cannot be obtained.

【0005】本発明は、上記問題点を解決するものであ
り、焼成工程における内部応力の発生を緩和して、デラ
ミネーションなどの構造欠陥の発生を防止することが可
能な積層セラミック電子部品の製造方法を提供すること
を目的とする。
The present invention solves the above-mentioned problems and manufactures a monolithic ceramic electronic component capable of alleviating the generation of internal stress in the firing process and preventing the occurrence of structural defects such as delamination. The purpose is to provide a method.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明の積層セラミック電子部品の製造方法は、内
部電極をセラミック中に配設してなる積層セラミック電
子部品の製造方法であって、セラミック層を介して内部
電極が互に対向するように複数層の内部電極とセラミッ
ク層とが交互に配設された積層部の上下両面側に、厚み
比が1:2〜1:3の範囲にある、内部電極が配設され
ていないセラミック層からなる外層部を配設することに
よりセラミック積層体を形成し、前記セラミック積層体
を焼成して、その焼結体に所定の方向への微小な反りを
生じさせることを特徴としている。
In order to achieve the above object, a method of manufacturing a monolithic ceramic electronic component according to the present invention is a method of manufacturing a monolithic ceramic electronic component in which internal electrodes are provided in a ceramic. , A thickness ratio of 1: 2 to 1: 3 is provided on the upper and lower surfaces of the laminated portion in which a plurality of layers of the internal electrodes and the ceramic layers are alternately arranged so that the internal electrodes face each other via the ceramic layers. A ceramic laminated body is formed by arranging an outer layer portion formed of a ceramic layer in which the internal electrodes are not arranged, the ceramic laminated body is fired, and the sintered body is formed in a predetermined direction. It is characterized by causing a minute warp.

【0007】[0007]

【作用】複数層の内部電極とセラミック層とが交互に配
設された積層部の上下両面側に、互いの厚み比が1:2
〜1:3の範囲にある外層部を配設することにより形成
されたセラミック積層体を焼成すると、その焼結体に所
定の方向への微小な反りが生じる。
The thickness ratio of each of the internal electrodes and the ceramic layers of the plurality of layers is 1: 2 on the upper and lower surfaces of the laminated portion.
When the ceramic laminate formed by disposing the outer layer portion in the range of to 1: 3 is fired, a slight warp in a predetermined direction occurs in the sintered body.

【0008】そして、この微小な反りにより、例えば、
積層部を構成するセラミック層(セラミックグリーンシ
ート)の表面に導電ペーストを塗布することにより内部
電極が形成されているような場合に、内部電極の影響を
受けて、積層部の収縮率が、内部電極が配設されていな
い外層部の収縮率よりも大きくなることから生じる内部
応力を緩和して、デラミネーションなどの構造欠陥の発
生を防止することができるようになる。
Then, due to this minute warp, for example,
When an internal electrode is formed by applying a conductive paste on the surface of a ceramic layer (ceramic green sheet) that constitutes the laminated part, the contraction rate of the laminated part is It becomes possible to alleviate the internal stress caused by the fact that the contraction rate of the outer layer portion where the electrodes are not provided is larger than that of the outer layer portion, and prevent the occurrence of structural defects such as delamination.

【0009】なお、上下両面側の外層部の厚み比を1:
2〜1:3とする場合に、上面側及び下面側の外層部の
どちら側の厚みを大きくするかについては、積層部の構
成(例えば、セラミック層への内部電極の塗布態様や両
者の位置関係など)を考慮して定めたりすればよい。
The thickness ratio of the outer layer portions on the upper and lower sides is 1:
In the case of 2 to 1: 3, regarding which side of the outer layer portion on the upper surface side or the lower surface side to increase the thickness, the configuration of the laminated portion (for example, the application mode of the internal electrode to the ceramic layer and the position of both of them) is determined. Relationships, etc.).

【0010】[0010]

【実施例】以下、本発明の実施例を示してその特徴とす
るところをさらに詳しく説明する。なお、この実施例で
は、積層セラミックコンデンサを製造する場合を例にと
って説明する。
EXAMPLES Examples of the present invention will be shown below to explain the features thereof in more detail. In this embodiment, a case of manufacturing a monolithic ceramic capacitor will be described as an example.

【0011】この実施例においては、図1に示すよう
に、導電ペースト(内部電極)2を印刷した誘電体シー
ト(セラミック層)1を複数枚積み重ねて積層部3を形
成し、さらにその上下両面側に内部電極が配設されてい
ない、セラミック層1と同じ材料からなるダミーシート
(外層部)4a,4bを積層した後、圧着してセラミッ
ク積層体5を形成した。
In this embodiment, as shown in FIG. 1, a plurality of dielectric sheets (ceramic layers) 1 printed with a conductive paste (internal electrode) 2 are stacked to form a laminated portion 3, and the upper and lower surfaces thereof are further formed. After stacking dummy sheets (outer layer portions) 4a and 4b made of the same material as the ceramic layer 1 on which no internal electrode is provided, the ceramic laminate 5 is formed by pressure bonding.

【0012】そして、この実施例では、下面側の外層部
4bの厚みを、上面側の外層部4aの厚みの1倍から4
倍の範囲で変化させた(上面側の外層部4aの厚み:下
面側の外層部4bの厚み=1:1,2:3,1:2,
1:3,及び1:4)。
Further, in this embodiment, the thickness of the outer layer portion 4b on the lower surface side is 1 to 4 times the thickness of the outer layer portion 4a on the upper surface side.
The thickness of the outer layer portion 4a on the upper surface side: the thickness of the outer layer portion 4b on the lower surface side = 1: 1, 2: 3, 1: 2
1: 3 and 1: 4).

【0013】それから、このようにして形成したセラミ
ック積層体5を所定の条件で脱脂した後、本焼成して、
図2に示すような焼結体5(5a)を得た。(なお、こ
の焼結体(セラミック積層体)5aの両端部に、内部電
極2と導通する外部電極6a,6b(図3)を配設する
ことにより、図3に示すような積層セラミックコンデン
サが形成される。)
Then, the ceramic laminated body 5 thus formed is degreased under predetermined conditions and then main-baked,
A sintered body 5 (5a) as shown in FIG. 2 was obtained. (In addition, by disposing external electrodes 6a and 6b (FIG. 3) which are electrically connected to the internal electrode 2 at both ends of this sintered body (ceramic laminated body) 5a, a laminated ceramic capacitor as shown in FIG. 3 is obtained. It is formed.)

【0014】そして、得られた各焼結体5aについて、
デラミネーション発生率と反りの大きさを調べた。その
結果を表1に示す。
Then, for each of the obtained sintered bodies 5a,
The incidence of delamination and the magnitude of warpage were investigated. Table 1 shows the results.

【0015】[0015]

【表1】 [Table 1]

【0016】なお、表1の「反りの大きさ」は、焼結体
5aを置いた面7と焼結体5aの下面との間の距離(図
2のXの距離)を意味している。
The "magnitude of warpage" in Table 1 means the distance (distance X in FIG. 2) between the surface 7 on which the sintered body 5a is placed and the lower surface of the sintered body 5a. .

【0017】表1より、上下両面側の外層部4a,4b
の厚み比が1:1の場合、デラミネーション発生率が5
6%であり、厚み比が2:3の場合には、デラミネーシ
ョン発生率が21%となっていることがわかる。
From Table 1, the outer layer portions 4a and 4b on both upper and lower surfaces are shown.
When the thickness ratio of 1 is 1, the delamination occurrence rate is 5
It is 6%, and it can be seen that the delamination occurrence rate is 21% when the thickness ratio is 2: 3.

【0018】これに対して、厚み比を1:2〜1:4の
範囲とした場合には、デラミネーション発生率が0%と
なる。
On the other hand, when the thickness ratio is in the range of 1: 2 to 1: 4, the delamination occurrence rate is 0%.

【0019】したがって、デラミネーション防止の見地
からは、下面側の外層部4bの厚みを上面側の外層部4
aの厚みの2倍以上にすることが望ましいことがわか
る。
Therefore, from the standpoint of preventing delamination, the thickness of the outer layer portion 4b on the lower surface side is made equal to the thickness of the outer layer portion 4 on the upper surface side.
It can be seen that it is desirable to make the thickness at least twice the thickness of a.

【0020】一方、厚み比が1:4になると反りの大き
さが74μmとなり、実装時の安定性が低下したり、反
りが大きくなり過ぎることに起因して両端面に露出して
いた内部電極2の一部が端面から後退して、両端面に形
成された外部電極6a,6b(図3)と導通しない場合
(図示せず)が生じて、所望の特性が得られなくなった
りするため好ましくない。
On the other hand, when the thickness ratio is 1: 4, the size of the warp becomes 74 μm, the stability at the time of mounting is deteriorated, and the warp becomes too large, so that the internal electrodes exposed on both end surfaces are exposed. A part (2) of 2 retreats from the end faces and does not conduct with the external electrodes 6a and 6b (FIG. 3) formed on both end faces (not shown), and desired characteristics may not be obtained, which is preferable. Absent.

【0021】したがって、上下両面側の外層部4a,4
bの厚み比は、1:2〜1:3の範囲内とすることが好
ましい。
Therefore, the outer layer portions 4a, 4 on both the upper and lower sides.
The thickness ratio of b is preferably within the range of 1: 2 to 1: 3.

【0022】なお、上記実施例では、積層部を構成する
セラミック層と外層部が同一材料である場合について説
明したが、本発明は、セラミック層と外層部が同一材料
でない場合にも適用することが可能である。
In the above embodiment, the case where the ceramic layer and the outer layer portion forming the laminated portion are made of the same material has been described, but the present invention can be applied to the case where the ceramic layer and the outer layer portion are not made of the same material. Is possible.

【0023】また、上記実施例では、積層セラミックコ
ンデンサを製造する場合を例にとって説明したが、本発
明は、積層セラミックコンデンサの製造方法に限定され
るものではなく、積層セラミックフィルタやセラミック
多層基板などの種々の積層セラミック電子部品を製造す
る場合に適用することが可能である。
In the above embodiments, the case of manufacturing a monolithic ceramic capacitor has been described as an example, but the present invention is not limited to the method of manufacturing a monolithic ceramic capacitor, and a monolithic ceramic filter, a ceramic multi-layer substrate, or the like. Can be applied to the case of manufacturing various types of monolithic ceramic electronic components.

【0024】本発明は、さらにその他の点においても上
記実施例に限定されるものではなく、セラミック積層体
の具体的な構造、内部電極のパターンなどに関し、発明
の要旨の範囲内において種々の応用、変形を加えること
が可能である。
The present invention is not limited to the above-mentioned embodiments in other points as well, and relates to specific structures of the ceramic laminate, internal electrode patterns, etc., and various applications within the scope of the invention. , Can be modified.

【0025】[0025]

【発明の効果】上述のように、本発明の積層セラミック
電子部品の製造方法は、セラミック層を介して内部電極
が互に対向するように複数層の内部電極とセラミック層
とが交互に配設された積層部の上下両面側に、厚み比が
1:2〜1:3の範囲にある外層部を配設することによ
りセラミック積層体を形成し、このセラミック積層体を
焼成して、焼結体に所定の方向への微小な反りを生じさ
せるようにしているので、セラミック積層体の焼成時の
部分的な収縮率の差によって生じる内部応力を緩和する
ことが可能になり、デラミネーションなどの構造欠陥の
ない、信頼性の高い積層セラミック電子部品を確実に製
造することができる。
As described above, according to the method of manufacturing a laminated ceramic electronic component of the present invention, a plurality of layers of internal electrodes and ceramic layers are alternately arranged so that the internal electrodes face each other with the ceramic layers interposed therebetween. A ceramic laminated body is formed by disposing outer layer portions having a thickness ratio in the range of 1: 2 to 1: 3 on both upper and lower sides of the formed laminated portion, and the ceramic laminated body is fired and sintered. Since a slight warpage in a predetermined direction is generated in the body, it is possible to relieve the internal stress caused by the partial difference in shrinkage rate during firing of the ceramic laminate, and to prevent delamination and the like. It is possible to reliably manufacture a highly reliable multilayer ceramic electronic component without structural defects.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例おいて形成したセラミック積
層体を示す断面図である。
FIG. 1 is a cross-sectional view showing a ceramic laminate formed in an embodiment of the present invention.

【図2】本発明の一実施例において形成したセラミック
積層体を焼成してなる焼結体を示す断面図である。
FIG. 2 is a cross-sectional view showing a sintered body obtained by firing a ceramic laminated body formed in one example of the present invention.

【図3】図2の焼結体に外部電極を形成してなる積層セ
ラミックコンデンサを示す断面図である。
FIG. 3 is a cross-sectional view showing a monolithic ceramic capacitor formed by forming external electrodes on the sintered body of FIG.

【図4】従来の積層セラミックコンデンサを示す断面図
である。
FIG. 4 is a sectional view showing a conventional monolithic ceramic capacitor.

【符号の説明】[Explanation of symbols]

1 セラミック層 2 内部電極(導電ペースト) 3 積層部 4a,4b 外層部(ダミーシート) 5 セラミック積層体 5a セラミック積層体の焼結体 6a,6b 外部電極 DESCRIPTION OF SYMBOLS 1 Ceramic layer 2 Internal electrode (conductive paste) 3 Laminated parts 4a, 4b Outer layer part (dummy sheet) 5 Ceramic laminated body 5a Sintered body of ceramic laminated body 6a, 6b External electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 内部電極をセラミック中に配設してなる
積層セラミック電子部品の製造方法であって、 セラミック層を介して内部電極が互に対向するように複
数層の内部電極とセラミック層とが交互に配設された積
層部の上下両面側に、厚み比が1:2〜1:3の範囲に
ある、内部電極が配設されていないセラミック層からな
る外層部を配設することによりセラミック積層体を形成
し、 前記セラミック積層体を焼成して、その焼結体に所定の
方向への微小な反りを生じさせることを特徴とする積層
セラミック電子部品の製造方法。
1. A method of manufacturing a laminated ceramic electronic component, which comprises arranging internal electrodes in a ceramic, comprising a plurality of internal electrodes and ceramic layers such that the internal electrodes face each other with a ceramic layer interposed therebetween. By arranging the outer layer part consisting of the ceramic layer in which the internal electrodes are not arranged, in the thickness ratio of 1: 2 to 1: 3, on both upper and lower sides of the laminated part in which the A method for producing a laminated ceramic electronic component, comprising forming a ceramic laminated body, firing the ceramic laminated body, and causing a minute warp of the sintered body in a predetermined direction.
JP6292196A 1994-10-31 1994-10-31 Manufacture of multilayer ceramic electronic component Withdrawn JPH08130160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6292196A JPH08130160A (en) 1994-10-31 1994-10-31 Manufacture of multilayer ceramic electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6292196A JPH08130160A (en) 1994-10-31 1994-10-31 Manufacture of multilayer ceramic electronic component

Publications (1)

Publication Number Publication Date
JPH08130160A true JPH08130160A (en) 1996-05-21

Family

ID=17778784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6292196A Withdrawn JPH08130160A (en) 1994-10-31 1994-10-31 Manufacture of multilayer ceramic electronic component

Country Status (1)

Country Link
JP (1) JPH08130160A (en)

Cited By (30)

* Cited by examiner, † Cited by third party
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US5989726A (en) * 1996-07-04 1999-11-23 Murata Manufacturing Co., Ltd. Multi-layer ceramic electronic part
JP2005212194A (en) * 2004-01-28 2005-08-11 Sony Corp Ceramic green sheet manufacturing method, laminated ceramic sheet manufactureing method and piezoelectric actuator element manufacturing method
US6974515B2 (en) * 2002-01-26 2005-12-13 Robert Bosch Gmbh Ceramic substrate and method of manufacturing same
CN102667980A (en) * 2009-10-16 2012-09-12 如碧空株式会社 Multilayer capacitor, manufacturing method thereof, circuit board, and electronic device
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