JP3316731B2 - Multilayer ceramic electronic components - Google Patents

Multilayer ceramic electronic components

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Publication number
JP3316731B2
JP3316731B2 JP02205596A JP2205596A JP3316731B2 JP 3316731 B2 JP3316731 B2 JP 3316731B2 JP 02205596 A JP02205596 A JP 02205596A JP 2205596 A JP2205596 A JP 2205596A JP 3316731 B2 JP3316731 B2 JP 3316731B2
Authority
JP
Japan
Prior art keywords
electrodes
electrode
internal
multilayer ceramic
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP02205596A
Other languages
Japanese (ja)
Other versions
JPH09190946A (en
Inventor
政樹 高木
勝己 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
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Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP02205596A priority Critical patent/JP3316731B2/en
Publication of JPH09190946A publication Critical patent/JPH09190946A/en
Application granted granted Critical
Publication of JP3316731B2 publication Critical patent/JP3316731B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層セラミック電
子部品に関し、詳しくは、セラミック中に内部電極とダ
ミー電極を配設してなる積層セラミック電子部品に関す
る。
The present invention relates to a multilayer ceramic electronic component, and more particularly, to a multilayer ceramic electronic component in which an internal electrode and a dummy electrode are provided in a ceramic.

【0002】[0002]

【従来の技術及び発明が解決しようとする課題】例え
ば、代表的な積層セラミック電子部品の一つである積層
セラミックコンデンサは、図4に示すように、セラミッ
ク1中に、複数の内部電極2を配設することにより形成
された素子(積層コンデンサ素子)3の両端側に、内部
電極2と導通する外部電極4を配設することにより形成
されている。
2. Description of the Related Art For example, a multilayer ceramic capacitor, which is one of typical multilayer ceramic electronic components, has a plurality of internal electrodes 2 in a ceramic 1 as shown in FIG. It is formed by disposing external electrodes 4 that are electrically connected to the internal electrodes 2 on both ends of the element (multilayer capacitor element) 3 formed by disposing.

【0003】ところで、図4に示すような構造の積層セ
ラミック電子部品の場合、内部電極2が一層ごとに素子
3の互いに逆側の端面に引き出されている電極引出部A
の厚みは、各内部電極2が重なっている部分Bに比べ
て、内部電極の厚み×0.5N(N=積層数)だけ小さ
くなり、積層数が50層以上になると、積層ブロックを
プレスする際に歪みが生じて内部電極2が湾曲したり、
積層ブロックをカットする際や焼成後にデラミネーショ
ンが発生したりして、製品の寿命低下を招くという問題
点がある。
In the case of a multilayer ceramic electronic component having a structure as shown in FIG. 4, an electrode lead-out portion A in which the internal electrodes 2 are led out to the opposite end surfaces of the element 3 one by one.
Is smaller than the portion B where the internal electrodes 2 overlap, by the thickness of the internal electrode × 0.5N (N = the number of layers). When the number of layers becomes 50 or more, the laminated block is pressed. When the internal electrode 2 is bent due to distortion,
There is a problem in that delamination occurs when the laminated block is cut or after firing, and the life of the product is shortened.

【0004】また、このような歪みを低減するために、
図5に示すように、ダミー電極5を上下の外層シートに
配設するようにした積層セラミック電子部品が提案され
ているが、内部電極2の積層数が多くなるとダミー電極
5をそれだけ多く積層しなければならず、必ずしも上記
問題点に対して十分に対応することができないのが実情
である。
In order to reduce such distortion,
As shown in FIG. 5, a multilayer ceramic electronic component in which dummy electrodes 5 are disposed on upper and lower outer sheets has been proposed. However, when the number of internal electrodes 2 is increased, the number of dummy electrodes 5 is increased. In fact, it is not always possible to sufficiently address the above problems.

【0005】また、図6に示すように、内部電極2と同
一の面に静電容量の形成には寄与しないダミー電極5を
配設した積層セラミック電子部品も提案されているが、
内部電極2の積層数が多くなると、積み重ね方向から見
た場合の内部電極2とダミー電極5の位置がそろってい
るため、この部分で、歪みや段差が発生し、図4の積層
セラミック電子部品の場合と同様にデラミネーションや
寿命の低下が発生するという問題点がある。
As shown in FIG. 6, a multilayer ceramic electronic component in which a dummy electrode 5 which does not contribute to the formation of a capacitance on the same surface as the internal electrode 2 is also proposed.
When the number of stacked internal electrodes 2 is increased, the positions of the internal electrodes 2 and the dummy electrodes 5 when viewed from the stacking direction are aligned, so that a distortion or a step occurs in this portion, and the multilayer ceramic electronic component of FIG. As in the case of (1), there is a problem that delamination and shortening of the service life occur.

【0006】本発明は、上記問題点を解決するものであ
り、内部電極の積層数が多くなった場合にも、大きな歪
みが発生せず、デラミネーションなどの内部欠陥や製品
の寿命低下などを引き起こすことのない積層セラミック
電子部品を提供することを目的とする。
The present invention solves the above-mentioned problems. Even when the number of internal electrodes is increased, large distortion does not occur, and internal defects such as delamination and shortened product life are reduced. It is an object of the present invention to provide a multilayer ceramic electronic component that does not cause any problems.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明の積層セラミック電子部品は、セラミック中
に配設され、一端側が素子の一方の端面に引き出された
容量形成用の第1の内部電極と、前記第1の内部電極と
セラミック層を介して対向する、一端側が素子の前記第
1の内部電極が引き出された端面とは逆側の端面に引き
出された容量形成用の第2の内部電極と、前記第1の内
部電極の素子の端面に引き出されていない方の端部側
に、該端部と所定の距離Gをおいて配設された第1のダ
ミー電極と、前記第2の内部電極の素子の端面に引き出
されていない方の端部側に、該端部と所定の距離Gをお
いて配設された第2のダミー電極とがセラミック層を介
して交互に積み重ねられた構造を有する積層セラミック
電子部品であって、第1及び第2の内部電極、及び第1
及び第2のダミー電極の各電極が、積み重ね方向から見
た場合に同じ位置に重複して配設されないように、第1
及び第2の内部電極と、第1及び第2のダミー電極の位
置を、一層ごと又は複数層ごとに、第1及び第2の内部
電極の引出し方向に平行な方向に所定の位置ずれ量
だけ、意図的にずらせたことを特徴としている。
In order to achieve the above object, a multilayer ceramic electronic component according to the present invention is provided in a ceramic and has a first end formed on one end face of an element for forming a capacitor. The first internal electrode is opposed to the first internal electrode via a ceramic layer, and one end of the second electrode for forming a capacitance is drawn to an end surface opposite to the end surface from which the first internal electrode of the element is drawn. 2, an internal electrode, and a first dummy electrode provided at a predetermined distance G from the end of the element of the first internal electrode that is not drawn out to the end face of the element; On the side of the end of the element of the second internal electrode which is not drawn out to the end face of the element, the end and a second dummy electrode disposed at a predetermined distance G alternately via a ceramic layer. A multilayer ceramic electronic component having a structure stacked on, First and second inner electrodes and the first
And the first and second dummy electrodes are arranged so as not to be overlapped at the same position when viewed from the stacking direction.
The position of the second internal electrode and the position of the first and second dummy electrodes are shifted by a predetermined amount in a direction parallel to the direction in which the first and second internal electrodes are drawn out, for each layer or for each of a plurality of layers. L
However, it is characterized by intentionally shifting.

【0008】また、前記各電極の、対応する電極との位
置ずれ量Lが、前記内部電極と前記ダミー電極の間の距
離Gの50%以上であることを特徴としている。
[0008] Further, the present invention is characterized in that the displacement L of each of the electrodes with respect to the corresponding electrode is 50% or more of the distance G between the internal electrode and the dummy electrode.

【0009】また、前記内部電極と、前記ダミー電極の
各電極のうち、積み重ね方向から見た場合に同じ位置に
重複して配設される電極の数が電極全体の60%を越え
ないことを特徴としている。
[0009] Further, among the electrodes of the internal electrode and the dummy electrode, the number of overlappingly disposed electrodes at the same position when viewed from the stacking direction does not exceed 60% of the entire electrodes. Features.

【0010】また、前記内部電極と前記ダミー電極の間
の距離Gを、積み重ね方向にとなり合う電極間に介在す
るセラミック層の厚みよりも大きくしたことを特徴とし
ている。
[0010] Further, a distance G between the internal electrode and the dummy electrode is made larger than a thickness of a ceramic layer interposed between the adjacent electrodes in the stacking direction.

【0011】[0011]

【作用】本発明の積層セラミック電子部品においては、
セラミックを介して積み重ねられる第1及び第2の内部
電極と、第1及び第2のダミー電極の位置を、一層ごと
又は複数層ごとに、第1及び第2の内部電極の引出し方
向に平行な方向に所定の位置ずれ量Lだけ、意図的に
ずらせるようにしているので、第1及び第2の内部電極
と、第1及び第2のダミー電極の各電極のすべてが、積
み重ね方向から見た場合に同じ位置に重複して配設され
ることを抑制して、内部電極の湾曲やそれによるデラミ
ネーションなどの内部欠陥の発生を防止することが可能
になる。
In the multilayer ceramic electronic component of the present invention,
The positions of the first and second internal electrodes stacked via the ceramic and the positions of the first and second dummy electrodes are set in parallel with the direction in which the first and second internal electrodes are drawn out for each layer or for each of a plurality of layers. In the direction, the predetermined positional deviation amount L is intentionally shifted, so that all of the first and second internal electrodes and each of the first and second dummy electrodes are In addition, it is possible to suppress the occurrence of internal defects such as the bending of the internal electrodes and the resulting delamination by suppressing the overlapping of the internal electrodes at the same position when viewed from the stacking direction.

【0012】また、各電極の位置ずれ量Lを、内部電極
とダミー電極の間の距離Gの50%以上にすることによ
り、歪みの発生を抑制して、デラミネーションなどの内
部欠陥の発生を確実に防止することができるようにな
る。
Further, by setting the displacement L of each electrode to 50% or more of the distance G between the internal electrode and the dummy electrode, the generation of distortion is suppressed, and the generation of internal defects such as delamination is suppressed. Prevention can be surely prevented.

【0013】さらに、各電極のうち、積み重ね方向から
見た場合に同じ位置に重複して配設される電極が60%
を越えないようにすることにより、また、内部電極とダ
ミー電極の間の距離Gを、積み重ね方向にとなり合う電
極間に介在するセラミック層の厚みより大きくすること
により、内部電極の積層数が増えた場合にも、歪みやそ
れによるデラミネーションの発生を確実に防止すること
が可能になり、本発明をより実効あらしめることができ
る。
Further, among the electrodes, 60% of the electrodes overlappingly arranged at the same position when viewed from the stacking direction are used.
The internal electrodes and the
By making the distance G between the me electrodes larger than the thickness of the ceramic layer interposed between the adjacent electrodes in the stacking direction, even when the number of laminated internal electrodes increases, distortion and the occurrence of delamination due to the distortion can be prevented. As a result, the present invention can be made more effective.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施の形態を示し
てその特徴とするところをさらに詳しく説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be shown and features thereof will be described in more detail.

【0015】なお、ここでは、セラミックを誘電体とす
る積層セラミックコンデンサを例にとって説明する。
Here, a multilayer ceramic capacitor using ceramic as a dielectric will be described as an example.

【0016】[製造方法] まず、セラミック原料粉末をバインダーと混合してなる
スラリーを用意し、これを厚み10μmのセラミックグ
リーンシートに成形する。そして、このセラミックグリ
ーンシート上に導電ペーストを印刷した後、これを複数
枚積み重ねることにより積層素子を作成した。それから
この積層素子のバインダーを分解、除去した後、所定の
温度で焼成した。
[Manufacturing Method] First, a slurry is prepared by mixing a ceramic raw material powder with a binder, and this is formed into a ceramic green sheet having a thickness of 10 μm. Then, after a conductive paste was printed on the ceramic green sheets, a plurality of the conductive pastes were stacked to form a laminated element. Then, after decomposing and removing the binder of this laminated element, it was fired at a predetermined temperature.

【0017】それから、外部電極形成用の金属ペースト
を塗布、焼付けすることにより図1,図2及び図3に示
すように、セラミック1中に、第1及び第2の内部電極
2(2a,2b)、第1及び第2のダミー電極5(5
a,5b)が配設され、かつ、素子(積層コンデンサ素
子)3の両側端面に引き出された第1及び第2の内部電
極2(2a,2b)と導通する外部電極4が配設された
構造を有する積層セラミックコンデンサを得た。このと
きの内部電極の有効積層枚数は150枚とした。
Then, by applying and baking a metal paste for forming an external electrode, as shown in FIGS. 1, 2 and 3, the first and second internal electrodes 2 (2a, 2b) are formed in the ceramic 1. ), The first and second dummy electrodes 5 (5
a, 5b), and external electrodes 4 electrically connected to the first and second internal electrodes 2 (2a, 2b) drawn out on both end surfaces of the element (multilayer capacitor element) 3. A multilayer ceramic capacitor having a structure was obtained. At this time, the effective number of laminated internal electrodes was 150.

【0018】また、比較例として、上記と同様の方法に
より、セラミック1中に複数の内部電極2のみが配設さ
れ、ダミー電極の配設されていない積層セラミックコン
デンサ(図4)及び、セラミック1中に内部電極2とダ
ミー電極5が、積み重ね方向から見た場合に同じ位置に
重複して配設された構造を有する積層セラミックコンデ
ンサ(図6)を製造した。
As a comparative example, a multilayer ceramic capacitor (FIG. 4) in which only a plurality of internal electrodes 2 are provided in the ceramic 1 and no dummy electrode is provided, and a ceramic 1 A multilayer ceramic capacitor (FIG. 6) having a structure in which the internal electrode 2 and the dummy electrode 5 are disposed at the same position when viewed from the stacking direction and overlapped with each other was manufactured.

【0019】[積層セラミックコンデンサの構造] 図1の積層セラミックコンデンサは、積み重ね方向に互
いにとなり合う、内部電極2(2a,2b)とダミー電
極5(5a,5b)の間の隙間(ギャップ)10(10
a,10b)の位置が距離Lだけずれるように構成され
ている。なお、この例では、位置ずれ量Lが、ギャップ
10の距離Gと等しくなるように構成されている。
[Structure of Multilayer Ceramic Capacitor] The multilayer ceramic capacitor of FIG. 1 has a gap (gap) 10 between the internal electrodes 2 (2a, 2b) and the dummy electrodes 5 (5a, 5b), which are adjacent to each other in the stacking direction. (10
a, 10b) are configured to be shifted by a distance L. Note that, in this example, the displacement L is equal to the distance G of the gap 10.

【0020】また、図2の積層セラミックコンデンサ
は、4層の第1の内部電極2aと4層の第2の内部電極
2bからなるコンデンサ部6aと、積み重ね方向に互い
にとなり合う、同じく4層の第1の内部電極2aと4層
の第2の内部電極2bからなるコンデンサ部6bとの関
係において、内部電極2とダミー電極5の間のギャップ
10(10a,10b)の位置がLだけずれるように構
成されている。なお、この例では、位置ずれ量Lが、ギ
ャップ10の距離Gと等しくなるように構成されてい
る。
The multilayer ceramic capacitor shown in FIG. 2 has a capacitor portion 6a composed of four layers of first internal electrodes 2a and four layers of second internal electrodes 2b, and also has a four-layered ceramic electrode. In the relationship between the first internal electrode 2a and the capacitor portion 6b including the four layers of second internal electrodes 2b, the position of the gap 10 (10a, 10b) between the internal electrode 2 and the dummy electrode 5 is shifted by L. Is configured. Note that, in this example, the displacement L is equal to the distance G of the gap 10.

【0021】また、図3の積層セラミックコンデンサに
おいては、図1の積層セラミックコンデンサと同様に、
積み重ね方向に互いにとなり合う、内部電極2(2a,
2b)とダミー電極5(5a,5b)の間のギャップ1
0(10a,10b)の位置が距離Lだけずれるように
構成されており、かつ、位置ずれ量Lが、ギャップ10
の距離Gよりも大きくなるように構成されている。
In the multilayer ceramic capacitor of FIG. 3, as in the case of the multilayer ceramic capacitor of FIG.
The internal electrodes 2 (2a, 2a,
2b) and the gap 1 between the dummy electrode 5 (5a, 5b)
0 (10a, 10b) is shifted by a distance L, and the position shift amount L
Is configured to be larger than the distance G of

【0022】[構造欠陥など観察結果] 上記のようにして製造した積層セラミックコンデンサに
ついて、脱バインダーの前後でのデラミネーションの発
生状態、及び焼成後におけるデラミネーション及びショ
ート不良の発生状態を調べた。その結果を表1に示す。
[Results of Observation of Structural Defects, etc.] With respect to the multilayer ceramic capacitor manufactured as described above, the state of occurrence of delamination before and after debinding and the state of occurrence of delamination and short circuit after firing were examined. Table 1 shows the results.

【0023】[0023]

【表1】 [Table 1]

【0024】表1において、No.1〜9の試料は、いず
れも本発明の構造を有する積層セラミックコンデンサで
あるが、そのうちのNo.8及び9の試料は、素子厚(セ
ラミック層の厚さ)=7μm、ギャップ10の距離G=
5μmという条件のものである。なお、その他のNo.1〜
7の試料は、素子厚=10μmであり、ギャップ10の
距離Gを、表1に示すように、100〜10μmの間で
変化させている。なお、No.1〜9の試料において、No.
5は図2に示す構造、No.6は図3に示す構造、その他
は図1に示す構造を有するものである。
In Table 1, the samples of Nos. 1 to 9 are all multilayer ceramic capacitors having the structure of the present invention. Among them, the samples of Nos. 8 and 9 have the element thickness (thickness of the ceramic layer). ) = 7 μm, distance G of gap 10 =
The condition is 5 μm. In addition, other No. 1 ~
In the sample No. 7, the element thickness was 10 μm, and the distance G of the gap 10 was changed between 100 and 10 μm as shown in Table 1. In the samples of Nos. 1 to 9, No.
No. 5 has the structure shown in FIG. 2, No. 6 has the structure shown in FIG. 3, and others have the structure shown in FIG.

【0025】また、No.10の試料はダミー電極を備え
ていない前述の図4に示すような構造を有する従来の積
層セラミックコンデンサであり、No.11の試料は、前
述の図6に示すような、積み重ね方向から見た場合に電
極全体が同じ位置に重複して配設された構造を有する従
来の積層セラミックコンデンサである。なお、このNo.
10,11の積層セラミックコンデンサにおいても、素
子厚=10μmであり、また、ギャップの距離Gは10
0μmである。
The sample of No. 10 is a conventional multilayer ceramic capacitor having no dummy electrode and having a structure as shown in FIG. 4 described above, and the sample of No. 11 is as shown in FIG. This is a conventional multilayer ceramic capacitor having a structure in which the whole electrode is overlapped at the same position when viewed from the stacking direction. This No.
Also in the multilayer ceramic capacitors 10 and 11, the element thickness is 10 μm, and the gap distance G is 10 μm.
0 μm.

【0026】なお、表1の、G,D1,D2,及びL1
(例えば、図3のモデルを参照)、それぞれ、(1) G =内部電極2とダミー電極の間の距離(2)1=短い方のダミー電極5aの長さ(3)2=長い方のダミー電極5bの長さ(4)1=電極の位置ずれ量(L)−ギャップ10の距離
(G) を示している。なお、上記(4)より、位置ずれ量LはL1
+Gとなる。すなわち、L1は、電極の位置がギャップ
10の距離Gよりどれだけ多くずれているかを示してお
り、L1=0のとき、電極がギャップ10の距離Gと同
じだけずれていることを意味している。
G, D 1 , D 2 , and L 1 in Table 1 (for example, see the model in FIG. 3) are as follows: (1) G = distance between the internal electrode 2 and the dummy electrode ( 2) D 1 = length of the shorter dummy electrode 5a (3) D 2 = length of the longer dummy electrode 5b (4) L 1 = displacement (L) of the electrode−distance of the gap 10 (G ). From the above (4) , the displacement L is L 1
+ G. In other words, L 1 indicates how much the position of the electrode is shifted from the distance G of the gap 10. When L 1 = 0, it means that the electrode is shifted by the same distance G as the gap 10. are doing.

【0027】表1に示すように、No.10及び11の試
料(従来例)の場合には、脱バインダーを行う前の時点
で、すでに素子に歪みが生じて、内部電極に湾曲がみら
れ、積層ブロックをカットして素子を切り出した時点で
デラミネーションの発生が認められた。
As shown in Table 1, in the case of the samples of Nos. 10 and 11 (conventional example), before the debinding was performed, the element was already distorted, and the internal electrode was curved. The occurrence of delamination was observed at the time when the device was cut out by cutting the laminated block.

【0028】これに対して、ギャップ幅Gを100〜1
0μm、D1を100μm、D2を200〜110μm、L1
を0又は50μm(No.6のみ)としたNo.1〜7の試料
の場合には、デラミネーションが発生せず、ショート不
良のない積層セラミックコンデンサが得られた。但し、
ギャップ幅Gが10μmと小さいNo.7の試料において
は、印刷精度の問題からわずかにショート不良の発生
(発生率2%)が認められた。
On the other hand, when the gap width G is 100 to 1
0 μm, D 1 is 100 μm, D 2 is 200 to 110 μm, L 1
In the case of the samples of Nos. 1 to 7 in which No. 1 was set to 0 or 50 μm (only No. 6), no delamination occurred and a multilayer ceramic capacitor free from short circuit was obtained. However,
In the sample of No. 7 in which the gap width G was as small as 10 μm, a short-circuit defect was slightly generated (occurrence rate: 2%) due to the problem of printing accuracy.

【0029】また、No.8及び9の試料については、デ
ラミネーションの発生は認められなかったが、素子厚
(7μm)に対して、ギャップの距離Gが5μmと小さい
ことからショート不良が発生している。このように、本
発明の積層セラミック電子部品においては、素子厚とギ
ャップの距離の関係も考慮することが望ましい。なお、
一般的には、各電極の、対応する電極との位置ずれ量L
を、ギャップの距離Gの50%以上とすることが望まし
い。
No delamination was observed in the samples of Nos. 8 and 9, but a short-circuit defect occurred because the gap distance G was as small as 5 μm with respect to the element thickness (7 μm). ing. As described above, in the multilayer ceramic electronic component of the present invention, it is desirable to consider the relationship between the element thickness and the gap distance. In addition,
In general, the displacement L of each electrode with respect to the corresponding electrode
Is preferably 50% or more of the gap distance G.

【0030】また、上記実施の形態では、積層セラミッ
クコンデンサを例にとって説明したが、本発明は、その
他にも、積層LC複合部品や積層アクチュエータ、積層
バリスタなどの、セラミック中に内部電極が配設された
種々のセラミック電子部品に適用することが可能であ
る。
In the above embodiment, a multilayer ceramic capacitor has been described as an example. However, the present invention is also applicable to a case in which internal electrodes are provided in ceramic, such as a multilayer LC composite component, a multilayer actuator, and a multilayer varistor. It can be applied to various ceramic electronic components.

【0031】また、上記実施の形態では、特に示してい
ないが、第1及び第2の内部電極と、第1及び第2のダ
ミー電極の各電極のうち、積み重ね方向から見た場合に
重複した位置に配設される電極の数が電極全体の60%
を越えると、内部電極の湾曲や、それに伴うデラミネー
ションなどが生じやすくなる傾向があるため、積み重ね
方向から見た場合に同じ位置に重複して配設される電極
の数が全体の60%以下になるようにすることが望まし
い。
Although not particularly shown in the above embodiment, of the first and second internal electrodes and the respective electrodes of the first and second dummy electrodes, they overlap when viewed from the stacking direction. 60% of the total number of electrodes placed
When the number of electrodes is more than 60%, the curvature of the internal electrodes and the accompanying delamination tend to be easily generated. It is desirable that

【0032】本発明はさらにその他の点においても上記
の実施の形態に限定されるものではなく、内部電極の積
層数や内部電極を構成する材料の種類、セラミック層の
厚みやセラミック層を構成する材料の種類などに関し、
発明の要旨の範囲内において種々の応用、変形を加える
ことが可能である。
The present invention is not limited to the above embodiment in other respects. The number of laminated internal electrodes, the type of material constituting the internal electrodes, the thickness of the ceramic layer, and the configuration of the ceramic layer are not limited. Regarding the type of material,
Various applications and modifications can be made within the scope of the invention.

【0033】[0033]

【発明の効果】上述のように、本発明の積層セラミック
電子部品は、セラミックを介して積み重ねられる第1及
び第2の内部電極と、第1及び第2のダミー電極の位置
を、一層ごと又は複数層ごとに、第1及び第2の内部電
極の引出し方向に平行な方向に所定の位置ずれ量Lだ
、意図的にずらせるようにしているので、第1及び第
2の内部電極と、第1及び第2のダミー電極の各電極の
すべてが、積み重ね方向から見た場合に同じ位置に重複
して配設されることを抑制して、内部電極の湾曲やそれ
によるデラミネーションなどの内部欠陥の発生を防止す
ることができる。
As described above, in the multilayer ceramic electronic component of the present invention, the position of the first and second internal electrodes and the position of the first and second dummy electrodes stacked on each other via the ceramic can be determined for each layer. For each of the plurality of layers , a predetermined positional deviation amount L is intentionally shifted in a direction parallel to the direction in which the first and second internal electrodes are drawn out. The second internal electrode and the first and second dummy electrodes are all prevented from being disposed at the same position when viewed from the stacking direction. This can prevent the occurrence of internal defects such as delamination.

【0034】また、各電極の位置ずれ量Lを、内部電極
とダミー電極の間の距離Gの50%以上にすることによ
り、歪みの発生を抑制して、デラミネーションなどの内
部欠陥の発生を確実に防止することができる。
Further, by setting the displacement L of each electrode to 50% or more of the distance G between the internal electrode and the dummy electrode, the generation of distortion is suppressed, and the generation of internal defects such as delamination is suppressed. It can be reliably prevented.

【0035】さらに、各電極のうち、積み重ね方向から
見た場合に同じ位置に重複して配設される電極が60%
を越えないようにすることにより、また、内部電極と前
記ダミー電極の間の距離Gを、積み重ね方向にとなり合
う電極間に介在するセラミック層の厚みより大きくする
ことにより、内部電極の積層数が増えた場合にも、歪み
やそれによるデラミネーションの発生を確実に防止する
ことが可能になり、本発明をより実効あらしめることが
できる。
Further, among the electrodes, 60% of the electrodes overlappingly arranged at the same position when viewed from the stacking direction are used.
By not exceeding the internal electrodes and the front
By making the distance G between the dummy electrodes greater than the thickness of the ceramic layer interposed between the adjacent electrodes in the stacking direction, even when the number of stacked internal electrodes increases, distortion and delamination due to the distortion occur. Can be reliably prevented, and the present invention can be made more effective.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態にかかる積層セラミック電
子部品の構造を示す断面図である。
FIG. 1 is a cross-sectional view showing a structure of a multilayer ceramic electronic component according to an embodiment of the present invention.

【図2】本発明の実施の形態にかかる積層セラミック電
子部品の構造の他の例を示す断面図である。
FIG. 2 is a cross-sectional view showing another example of the structure of the multilayer ceramic electronic component according to the embodiment of the present invention.

【図3】本発明の実施の形態にかかる積層セラミック電
子部品の構造のさらに他の例を示す断面図である。
FIG. 3 is a sectional view showing still another example of the structure of the multilayer ceramic electronic component according to the embodiment of the present invention.

【図4】従来の積層セラミックコンデンサを示す断面図
である。
FIG. 4 is a sectional view showing a conventional multilayer ceramic capacitor.

【図5】従来の積層セラミックコンデンサの他の例を示
す断面図である。
FIG. 5 is a cross-sectional view showing another example of a conventional multilayer ceramic capacitor.

【図6】従来の積層セラミックコンデンサのさらに他の
例を示す断面図である。
FIG. 6 is a sectional view showing still another example of the conventional multilayer ceramic capacitor.

【符号の説明】[Explanation of symbols]

1 セラミック 2(2a,2b) 内部電極 3 素子 4 外部電極 5(5a,5b) ダミー電極 6a,6b コンデンサ部 10(10a,10b) ギャップ G 内部電極とダミー電極の距離 D1 短い方のダミー電極の長さ D2 長い方のダミー電極の長さ L 電極の位置ずれ量 L1 電極の位置ずれ量(L)−ギ
ャップの距離(G)
1 ceramic 2 (2a, 2b) internal electrode 3 element 4 external electrode 5 (5a, 5b) dummy electrodes 6a, 6b capacitor section 10 (10a, 10b) gap G internal electrodes and the distance D 1 shorter dummy electrodes of the dummy electrode D 2 Length of the longer dummy electrode L Displacement of electrode L Displacement of electrode 1 (L) -Gap distance (G)

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 セラミック中に配設され、一端側が素子
の一方の端面に引き出された容量形成用の第1の内部電
極と、 前記第1の内部電極とセラミック層を介して対向する、
一端側が素子の前記第1の内部電極が引き出された端面
とは逆側の端面に引き出された容量形成用の第2の内部
電極と、 前記第1の内部電極の素子の端面に引き出されていない
方の端部側に、該端部と所定の距離Gをおいて配設され
た第1のダミー電極と、 前記第2の内部電極の素子の端面に引き出されていない
方の端部側に、該端部と所定の距離Gをおいて配設され
た第2のダミー電極と がセラミック層を介して交互に積み重ねられた構造を有
する積層セラミック電子部品であって、 第1及び第2の内部電極、及び第1及び第2のダミー電
極の各電極が、積み重ね方向から見た場合に同じ位置に
重複して配設されないように、第1及び第2の内部電極
と、第1及び第2のダミー電極の位置を、一層ごと又は
複数層ごとに、第1及び第2の内部電極の引出し方向に
平行な方向に所定の位置ずれ量Lだけ、意図的にずら
せたこと を特徴とする積層セラミック電子部品。
1. A first internal electrode for capacitance formation, which is provided in a ceramic and has one end side drawn out to one end face of an element, facing the first internal electrode via a ceramic layer,
One end side is drawn out to an end face of the element opposite to the end face from which the first internal electrode is drawn out, and a second internal electrode for forming a capacitance is drawn out to an end face of the element of the first internal electrode. A first dummy electrode disposed at a predetermined distance G from the other end, and an end not drawn to an end face of the element of the second internal electrode. A multilayer ceramic electronic component having a structure in which the end and a second dummy electrode disposed at a predetermined distance G are alternately stacked via a ceramic layer, The first and second internal electrodes, the first and second dummy electrodes, and the first and second internal electrodes, so that the respective electrodes of the first and second dummy electrodes are not disposed at the same position when viewed from the stacking direction. The position of the second dummy electrode is changed for each layer or for each layer by the first and second A multilayer ceramic electronic component characterized in that the multilayer ceramic electronic component is intentionally shifted by a predetermined position shift amount L in a direction parallel to a direction in which the internal electrodes are led out.
【請求項2】 前記各電極の、対応する電極との位置ず
れ量Lが、前記内部電極と前記ダミー電極の間の距離G
の50%以上であることを特徴とする請求項1記載の積
層セラミック電子部品。
2. The method according to claim 1, wherein the amount of displacement L between each of the electrodes and the corresponding electrode is a distance G between the internal electrode and the dummy electrode.
2. The multilayer ceramic electronic component according to claim 1, wherein the ratio is 50% or more.
【請求項3】 前記内部電極と、前記ダミー電極の各電
極のうち、積み重ね方向から見た場合に同じ位置に重複
して配設される電極の数が電極全体の60%を越えない
ことを特徴とする請求項1又は記載の積層セラミック電
子部品。
3. A method according to claim 1, wherein, of the internal electrodes and the dummy electrodes, the number of electrodes provided at the same position when viewed from the stacking direction does not exceed 60% of the total number of the electrodes. The multilayer ceramic electronic component according to claim 1, wherein:
【請求項4】 前記内部電極と前記ダミー電極の間の距
離Gを、積み重ね方向にとなり合う電極間に介在するセ
ラミック層の厚みよりも大きくしたことを特徴とする請
求項1,2又は3記載の積層セラミック電子部品。
4. The device according to claim 1, wherein a distance G between the internal electrode and the dummy electrode is larger than a thickness of a ceramic layer interposed between the adjacent electrodes in the stacking direction. Of multilayer ceramic electronic components.
JP02205596A 1996-01-11 1996-01-11 Multilayer ceramic electronic components Expired - Lifetime JP3316731B2 (en)

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JP3316731B2 true JP3316731B2 (en) 2002-08-19

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US6576523B1 (en) 1997-11-18 2003-06-10 Matsushita Electric Industrial Co., Ltd. Layered product, capacitor and a method for producing the layered product
JP2000012377A (en) * 1998-06-17 2000-01-14 Murata Mfg Co Ltd Laminated ceramic electronic component and manufacture of the same
JP2003017362A (en) * 2001-06-28 2003-01-17 Kyocera Corp Method of manufacturing ceramic laminate
US7152291B2 (en) 2002-04-15 2006-12-26 Avx Corporation Method for forming plated terminations
US7345868B2 (en) 2002-10-07 2008-03-18 Presidio Components, Inc. Multilayer ceramic capacitor with terminal formed by electroless plating
JP2005285801A (en) 2004-03-26 2005-10-13 Kyocera Corp Method of manufacturing stacked electronic component
TWI399765B (en) * 2005-01-31 2013-06-21 Tdk Corp Laminated electronic components
KR100944098B1 (en) 2005-08-19 2010-02-24 가부시키가이샤 무라타 세이사쿠쇼 Multilayer ceramic capacitor
JP4760857B2 (en) * 2008-05-29 2011-08-31 Tdk株式会社 Manufacturing method of multilayer electronic component
EP2449569B1 (en) 2009-07-01 2015-08-26 Kemet Electronics Corporation Multilayer capacitor with high capacitance and high voltage capability
KR101141402B1 (en) 2011-03-09 2012-05-03 삼성전기주식회사 A multilayer ceramic capacitor and a method for manufactuaring the same
JP2014027255A (en) * 2012-06-22 2014-02-06 Murata Mfg Co Ltd Ceramic electronic component and ceramic electronic device
KR101420517B1 (en) * 2012-10-31 2014-07-16 삼성전기주식회사 Multi-Layer Ceramic Capacitor and Printed Circuit Board embedding the same
KR102067173B1 (en) * 2013-02-25 2020-01-15 삼성전기주식회사 Multi-layered ceramic capacitor and manufacturing method of the same
JP6550737B2 (en) * 2014-12-09 2019-07-31 Tdk株式会社 Multilayer ceramic capacitor
JP2022021734A (en) * 2020-07-22 2022-02-03 太陽誘電株式会社 Ceramic electronic component and method of manufacturing the same
KR20240022827A (en) * 2022-08-12 2024-02-20 삼성전기주식회사 Multilayer capacitor

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