JP2005159056A - Laminated ceramic electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic electronic component capable of preventing internal defects at baking and occurrence of cracks due to an external shock. <P>SOLUTION: The laminated ceramic electronic component is configured such that internal electrodes 3, 4 are laminated with each of a plurality of first dielectric layers 2a inbetween to form a laminated body 1, a first dielectric layer 2b is coated and formed to both principal sides of the laminated body 1, and external electrodes 5, 6 electrically connected to the internal electrodes 3, 4 are coated and formed to end faces of the laminated body 1. The void rate of the first and second dielectric layers 2a, 2b is selected as 0.01% to 1.00%, and the void rate of the first dielectric layer 2a is higher than the void rate of the display second dielectric layer 2b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multilayer ceramic electronic component.

  As a typical multilayer ceramic electronic component, a multilayer ceramic capacitor will be described as an example.

  FIG. 4 is a cross-sectional view showing a conventional multilayer ceramic capacitor, in which the multilayer ceramic capacitor 30 includes a multilayer body 1 in which a plurality of dielectric layers 32 are stacked with internal electrodes 33 and 34 interposed therebetween, It is composed of external electrodes 35 and 36 which are deposited and formed on the end face of the laminate 1 and are electrically connected to the internal electrodes 33 and 34, respectively.

  Such a conventional multilayer ceramic capacitor 10 is manufactured by the following process.

  First, a conductive paste mixed with metal powder such as Cu and Ni, a binder resin, a solvent and the like is applied in a thin film on the ceramic green sheet 32 by a screen printing method or the like, and dried to form a conductive pattern 33 serving as an internal electrode. , 34 are formed.

  Next, a plurality of ceramic green sheets 32 on which the conductor patterns 33 and 34 are formed are stacked, and a plurality of ceramic green sheets 32 on which the conductor patterns 33 and 34 are not formed are stacked to form a large laminate.

Subsequently, the large laminate is cut into each element region to form an unfired laminate 31, and then the unfired laminate 31 is fired to obtain the laminate 31 and finally obtained. The laminated ceramic capacitor 30 is obtained by depositing and forming the external electrodes 35 and 36 on the pair of end portions of the laminated body 31 thus obtained.
Japanese Patent Laid-Open No. 3-91218 Japanese Patent No. 2804325 Japanese Patent No. 3047706

  However, in the conventional multilayer ceramic capacitor 30 described above, when the porosity of the dielectric layer 32 is low, as shown in FIG. 4A, the effect of relieving internal stress generated during firing is reduced. There was a problem that internal defects 42 such as lamination cracks occurred. On the other hand, when the porosity of the dielectric layer 32 is high, as shown in FIG. 4B, there is a problem that a crack 43 is generated in the laminate 31 due to an external impact.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a multilayer ceramic electronic component that can prevent internal defects during firing and cracks due to external impact.

  The multilayer ceramic electronic component of the present invention is formed by laminating a plurality of first dielectric layers with internal electrodes interposed therebetween, and depositing and forming a second dielectric layer on both main surfaces of the laminate, A multilayer ceramic electronic component formed by depositing and forming an external electrode electrically connected to the internal electrode on an end face of a body, wherein the porosity of the first dielectric layer and the second dielectric layer is 0 0.01% to 1.00%, and the porosity of the first dielectric layer is higher than the porosity of the second dielectric layer.

In the multilayer ceramic electronic component of the present invention, when the porosity of the first dielectric layer is P ₁ and the porosity of the second dielectric layer is P ₂ , the range is 1 <P ₁ / P ₂ ≦ 10. It is characterized by being set to.

  Furthermore, the multilayer ceramic electronic component of the present invention is characterized in that the porosity in the second dielectric layer is lower on the surface layer side than on the first dielectric layer side.

  According to the present invention, the porosity of the first dielectric layer is higher than the porosity of the second dielectric layer. That is, since the porosity of the first dielectric layer can be increased, internal defects such as delamination and cracks during firing can be prevented, and the porosity of the second dielectric layer can be decreased, so that the mechanical strength of the laminate can be reduced. And cracks due to external impact can be prevented. Furthermore, since the porosity of the first dielectric layer and the second dielectric layer is set to 0.01% to 1.00%, while preventing internal defects such as delamination and cracks during the firing, Even when the thickness of the first dielectric layer is reduced to 10 μm or less, there is no short circuit between the internal electrodes starting from the gap.

Further, when the porosity of the first dielectric layer is P ₁ and the porosity of the second dielectric layer is P ₂ , it is more effective because it is set in the range of 1 <P ₁ / P ₂ ≦ 10. In addition, it is possible to prevent a short circuit between the internal electrodes starting from the gap while preventing internal defects during the firing and cracking due to external impact.

  Furthermore, since the porosity in the second dielectric layer is lower on the surface layer side than on the first dielectric layer side, the porosity on the first dielectric layer side in the second dielectric layer can be increased. , Steps due to the presence or absence of internal electrodes can be reduced.

  Hereinafter, a method of manufacturing a multilayer ceramic electronic component according to the present invention will be described taking a case of manufacturing a multilayer ceramic capacitor as an example.

  1A is an external perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 1B is a longitudinal sectional view of the multilayer ceramic capacitor of FIG. 1A, and FIG. 2 is a multilayer ceramic capacitor of FIG. It is a figure which shows the manufacturing method of a capacitor | condenser.

  The multilayer ceramic capacitor 10 of the present embodiment is generally composed of a multilayer body 1 and external electrodes 5 and 6 that are deposited and formed on a pair of end faces of the multilayer body 1.

  The multilayer body 1 includes a plurality of dielectric layers 2a laminated with internal electrodes 3 and 4 formed therebetween, and a second dielectric layer 2b laminated on both main surfaces. 5. The internal electrode 4 and the external electrode 6 are electrically connected to each other.

  Here, the porosity of the first dielectric layer 2a and the second dielectric layer 2b is set to 0.01% to 1.00%, and the porosity of the first dielectric layer 2a is set to the second dielectric layer. Higher than the porosity of the layer 2b.

Also, _{P 1} the porosity of the first dielectric layer 2a, if the porosity of the second dielectric layer 2b was set to _{P 2,} is set in a range of _{1 <P 1 / P 2 ≦} 10.

  Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 of the present invention will be described. Note that reference numerals in the figure are used without distinction before and after firing.

First, a ceramic slurry in which a ceramic powder mainly composed of a dielectric material such as barium titanate (BaTiO ₃ ), a binder resin, a solvent, a plasticizer, a dispersant, etc. is mixed with a doctor blade method, a pulling method, a die coater, Using a gravure roll coater or the like, it is formed into a sheet and dried to form a ceramic green sheet 2a that becomes the first dielectric layer and a ceramic green sheet 2b that becomes the second dielectric layer.

  Here, the ratio of the binder resin contained in the ceramic green sheet 2a is made higher than the ratio of the binder resin contained in the ceramic green sheet 2b. For example, when the ratio of the binder resin contained in the ceramic green sheet 2a is 10%, the ratio of the binder resin contained in the ceramic green sheet 2b is set to 8%.

  Next, a conductive paste mixed with a metal powder such as Cu or Ni, a binder resin, a solvent, etc. is applied in a thin film on the ceramic green sheet 2a by a screen printing method or the like, and dried to form a conductive pattern serving as an internal electrode. 3 and 4 are formed.

  Next, a plurality of ceramic green sheets 2 b are stacked on the base plate 21. Further, the ceramic green sheets 2a on which the conductor patterns 3 and 4 are formed are alternately laminated. Further, the multilayer body 11 is formed by laminating a plurality of ceramic green sheets 2b.

  Next, the pressure-bonded laminated body 11 is formed by applying pressure in the stacking direction while heating the laminated body 11 formed on the base plate 21. Specifically, as shown in FIG. 2, the periphery of the multilayer body 11 formed on the base plate 21 is surrounded by a frame 23, and a rigid body plate 22 is disposed on the multilayer body 11, and these are flexible. It is put in the bag 24 and put into the pressurizing chamber of the hydrostatic pressure press apparatus while the inside is deaerated and sealed. At this time, a PET film or the like may be interposed therebetween so that the pressure-bonded laminate 11 is easily peeled off from the flexible bag 24.

  At this time, since the ratio of the binder resin contained in the ceramic green sheet 2a is higher than the ratio of the binder resin contained in the ceramic green sheet 2b, the ratio of the binder resin contained in the ceramic green sheet 2a can be increased. The delamination between the ceramic green sheet 2a and the conductor patterns 3 and 4 can be prevented. On the other hand, since the ratio of the binder resin contained in the ceramic green sheet 2b can be reduced, the ceramic green sheet 2b becomes the base plate 21 and the rigid plate 22. Breakage of the laminated crimped body 11 due to sticking can be prevented.

  Next, the pressure-bonded laminate 11 is cut into each element region to form the unfired laminate 1, and then the unfired laminate 1 is fired to obtain the laminate 1.

  At this time, since the ratio of the binder resin contained in the ceramic green sheet 2a is higher than the ratio of the binder resin contained in the ceramic green sheet 2b, the porosity of the first dielectric layer is the gap of the second dielectric layer. Higher than the rate.

  Finally, the external electrodes 5 and 6 are deposited and formed on the pair of end portions of the obtained multilayer body 1, thereby completing the multilayer ceramic capacitor 10 shown in FIG.

  According to the multilayer ceramic capacitor 10 of the present embodiment as described above, the porosity of the first dielectric layer 2a is higher than the porosity of the second dielectric layer 2b. That is, since the porosity of the first dielectric layer 2a can be increased, internal defects 42 such as delamination and cracks during firing can be prevented, and the porosity of the second dielectric layer 2b can be decreased. This improves the mechanical strength and prevents cracks 43 due to external impacts. Furthermore, since the porosity of the first dielectric layer 2a and the second dielectric layer 2b is set to 0.01% to 1.00%, internal defects 42 such as delamination and cracks during the firing are prevented. However, even when the thickness of the first dielectric layer 2a is reduced to 10 μm or less, there is no short circuit between the internal electrodes 3-4 starting from the gap.

In addition, when the porosity of the first dielectric layer 2a is P ₁ and the porosity of the second dielectric layer 2b is P ₂ , it is set in the range of 1 <P ₁ / P ₂ ≦ 10. Effectively, it is possible to prevent a short circuit between the internal electrodes 3-4 starting from the gap while preventing the internal defect 42 at the time of firing and the crack 43 due to external impact.

  It should be noted that the present invention is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the scope of the present invention.

  FIG. 3 is a longitudinal sectional view showing another embodiment of the present invention. As shown in FIG. 3, the dielectric layers 2b1 and 2b2 on which the internal electrodes 3 and 4 are not formed are laminated, and the porosity is The relationship 2a <2b1 <2a may be satisfied. That is, since the porosity of the dielectric layer 2b1 can be higher than that of the dielectric layer 2b2, there is also an effect that the step due to the presence or absence of the internal electrodes 3 and 4 can be reduced.

  In addition, as shown in FIG. 2, when the laminated body 11 is formed on the base plate 21 and heated in the laminating direction while being heated, the ceramic green sheet 2a and the conductor are formed. While preventing delamination between the patterns 3 and 4 and the damage of the laminated crimped body 11 due to the ceramic green sheet 2b2 sticking to the base plate 21 or the rigid plate 22, the portion where the ceramic green sheet 2a is laminated and the ceramic It is also possible to prevent delamination between the portions where the green sheets 2b2 are laminated.

  Furthermore, in the above-described embodiment, the example in which the present invention is applied to the method for manufacturing the multilayer ceramic capacitor 10 has been described. However, the present invention is applicable to manufacturing all the multilayer ceramic electronic components 10 such as circuit boards, multilayer piezoelectric components, and semiconductor components. Applicable to the method.

The inventor controls the porosity P ₁ of the first dielectric layer 2a and the porosity P ₂ of the second dielectric layer 2a by changing the ratio of the binder resin contained in the ceramic green sheets 2a and 2b. A laminated ceramic capacitor 10 was produced.

  About the obtained multilayer ceramic capacitor 10, the incidence rate of the internal defect 42 at the time of baking and the incidence rate of the crack 43 at the time of mounting were calculated | required.

  The rate of occurrence of internal defects 42 during firing was determined by polishing 100 laminated bodies 1 and observing them with a metallurgical microscope to determine the occurrence rate of delamination cracks.

  The incidence of cracks 43 during mounting should be observed with a metal microscope after 100 multilayer ceramic capacitors 10 are surface-mounted by soldering onto a wiring pattern on a 1.6 mm thick glass epoxy substrate (wiring substrate). Thus, the occurrence rate of cracks was obtained.

The results are shown in Table 1.

As shown in Table 1, the porosity of the first dielectric layer 2a and the second dielectric layer 2b is set to 0.01% to 1.00%, and 1 <P ₁ / P ₂ ≦ 10. In this example (sample numbers 2 to 7) in the range, the occurrence rate of internal defects 42 during firing and the occurrence rate of cracks 43 during mounting were both 0%.

On the other hand, in the comparative example (sample number 1) in which P ₁ = P ₂ = 0.01%, 2% of internal defects 42 during firing occurred. On the other hand, in the comparative example (sample number 8) in which P ₁ = P ₂ = 1.00%, 1% of cracks 43 during mounting occurred.

From these results, in the multilayer ceramic capacitor 10 of the present invention, the porosity of the first dielectric layer 2a and the second dielectric layer 2b is set to 0.01% to 1.00%, and 1 <P _Since it is in the range of ₁ / P ₂ ≦ 10, it was found that the internal defects 42 during firing and the cracks 43 due to external impact can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the multilayer ceramic electronic component (multilayer ceramic capacitor) concerning one Embodiment of this invention, (a) is an external appearance perspective view, (b) is a longitudinal cross-sectional view. It is sectional drawing which shows the manufacturing method of the multilayer ceramic capacitor of FIG. It is a longitudinal cross-sectional view of the multilayer ceramic electronic component concerning other embodiment of this invention. It is sectional drawing which shows the problem of the conventional multilayer ceramic capacitor, (a) is sectional drawing which shows a mode that the internal defect was formed at the time of baking, (b) is sectional drawing which shows a mode that the crack was formed by the external impact It is.

Explanation of symbols

10 ····························································· 1st dielectric layer (ceramic green sheet)
2b ... Second dielectric layer (ceramic green sheet)
3, 4, ... Internal electrodes (conductor pattern)
5, 6 ········ External electrode 11 ········· Press-bonded laminated body (laminated body)
21 ..... Base plate 22 ..... Rigid plate 23 ..... Frame 24 ..... Flexible bag

Claims (3)

A plurality of first dielectric layers are laminated with an internal electrode therebetween, and a second dielectric layer is deposited and formed on both main surfaces of the laminated body, and the internal electrode is electrically connected to the end face of the laminated body. A laminated ceramic electronic component formed by depositing and forming externally connected external electrodes,
The porosity of the first dielectric layer and the second dielectric layer is set to 0.01% to 1.00%, and the porosity of the first dielectric layer is that of the second dielectric layer. A multilayer ceramic electronic component characterized by being higher than the porosity. When the porosity of the first dielectric layer is P ₁ and the porosity of the second dielectric layer is P ₂ , the range is set to 1 <P ₁ / P ₂ ≦ 10. The multilayer ceramic electronic component according to claim 1. 3. The multilayer ceramic electronic component according to claim 1, wherein the porosity in the second dielectric layer is lower on the surface layer side than on the first dielectric layer side. 4.

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