JP2003272945A - Laminated ceramic electronic component and its manufacturing method - Google Patents

Laminated ceramic electronic component and its manufacturing method

Info

Publication number
JP2003272945A
JP2003272945A JP2002075745A JP2002075745A JP2003272945A JP 2003272945 A JP2003272945 A JP 2003272945A JP 2002075745 A JP2002075745 A JP 2002075745A JP 2002075745 A JP2002075745 A JP 2002075745A JP 2003272945 A JP2003272945 A JP 2003272945A
Authority
JP
Japan
Prior art keywords
electrode
electrodes
internal
conductor layer
capacitance forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002075745A
Other languages
Japanese (ja)
Other versions
JP3985557B2 (en
Inventor
Takeki Kamata
雄樹 鎌田
Tatsuo Kikuchi
立郎 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002075745A priority Critical patent/JP3985557B2/en
Publication of JP2003272945A publication Critical patent/JP2003272945A/en
Application granted granted Critical
Publication of JP3985557B2 publication Critical patent/JP3985557B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic electronic component which can be easily and variously changed in electrostatic capacity by changing the overlap of an internal electrode in one pattern even if an internal electrode is reduced in its connection with an external electrode, and to provide its manufacturing method. <P>SOLUTION: The internal electrode is composed of first internal electrodes 110 to 140 located on one side and second internal electrodes 210 to 240 located on the other side, and the first internal electrodes 110 to 140 and the second internal electrodes 210 to 240 are separated from each other by a dielectric layer 100. The first electrodes and the second electrodes are equipped with capacity forming electrodes 110a and 210a, leading electrodes 110b and 210b connecting the capacity forming electrodes 110a and 210a to an external electrode, and dummy electrodes 110c and 210c which are not connected to the capacity forming electrodes 110a and 210a but connected to the external electrode, and the leading electrodes and the dummy electrodes are nearly equal to each other and smaller in width than the capacity forming electrodes. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、例えば積層セラミ
ックコンデンサなどの積層セラミック電子部品およびそ
の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic electronic component such as a monolithic ceramic capacitor and a method for manufacturing the same.

【0002】[0002]

【従来の技術】昨今のコンピュータや携帯電話に代表さ
れる情報通信機器の小型化に伴い、電子部品の高密度実
装が進行する中で積層セラミック電子部品においては小
型化が望まれている。特に、代表的な積層セラミック電
子部品である積層セラミックコンデンサにおいては小型
化とともに大容量化が望まれている。
2. Description of the Related Art With the recent miniaturization of information communication equipment typified by computers and mobile phones, miniaturization of laminated ceramic electronic components is desired as high-density mounting of electronic components progresses. In particular, in a monolithic ceramic capacitor, which is a typical monolithic ceramic electronic component, it is desired to reduce the size and increase the capacity.

【0003】そして、実装面積低減と実装回数削減によ
るコスト低減の要求から単一素体内にコンデンサを複数
個並設した多連形の積層セラミックコンデンサも開発さ
れ使用されてきており、多連形の積層セラミックコンデ
ンサにおいても小型化、大容量化が要望されている。
In order to reduce the mounting area and cost by reducing the number of times of mounting, a multi-layer type monolithic ceramic capacitor in which a plurality of capacitors are arranged side by side in a single element has been developed and used. There is also a demand for miniaturization and large capacity in multilayer ceramic capacitors.

【0004】従来の多連形の積層セラミックコンデンサ
について、図13を参照して説明する。図13は従来の
多連形の積層セラミックコンデンサの内部電極の構造を
示す模式的分解斜視図である。
A conventional multi-layer type monolithic ceramic capacitor will be described with reference to FIG. FIG. 13 is a schematic exploded perspective view showing a structure of an internal electrode of a conventional multi-layer type monolithic ceramic capacitor.

【0005】図13に示すように、従来の多連形の積層
セラミックコンデンサは、誘電体層3を挟んで第1の内
部電極1と第2の内部電極2とが交互に積層され、第1
の内部電極1および第2の内部電極2は同一平面に複数
(図13では4個)が形成され、この素体の相対向する
端面に内部電極の複数対が交互に露出し、この露出した
内部電極に接続するように複数対の外部電極(図示せ
ず)を形成している。また、多連形の積層セラミックコ
ンデンサは外部電極の形状を小さくする必要があるた
め、図13に示すように、第1の内部電極1および第2
の内部電極2は、容量形成電極部1a,2aと引出し電
極部1b,2bとを設け、引出し電極部1b,2bの幅
寸法を容量形成電極部1a,2aに比べ小さくし、外部
電極との接続部分の寸法を小さくしている。
As shown in FIG. 13, in a conventional multi-layer type monolithic ceramic capacitor, a first internal electrode 1 and a second internal electrode 2 are alternately laminated with a dielectric layer 3 sandwiched between them.
A plurality of internal electrodes 1 and second internal electrodes 2 (4 in FIG. 13) are formed on the same plane, and a plurality of pairs of internal electrodes are alternately exposed on the end faces of the element body facing each other. A plurality of pairs of external electrodes (not shown) are formed so as to connect to the internal electrodes. Further, in the multi-layer type monolithic ceramic capacitor, it is necessary to reduce the shape of the external electrodes, and therefore, as shown in FIG.
The internal electrode 2 has capacitance forming electrode portions 1a, 2a and lead electrode portions 1b, 2b, and the width dimensions of the lead electrode portions 1b, 2b are made smaller than those of the capacitance forming electrode portions 1a, 2a, so The size of the connecting part is reduced.

【0006】一方、積層セラミックコンデンサの静電容
量は、内部電極の重なり面積、内部電極に挟まれた誘電
体層の有効層数、誘電体層の厚みおよび誘電体層の比誘
電率によって決定される。したがって、所望の静電容量
を得るためには、上記の各因子のいずれか一つまたは複
数を変更して行う。
On the other hand, the electrostatic capacitance of the monolithic ceramic capacitor is determined by the overlapping area of the internal electrodes, the number of effective layers of the dielectric layers sandwiched by the internal electrodes, the thickness of the dielectric layers and the relative dielectric constant of the dielectric layers. It Therefore, in order to obtain a desired capacitance, one or more of the above factors are changed.

【0007】しかしながら、非常に多種類の比誘電率の
異なる誘電体セラミック材料を作製することや非常に多
種類の厚みの誘電体層となるセラミック生シートを作製
することは煩雑で生産効率が悪い。また、有効層数での
調整は静電容量の微調整ができない。したがって、通
常、面積が異なる多種類の内部電極となる導体層パター
ンを用意して、誘電体層の厚みや有効層数を変化させる
と共に、静電容量設計に応じた導体層パターンを使用し
て内部電極の重なり面積を変えて所望の静電容量を得る
ことが一般的である。しかし、非常に多種類の導体層パ
ターンの印刷版を揃えることも、製版コストがかさみ、
製品の低コスト化が困難となる問題が生じる。
However, it is cumbersome to produce a great variety of types of dielectric ceramic materials having different relative dielectric constants, or to produce a ceramic green sheet as a dielectric layer having a great variety of thicknesses, and the production efficiency is poor. . In addition, the capacitance cannot be finely adjusted by adjusting the number of effective layers. Therefore, in general, prepare conductor layer patterns that will be various types of internal electrodes with different areas, change the thickness of the dielectric layer and the number of effective layers, and use conductor layer patterns according to the capacitance design. It is common to obtain a desired capacitance by changing the overlapping area of the internal electrodes. However, arranging printing plates with a great variety of conductor layer patterns also increases plate making costs,
There is a problem that it becomes difficult to reduce the cost of the product.

【0008】このため、従来の多連形の積層セラミック
コンデンサにおいて、1種類の導体層パターンを用いて
内部電極の重なり面積を変えることができ多種類の静電
容量を得る方法として、特開2001−203122公
報のように、容量形成部の2辺から相対向する両端面へ
延ばされている第1、第2の引出し部がそれぞれ設けら
れた内部電極となる導体層パターンを用いて、この1種
類の導体層パターンの第1、第2の引出し部が交互に相
対向する端面から露出するよう対向方向に交互にずらし
て積層するとともに、ずらし量を調整することで内部電
極間の重なり面積を変化させて静電容量を調整するとい
う方法も提案されている。
Therefore, in a conventional multi-layer type monolithic ceramic capacitor, a method of changing the overlapping area of the internal electrodes by using one kind of conductor layer pattern and obtaining a large number of kinds of electrostatic capacitance is disclosed in Japanese Patent Laid-Open No. 2001-2001. As disclosed in Japanese Patent Application Laid-Open No.-203122, by using a conductor layer pattern serving as an internal electrode provided with first and second lead portions extending from two sides of the capacitance forming portion to opposite end faces thereof, The first and second lead portions of one type of conductor layer pattern are alternately staggered in the facing direction so that they are exposed from the end faces that are facing each other, and the amount of shift is adjusted to overlap the internal electrodes. There is also proposed a method of adjusting the electrostatic capacity by changing.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、上記特
開2001−203122公報の方法では、容量形成部
の2辺から相対向する両端面へ延ばされている第1、第
2の引出し部がそれぞれ設けられた導体層パターンを用
いるので、誘電体層を挟んで向かい合う容量形成部の面
積が制限され内部電極の重なり面積を大きくすることが
できないため、大容量化を図る上で不適であるという問
題がある。
However, in the method of the above-mentioned Japanese Patent Application Laid-Open No. 2001-203122, the first and second lead portions extending from the two sides of the capacitance forming portion to the opposite end surfaces thereof are respectively provided. Since the provided conductor layer pattern is used, the area of the capacitance forming portions facing each other across the dielectric layer is limited, and the overlapping area of the internal electrodes cannot be increased, which is not suitable for increasing the capacitance. There is.

【0010】本発明は上記従来の問題点を解決するもの
で、1種類の導体層パターンを用いて内部電極の重なり
を変えることができ多種類の静電容量が容易に得られる
とともに、内部電極の重なり面積を大きくして大容量化
が図れる積層セラミック電子部品およびその製造方法を
提供することを目的とするものである。
The present invention solves the above-mentioned problems of the prior art. It is possible to change the overlap of the internal electrodes by using one type of conductor layer pattern and easily obtain a large number of types of capacitances, and at the same time, to obtain the internal electrodes. It is an object of the present invention to provide a monolithic ceramic electronic component capable of increasing the overlapping area by increasing the capacity and a manufacturing method thereof.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に、本発明は以下の構成を有するものである。
In order to achieve the above object, the present invention has the following constitution.

【0012】本発明の請求項1に記載の発明は、誘電体
層と内部電極とを交互に積層した積層焼結体とこの積層
焼結体の表面に設けた対向する第1の外部電極と第2の
外部電極とを備えた積層セラミック電子部品であって、
前記内部電極は、誘電体層を挟んで設けた第1の内部電
極と第2の内部電極とを備え、前記第1および第2の内
部電極は、それぞれ同一層に容量形成電極とこの容量形
成電極と一方の外部電極とを接続する引出し電極と前記
容量形成電極に非接続で他方の外部電極に接続するダミ
ー電極とを有し、前記引出し電極および前記ダミー電極
の幅はほぼ同一でかつ前記容量形成電極に比して小であ
り、前記第2の内部電極の形状は、前記第1の内部電極
と略同一形状を略180度回転させた形状であるという
構成を備えており、これにより、内部電極が容量形成電
極部に比べ引出し電極部の幅寸法を小さくして外部電極
との接続部の寸法を小さくする必要がある形状である場
合においても、所望の静電容量を得るための内部電極の
重なり面積の変更が最少1種類の導体層パターンででき
るので、容易に多種類の静電容量を得られる積層セラミ
ック電子部品となるとともに、従来に比べて内部電極の
重なり面積が大きくでき、かつ変更できる重なり面積の
幅つまり静電容量の範囲が大きくできる積層セラミック
電子部品となるという作用効果が得られる。
The invention according to claim 1 of the present invention comprises: a laminated sintered body in which dielectric layers and internal electrodes are alternately laminated; and a first external electrode facing the surface of the laminated sintered body. A multilayer ceramic electronic component including a second external electrode, comprising:
The internal electrode includes a first internal electrode and a second internal electrode that are provided with a dielectric layer sandwiched therebetween, and the first and second internal electrodes are respectively formed with a capacitance forming electrode and a capacitance forming electrode in the same layer. An extraction electrode connecting the electrode and one external electrode and a dummy electrode connected to the other external electrode without being connected to the capacitance forming electrode, and the extraction electrode and the dummy electrode have substantially the same width and The second internal electrode is smaller than the capacitance forming electrode, and the shape of the second internal electrode is the same as the first internal electrode rotated by approximately 180 degrees. In order to obtain a desired capacitance even when the internal electrode has a shape in which the width dimension of the extraction electrode portion needs to be smaller than the capacitance forming electrode portion to reduce the dimension of the connection portion with the external electrode. Changing the overlapping area of internal electrodes Since it can be made with a minimum of one kind of conductor layer pattern, it becomes a multilayer ceramic electronic component that can easily obtain many kinds of capacitances, and the overlapping area of the internal electrodes can be made larger and the overlapping area width that can be changed compared to the conventional one. That is, it is possible to obtain the function and effect that the multilayer ceramic electronic component can have a large electrostatic capacitance range.

【0013】また、外部電極に接続する内部電極とし
て、容量形成電極に接続する引出し電極のほかに容量形
成電極に非接続のダミー電極が設けてあるので、外部電
極と内部電極との接続強度が向上し信頼性の高い積層セ
ラミック電子部品となるという作用効果が得られる。
Further, as the internal electrode connected to the external electrode, in addition to the extraction electrode connected to the capacitance forming electrode, a dummy electrode not connected to the capacitance forming electrode is provided, so that the connection strength between the external electrode and the internal electrode is improved. It is possible to obtain the function and effect that the multilayer ceramic electronic component is improved and has high reliability.

【0014】本発明の請求項2に記載の発明は、特に、
ダミー電極と容量形成電極の間隔は誘電体層1層当りの
厚みの3倍以上であるという構成を有しており、これに
より、ダミー電極と容量形成電極との間の十分な電気絶
縁性が確保できるばかりでなく、積層ずれ切断ずれ等に
より外部電極と対向する内部電極との間隔が誘電体層1
層当りの厚みの3倍以下に近接した場合、これを容量測
定により選別除去することができる。したがって、外部
電極と対向する内部電極との間で絶縁破壊する危険性の
高い製品をあらかじめ除去でき信頼性の高い積層セラミ
ック電子部品となるという作用効果が得られる。
The invention according to claim 2 of the present invention is
The distance between the dummy electrode and the capacitance forming electrode is three times or more the thickness per one dielectric layer, which provides sufficient electrical insulation between the dummy electrode and the capacitance forming electrode. Not only can it be ensured, but the gap between the external electrode and the internal electrode facing the dielectric layer 1 due to stacking deviation, cutting deviation, etc.
When it is close to 3 times or less of the thickness per layer, it can be selectively removed by capacitance measurement. Therefore, a product having a high risk of dielectric breakdown between the external electrode and the facing internal electrode can be removed in advance, and a highly reliable laminated ceramic electronic component can be obtained.

【0015】本発明の請求項3に記載の発明は、誘電体
層と内部電極とを交互に積層した積層焼結体とこの積層
焼結体の表面に設けた複数対の対向する第1の外部電極
と第2の外部電極とを備えた多連形の積層セラミック電
子部品であって、前記内部電極は、誘電体層を挟んで設
けた第1の内部電極と第2の内部電極とを備え、前記第
1および第2の内部電極は、それぞれ同一層に容量形成
電極とこの容量形成電極と一方の外部電極とを接続する
引出し電極と前記容量形成電極に非接続で他方の外部電
極に接続するダミー電極とを有し、前記引出し電極およ
び前記ダミー電極の幅はほぼ同一でかつ前記容量形成電
極に比して小であり、前記第2の内部電極の形状は、前
記第1の内部電極と略同一形状を略180度回転させた
形状であり、前記第1および第2の内部電極はそれぞれ
複数を同一層に並設した構成であり、これにより、内部
電極が容量形成電極部に比べ引出し電極部の幅寸法を小
さくして外部電極との接続部の寸法を小さくする必要が
ある形状である場合においても、所望の静電容量を得る
ための内部電極の重なり面積の変更が最少1種類の導体
層パターンでできるので、容易に多種類の静電容量を得
られる多連形の積層セラミック電子部品となるととも
に、従来に比べて内部電極の重なり面積が大きくでき、
かつ変更できる重なり面積の幅つまり静電容量の範囲が
大きくできる多連形の積層セラミック電子部品となると
いう作用効果が得られる。
According to a third aspect of the present invention, there is provided a laminated sintered body in which dielectric layers and internal electrodes are alternately laminated, and a plurality of pairs of opposing first laminated bodies provided on the surface of the laminated sintered body. A multi-layered laminated ceramic electronic component including an external electrode and a second external electrode, wherein the internal electrode includes a first internal electrode and a second internal electrode sandwiching a dielectric layer. The first and second internal electrodes are respectively connected to a capacitance forming electrode in the same layer, a lead-out electrode connecting the capacitance forming electrode and one external electrode, and the other external electrode not connected to the capacitance forming electrode. A dummy electrode to be connected, the widths of the extraction electrode and the dummy electrode are substantially the same and smaller than that of the capacitance forming electrode, and the shape of the second internal electrode is the first internal The electrode has a shape substantially the same as that of the electrode rotated by about 180 degrees. Each of the first and second internal electrodes has a structure in which a plurality of them are arranged side by side in the same layer, which makes the width of the extraction electrode portion of the internal electrode smaller than that of the capacitance forming electrode portion and reduces the width of the connection portion with the external electrode. Even in the case of a shape that needs to be reduced in size, it is possible to change the overlapping area of the internal electrodes in order to obtain the desired capacitance with at least one type of conductor layer pattern, so that it is possible to easily use various types of capacitance. In addition to being a multi-layer type monolithic ceramic electronic component that can be obtained, the overlapping area of internal electrodes can be increased compared to conventional products,
In addition, it is possible to obtain the operational effect that the multi-layered monolithic ceramic electronic component in which the width of the overlapping area that can be changed, that is, the electrostatic capacitance range can be increased.

【0016】また、外部電極に接続する内部電極とし
て、容量形成電極に接続する引出し電極のほかに容量形
成電極に非接続のダミー電極が設けてあるので、外部電
極と内部電極との接続強度が向上し信頼性の高い多連形
の積層セラミック電子部品となるという作用効果が得ら
れる。
Further, as the internal electrode connected to the external electrode, in addition to the extraction electrode connected to the capacitance forming electrode, a dummy electrode not connected to the capacitance forming electrode is provided, so that the connection strength between the external electrode and the internal electrode is increased. It is possible to obtain the function and effect that the multi-layered ceramic electronic component is improved and has high reliability.

【0017】本発明の請求項4に記載の発明は、特に、
複数対の外部電極を備えた多連形の積層セラミック電子
部品であって、ダミー電極と容量形成電極の間隔は誘電
体層1層当りの厚みの3倍以上であるという構成を有し
ており、これにより、ダミー電極と容量形成電極との間
の十分な電気絶縁性が確保できるばかりでなく、積層ず
れ切断ずれ等により外部電極と対向する内部電極との間
隔が誘電体層1層当りの厚みの3倍以下に近接した場
合、これを容量測定により選別除去することができる。
したがって、外部電極と対向する内部電極との間で絶縁
破壊する危険性の高い製品をあらかじめ除去でき信頼性
の高い多連形の積層セラミック電子部品となるという作
用効果が得られる。
The invention according to claim 4 of the present invention is
A multi-layered laminated ceramic electronic component having a plurality of pairs of external electrodes, wherein the distance between the dummy electrode and the capacitance forming electrode is at least three times the thickness of one dielectric layer. As a result, not only sufficient electrical insulation between the dummy electrode and the capacitance forming electrode can be ensured, but also the distance between the external electrode and the internal electrode opposed to each other due to stacking error, cutting error, etc. When it is close to 3 times or less of the thickness, it can be selectively removed by capacitance measurement.
Therefore, a product having a high risk of dielectric breakdown between the external electrode and the facing internal electrode can be removed in advance, and a highly reliable multi-layered multilayer ceramic electronic component can be obtained.

【0018】本発明の請求項5に記載の発明は、特に、
複数対の外部電極および同一層に複数並設した内部電極
は、その外部電極のピッチと前記内部電極の容量形成電
極のピッチとが異なるという構成を有しており、これに
より、複数を同一層に並設した内部電極の容量形成電極
のピッチを外部電極のピッチに合わせる必要がなく容量
形成電極の配置の自由度が増し、外形寸法を大きくする
ことなく容量形成電極の面積を大きくできるので、小型
大容量化が可能な多連形の積層セラミック電子部品とな
るという作用効果が得られる。
The invention according to claim 5 of the present invention is
A plurality of pairs of external electrodes and a plurality of internal electrodes arranged side by side in the same layer have a configuration in which the pitch of the external electrodes and the pitch of the capacitance forming electrodes of the internal electrodes are different, and thus a plurality of external electrodes are formed in the same layer. Since it is not necessary to match the pitch of the capacitance forming electrodes of the internal electrodes arranged in parallel with the pitch of the external electrodes, the degree of freedom in arranging the capacitance forming electrodes is increased, and the area of the capacitance forming electrodes can be increased without increasing the external dimensions, It is possible to obtain a function and effect that it becomes a multi-layer type monolithic ceramic electronic component capable of being downsized and having a large capacity.

【0019】本発明の請求項6に記載の発明は、セラミ
ック生シートと内部電極となる導体層とを交互に積層し
て積層体ブロックを作製する第1工程と、この積層体ブ
ロックを個片に切断分離し焼成して積層焼結体を作製す
る第2工程と、この積層焼結体に外部電極を形成する第
3工程と、これを検査する第4工程とを備え、前記第1
工程において、前記内部電極となる導体層の形成は、容
量形成電極となる矩形状パターンとこれに接続する引出
し電極およびダミー電極となる帯状パターンとからなる
導体層パターンを縦横に多数個配列した導体層パターン
群を用いて行う第1電極形成工程と、前記導体層パター
ン群と略同一の導体層パターン群を略180度回転させ
て行う第2電極形成工程とを、交互に繰り返して行う積
層セラミック電子部品の製造方法であり、これにより、
内部電極が容量形成電極部に比べ引出し電極部の幅寸法
を小さくして外部電極との接続部の寸法を小さくする必
要がある形状である積層セラミック電子部品において
も、所望の静電容量を得るための内部電極の重なり面積
の変更が最少1種類の導体層パターンでできるので、製
版コストが低減でき製品の低コスト化が図れるととも
に、所望の多種類の静電容量の積層セラミック電子部品
が容易に製造できるという作用効果が得られる。
According to a sixth aspect of the present invention, the first step of producing a laminated body block by alternately laminating a ceramic green sheet and a conductor layer to be an internal electrode, and separating the laminated body block into individual pieces. The method further comprises a second step of manufacturing a laminated sintered body by cutting and separating into a plurality of layers, firing, a third step of forming an external electrode on the laminated sintered body, and a fourth step of inspecting the external electrode.
In the step, the formation of the conductor layer serving as the internal electrode is performed by arranging a large number of conductor layer patterns, each of which is composed of a rectangular pattern serving as a capacitance forming electrode and a strip pattern serving as a lead electrode and a dummy electrode connected to the conductor pattern, vertically and horizontally. A laminated ceramic in which a first electrode forming step performed using a layer pattern group and a second electrode forming step performed by rotating a conductor layer pattern group substantially the same as the conductor layer pattern group by about 180 degrees are alternately repeated. It is a method of manufacturing electronic parts, and
The desired capacitance can be obtained even in a monolithic ceramic electronic component in which the internal electrode has a shape in which the width of the extraction electrode portion needs to be smaller than that of the capacitance forming electrode portion to reduce the dimension of the connection portion with the external electrode. Because the overlapping area of the internal electrodes can be changed with at least one type of conductor layer pattern, plate making cost can be reduced, product cost can be reduced, and desired multilayer ceramic electronic parts with various capacitances can be easily manufactured. The effect that it can be manufactured is obtained.

【0020】また、従来に比べて内部電極の重なり面積
が大きくでき、かつ変更できる重なり面積の幅つまり静
電容量の範囲が大きくでき、積層セラミック電子部品の
大容量化が図れるという作用効果が得られる。
In addition, the overlapping area of the internal electrodes can be increased and the width of the overlapping area that can be changed, that is, the range of the electrostatic capacity can be increased as compared with the conventional case, so that the capacity of the laminated ceramic electronic component can be increased. To be

【0021】本発明の請求項7に記載の発明は、特に、
第2電極形成工程において、第1電極形成工程と同一の
導体層パターン群を用いこれを略180度回転させて内
部電極となる導体層を形成する積層セラミック電子部品
の製造方法であり、これにより、内部電極が容量形成電
極部に比べ引出し電極部の幅寸法を小さくして外部電極
との接続部の寸法を小さくする必要がある形状である積
層セラミック電子部品においても、導体層パターンを形
成するために必要な印刷版の数は一つであり、一つの印
刷版により内部電極の重なり面積の変更ができるので、
製版コストが極限まで低減でき製品の低コスト化が図れ
るという作用効果が得られる。
The invention according to claim 7 of the present invention is
In the second electrode forming step, the same conductor layer pattern group as in the first electrode forming step is used, and the conductor layer pattern group is rotated about 180 degrees to form a conductor layer to be an internal electrode. The conductor layer pattern is formed even in a multilayer ceramic electronic component in which the internal electrode has a shape in which the width dimension of the extraction electrode section needs to be smaller than that of the capacitance forming electrode section to reduce the dimension of the connection section with the external electrode. The number of printing plates required for this is one, and since the overlapping area of the internal electrodes can be changed with one printing plate,
The plate-making cost can be reduced to the utmost limit and the cost of the product can be reduced.

【0022】本発明の請求項8に記載の発明は、特に、
第2電極形成工程において、第1電極形成工程の導体層
パターン群と略同一形状を略180度回転させた形状の
導体層パターン群を用いて内部電極となる導体層を形成
する積層セラミック電子部品の製造方法であり、これに
より、内部電極が容量形成電極部に比べ引出し電極部の
幅寸法を小さくして外部電極との接続部の寸法を小さく
する必要がある形状である積層セラミック電子部品にお
いても、導体層パターンを形成するために必要な印刷版
の数は二つであり、わずか二つの印刷版により内部電極
の重なり面積の変更ができるので、製版コストが大幅に
低減でき製品の低コスト化が図れるという作用効果が得
られる。
The invention according to claim 8 of the present invention is
In the second electrode forming step, a multilayer ceramic electronic component for forming a conductor layer to be an internal electrode by using a conductor layer pattern group having a shape obtained by rotating the same shape as the conductor layer pattern group in the first electrode forming step by about 180 degrees In the multilayer ceramic electronic component in which the internal electrode has a shape in which it is necessary to reduce the width dimension of the extraction electrode section and the dimension of the connection section with the external electrode as compared with the capacitance forming electrode section, However, the number of printing plates required to form the conductor layer pattern is two, and because the overlapping area of the internal electrodes can be changed with only two printing plates, the plate making cost can be significantly reduced and the product cost can be reduced. It is possible to obtain the action and effect.

【0023】本発明の請求項9に記載の発明は、特に、
静電容量を測定して外部電極と対向する内部電極との間
隔が近接した不良品を選別除去する方法であり、これに
より、外部電極と対向する内部電極との間で絶縁破壊す
る危険性の高い製品をあらかじめ除去でき信頼性の高い
積層セラミック電子部品が容易に製造できるという作用
効果が得られる。
The invention according to claim 9 of the present invention is
This is a method to measure and remove the defective product in which the distance between the external electrode and the facing internal electrode is close, and to remove the defective product, which may cause dielectric breakdown between the external electrode and the facing internal electrode. It is possible to remove expensive products in advance and easily manufacture a highly reliable multilayer ceramic electronic component.

【0024】[0024]

【発明の実施の形態】(実施の形態1)以下、実施の形
態1を用いて、本発明の特に請求項1、請求項2、請求
項3、請求項4、請求項6、請求項7および請求項9に
記載の発明について積層セラミックコンデンサを例に説
明する。
DETAILED DESCRIPTION OF THE INVENTION (Embodiment 1) In the following, the first embodiment will be used to particularly claim 1, claim 2, claim 3, claim 4, claim 6, claim 7 of the present invention. The invention described in claim 9 will be described by taking a multilayer ceramic capacitor as an example.

【0025】本発明の実施の形態1について図面を参照
して説明する。図1は本発明の実施の形態1における積
層セラミックコンデンサの内部電極の構造を示す模式的
分解斜視図、図2は本発明の実施の形態1における積層
セラミックコンデンサの積層焼結体の斜視図、図3は本
発明の実施の形態1における積層セラミックコンデンサ
の斜視図である。
The first embodiment of the present invention will be described with reference to the drawings. 1 is a schematic exploded perspective view showing a structure of internal electrodes of a monolithic ceramic capacitor according to Embodiment 1 of the present invention, and FIG. 2 is a perspective view of a laminated sintered body of a monolithic ceramic capacitor according to Embodiment 1 of the present invention, FIG. 3 is a perspective view of the monolithic ceramic capacitor according to the first embodiment of the present invention.

【0026】図1〜図3において、10は積層焼結体、
11〜14は第1の外部電極、21〜24は第2の外部
電極、100は誘電体層、110〜140は第1の内部
電極、210〜240は第2の内部電極である。
1 to 3, 10 is a laminated sintered body,
11 to 14 are first external electrodes, 21 to 24 are second external electrodes, 100 is a dielectric layer, 110 to 140 are first internal electrodes, and 210 to 240 are second internal electrodes.

【0027】図3に示すように、本実施の形態1におけ
る積層セラミックコンデンサは、誘電体層と内部電極と
を交互に積層した積層焼結体10とこの積層焼結体10
の表面に設けた4対の対向する外部電極、つまり、第1
の外部電極11と第2の外部電極21、第1の外部電極
12と第2の外部電極22、第1の外部電極13と第2
の外部電極23および第1の外部電極14と第2の外部
電極24の4対を備えている。そして、図1〜図3に示
すように、内部電極は、誘電体層100を挟んで一方の
層に4つ並設した第1の内部電極110〜140と他方
の層に4つ並設した第2の内部電極210〜240とか
らなり、第1の内部電極110と第2の内部電極21
0、第1の内部電極120と第2の内部電極220、第
1の内部電極130と第2の内部電極230および第1
の内部電極140と第2の内部電極240とがそれぞれ
1個のコンデンサを構成し、1個の素体である積層焼結
体10内に4個のコンデンサを内蔵した4連形の積層セ
ラミックコンデンサである。
As shown in FIG. 3, the monolithic ceramic capacitor according to the first embodiment includes a monolithic sintered body 10 in which dielectric layers and internal electrodes are alternately laminated, and the monolithic sintered body 10.
Of the four pairs of opposing external electrodes provided on the surface of the
External electrode 11 and second external electrode 21, first external electrode 12 and second external electrode 22, first external electrode 13 and second external electrode
The external electrodes 23 and the first external electrode 14 and the second external electrode 24 are provided in four pairs. Then, as shown in FIGS. 1 to 3, four internal electrodes are arranged in parallel on one layer with the dielectric layer 100 sandwiched therebetween, and four internal electrodes are arranged on the other layer in parallel. The second internal electrodes 210 to 240, and the first internal electrode 110 and the second internal electrode 21.
0, the first internal electrode 120 and the second internal electrode 220, the first internal electrode 130 and the second internal electrode 230, and the first internal electrode 130.
Each of the internal electrodes 140 and the second internal electrodes 240 constitutes one capacitor, and four stacked monolithic ceramic capacitors in which four capacitors are incorporated in the multilayer sintered body 10 which is one element. Is.

【0028】そして、いずれの内部電極も、容量形成電
極とこの容量形成電極と一方の外部電極とを接続する引
出し電極と容量形成電極に非接続で他方の外部電極に接
続するダミー電極とを1単位としてそれぞれ同一層に有
した構成としている。具体的には、図1に示すように、
第1の内部電極110は、容量形成電極110aとこの
容量形成電極110aと第1の外部電極11とを接続す
る引出し電極110bと容量形成電極110aに非接続
で第2の外部電極21に接続するダミー電極110cと
を有し、第2の内部電極210は、容量形成電極210
aとこの容量形成電極210aと第2の外部電極21と
を接続する引出し電極210bと容量形成電極210a
に非接続で第1の外部電極11に接続するダミー電極2
10cとを有している。また、引出し電極およびダミー
電極の幅はほぼ同一でかつ容量形成電極に比して小とし
ている。例えば、引出し電極110bおよびダミー電極
110cの幅はほぼ同一でかつ容量形成電極110aに
比して小としている。
Each of the internal electrodes has a capacitance forming electrode, a lead electrode connecting the capacitance forming electrode and one external electrode, and a dummy electrode not connected to the capacitance forming electrode but connected to the other external electrode. Each unit has the same layer. Specifically, as shown in FIG.
The first internal electrode 110 is connected to the second external electrode 21 without being connected to the capacitance forming electrode 110a, the extraction electrode 110b connecting the capacitance forming electrode 110a and the first external electrode 11, and the capacitance forming electrode 110a. The second inner electrode 210 has a dummy electrode 110c, and the second inner electrode 210 is the capacitance forming electrode 210.
a, a lead-out electrode 210b for connecting the capacitance forming electrode 210a and the second external electrode 21, and a capacitance forming electrode 210a.
The dummy electrode 2 that is connected to the first external electrode 11 without being connected to
10c and. The widths of the extraction electrode and the dummy electrode are substantially the same and smaller than that of the capacitance forming electrode. For example, the lead electrode 110b and the dummy electrode 110c have substantially the same width and are smaller than the capacitance forming electrode 110a.

【0029】さらに、図1に示すように、第2の内部電
極210,220,230および240の形状は、第1
の内部電極140,130,120および110と略同
一形状を略180度回転させた形状としている。
Further, as shown in FIG. 1, the shape of the second internal electrodes 210, 220, 230 and 240 is the first.
The internal electrodes 140, 130, 120 and 110 have a shape substantially the same as that of the internal electrodes 140, 130, 120 and 110 rotated by 180 degrees.

【0030】以上のように構成することにより、本実施
の形態1における積層セラミックコンデンサは、内部電
極が容量形成電極部に比べ引出し電極部の幅寸法を小さ
くして外部電極との接続部の寸法を小さくする必要があ
る形状である場合においても、所望の静電容量を得るた
めの内部電極の重なり面積の変更が最少1種類の導体層
パターンでできるので、容易に多種類の静電容量を得ら
れる積層セラミックコンデンサとなるとともに、従来に
比べて内部電極の重なり面積が大きくでき、かつ変更で
きる重なり面積の幅つまり静電容量の範囲が大きくでき
る積層セラミックコンデンサとなる。具体的には、本発
明の実施の形態1における積層セラミックコンデンサの
製造方法とともに説明する。
With the above-described structure, in the monolithic ceramic capacitor according to the first embodiment, the width of the extraction electrode portion of the internal electrode is smaller than that of the capacitance forming electrode portion, and the dimension of the connection portion with the external electrode is reduced. Even if the shape is required to be small, it is possible to change the overlapping area of the internal electrodes in order to obtain a desired capacitance with at least one type of conductor layer pattern, so that it is possible to easily obtain many types of capacitance. In addition to the obtained monolithic ceramic capacitor, the monolithic ceramic capacitor can have a larger overlapping area of the internal electrodes and a wider range of the overlapping area that can be changed, that is, a range of electrostatic capacitance, as compared with the related art. Specifically, description will be given together with the method for manufacturing a monolithic ceramic capacitor according to the first embodiment of the present invention.

【0031】以下に、本発明の実施の形態1における積
層セラミックコンデンサの製造方法について説明する。
図4は本発明の実施の形態1で用いた内部電極となる導
体層パターン群を形成するための印刷版のパターン図で
あり、容量形成電極となる矩形状パターン501とこれ
に接続する引出し電極およびダミー電極となる帯状パタ
ーン502とからなる導体層パターン500を縦横に多
数個配列した導体層パターン群である。また、図4に示
す導体層パターン500の配列は、焼成後にダミー電極
と容量形成電極の間隔が誘電体層1層当りの厚みの3倍
以上となるように、ダミー電極となる帯状パターン50
2と容量形成電極となる矩形状パターン501の間隔D
1は、後述するセラミック生シートの厚みの4倍とし
た。
The method of manufacturing the monolithic ceramic capacitor according to the first embodiment of the present invention will be described below.
FIG. 4 is a pattern diagram of a printing plate for forming a conductor layer pattern group used as the internal electrodes used in the first embodiment of the present invention. A rectangular pattern 501 serving as a capacitance forming electrode and a lead electrode connected to the rectangular pattern 501 are provided. And a conductor layer pattern group in which a large number of conductor layer patterns 500 each including a strip-shaped pattern 502 serving as a dummy electrode are arranged in a matrix. In addition, the arrangement of the conductor layer patterns 500 shown in FIG. 4 is a strip-shaped pattern 50 to be a dummy electrode so that the distance between the dummy electrode and the capacitance forming electrode after firing becomes three times or more the thickness per one dielectric layer.
2 and the space D between the rectangular pattern 501 serving as the capacitance forming electrode
1 was 4 times the thickness of the ceramic green sheet described later.

【0032】まず、チタン酸バリウムを主成分とするセ
ラミック粉末と有機バインダからなるセラミック生シー
トを作製し準備した。この時、セラミック生シートの厚
みは約15μmとした。
First, a ceramic green sheet composed of a ceramic powder containing barium titanate as a main component and an organic binder was prepared and prepared. At this time, the thickness of the green ceramic sheet was about 15 μm.

【0033】そして、支持板上に接着シートを介して上
記セラミック生シートを複数枚積層して下側の無効層を
形成した。続いて、図4に示したパターンの印刷板を用
いてスクリーン印刷法により、上記の無効層上にニッケ
ルを主成分とする金属ペーストで、下最外層の第1の内
部電極110〜140となる導体層を形成した。
Then, a plurality of the above-mentioned ceramic green sheets were laminated on the support plate via an adhesive sheet to form a lower ineffective layer. Then, a metal paste containing nickel as a main component is formed on the ineffective layer by a screen printing method using a printing plate having the pattern shown in FIG. 4 to form the first inner electrodes 110 to 140 of the lower outermost layer. A conductor layer was formed.

【0034】次に、上記の第1の内部電極110〜14
0となる導体層を形成した積層体を支持板とともに略1
80度回転させ、印刷版の位置合わせを行って、この積
層体の上にセラミック生シートを積層し、このセラミッ
ク生シート上に上記と同じ印刷版を用いてスクリーン印
刷法により、ニッケルを主成分とする金属ペーストで、
第2の内部電極210〜240となる導体層を形成し
た。
Next, the above-mentioned first internal electrodes 110-14
A laminated body on which a conductor layer having a thickness of 0 is formed is approximately 1 together with a supporting plate.
The printing plate is aligned by rotating it by 80 degrees, a ceramic green sheet is laminated on this laminate, and nickel is used as a main component on this ceramic green sheet by the screen printing method using the same printing plate as above. With the metal paste,
A conductor layer to be the second inner electrodes 210 to 240 was formed.

【0035】さらに、上記の第2の内部電極210〜2
40となる導体層を形成した積層体を支持板とともに略
180度回転させ、印刷版の位置合わせを行って、この
積層体の上にセラミック生シートを積層し、このセラミ
ック生シート上に上記と同じ印刷版を用いてスクリーン
印刷法により、ニッケルを主成分とする金属ペースト
で、第1の内部電極110〜140となる導体層を形成
した。
Furthermore, the above-mentioned second internal electrodes 210-2
The laminated body on which the conductor layer to be 40 is formed is rotated about 180 degrees together with the support plate, the printing plate is aligned, and the ceramic green sheet is laminated on the laminated body. Using the same printing plate, a conductor layer to be the first internal electrodes 110 to 140 was formed by a screen printing method using a metal paste containing nickel as a main component.

【0036】続いて、上記の第1の内部電極110〜1
40となる導体層を形成した積層体を支持板とともに略
180度回転させ、印刷版の位置合わせを行って、この
積層体の上にセラミック生シートを積層し、このセラミ
ック生シート上に上記と同じ印刷版を用いてスクリーン
印刷法により、ニッケルを主成分とする金属ペースト
で、第2の内部電極210〜240となる導体層を形成
した。
Subsequently, the above-mentioned first internal electrodes 110-1
The laminated body on which the conductor layer to be 40 is formed is rotated about 180 degrees together with the support plate, the printing plate is aligned, and the ceramic green sheet is laminated on the laminated body. Using the same printing plate, a conductor layer to be the second internal electrodes 210 to 240 was formed by a screen printing method using a metal paste containing nickel as a main component.

【0037】これら上記の第1の内部電極110〜14
0となる導体層の印刷、略180度回転、印刷版の位置
合わせ、セラミック生シートの積層、第2の内部電極2
10〜240となる導体層の印刷、略180度回転、印
刷版の位置合わせ、セラミック生シートの積層を所望の
回数繰り返した。そして、この上に上記セラミック生シ
ートを複数枚積層して上側の無効層を形成し積層体ブロ
ックを得た。なお、上記において略180度回転、印刷
版の位置合わせは、支持板とともに積層体を略180度
回転させ行ったが、積層体と印刷版とを相対的に略18
0度回転させれば良く、積層体側を固定し印刷版を略1
80度回転させて行っても良い。
The above-mentioned first internal electrodes 110 to 14
Printing of 0 conductor layer, rotation of approximately 180 degrees, alignment of printing plates, lamination of ceramic green sheets, second internal electrode 2
Printing of the conductor layers of 10 to 240, rotation of about 180 degrees, alignment of the printing plate, and lamination of the ceramic green sheets were repeated a desired number of times. Then, a plurality of the above-mentioned ceramic green sheets were laminated on this to form an ineffective layer on the upper side to obtain a laminated body block. In the above, the rotation of about 180 degrees and the alignment of the printing plate were performed by rotating the laminated body together with the support plate by about 180 degrees.
It is only necessary to rotate it by 0 degrees, and fix the laminate side to make the printing plate approximately 1
It may be rotated by 80 degrees.

【0038】次に、上記積層体ブロックを図4に示した
切断位置510および520で所望の寸法に切断分離し
て、個片の生チップとした。この生チップを窒素ガス中
で加熱して脱バインダ処理した後、ニッケルが酸化され
ない窒素水素の混合ガス雰囲気中で1300℃まで加熱
して焼成し焼結体を得た。
Next, the laminate block was cut and separated into desired dimensions at cutting positions 510 and 520 shown in FIG. 4 to obtain individual raw chips. The raw chips were heated in nitrogen gas to remove the binder, and then heated to 1300 ° C. in a nitrogen-hydrogen mixed gas atmosphere in which nickel was not oxidized, and fired to obtain a sintered body.

【0039】次に、上記焼結体を面取りして焼結体の表
面に内部電極を完全に露出させ図2の積層焼結体10を
得た。続いて、積層焼結体10の両端面に銅を主成分と
する電極ペーストを塗布し、800℃の窒素雰囲気中で
焼付けし、この上にニッケルめっき、はんだめっきを施
して、第1の外部電極11〜14および第2の外部電極
21〜24を形成し、図3に示した本実施の形態1にお
ける積層セラミックコンデンサを作製した。
Next, the sintered body was chamfered to completely expose the internal electrodes on the surface of the sintered body to obtain a laminated sintered body 10 shown in FIG. Subsequently, an electrode paste containing copper as a main component is applied to both end faces of the laminated sintered body 10 and baked in a nitrogen atmosphere at 800 ° C., and nickel plating and solder plating are applied to the electrode paste to form a first external layer. The electrodes 11 to 14 and the second external electrodes 21 to 24 were formed, and the monolithic ceramic capacitor according to the first embodiment shown in FIG. 3 was produced.

【0040】作製した本実施の形態1における積層セラ
ミックコンデンサは、長手方向寸法が3.2mm、幅方
向寸法が1.6mm、厚み方向寸法が0.85mmであ
った。
The produced monolithic ceramic capacitor according to the first embodiment had a lengthwise dimension of 3.2 mm, a widthwise dimension of 1.6 mm, and a thicknesswise dimension of 0.85 mm.

【0041】次に、本実施の形態1における積層セラミ
ックコンデンサおよびその製造方法が、図4に示した導
体層パターン群を形成するための印刷版一つで、内部電
極の重なり面積の変更ができ容易に多種類の静電容量を
得られる積層セラミックコンデンサとなることについ
て、図4〜図6を用いて詳しく説明する。
Next, in the monolithic ceramic capacitor and the manufacturing method thereof according to the first embodiment, one printing plate for forming the conductor layer pattern group shown in FIG. 4 can change the overlapping area of the internal electrodes. It will be described in detail with reference to FIGS. 4 to 6 that the multilayer ceramic capacitor can easily obtain various kinds of capacitances.

【0042】図5は本発明の実施の形態1における積層
セラミックコンデンサの内部電極の重なり状態の1例を
示す平面透視図であり、図6は本発明の実施の形態1に
おける積層セラミックコンデンサの内部電極の重なり状
態の他の例を示す平面透視図である。なお、説明をわか
りやすくするために、図5および図6においては第1の
内部電極と第2の内部電極とをそれぞれ1層のみを図示
している。
FIG. 5 is a plan perspective view showing an example of the overlapping state of the internal electrodes of the monolithic ceramic capacitor according to Embodiment 1 of the present invention, and FIG. 6 is the interior of the monolithic ceramic capacitor according to Embodiment 1 of the present invention. It is a plane perspective view which shows the other example of the overlapping state of an electrode. Note that, in order to make the description easy to understand, only one layer of each of the first internal electrode and the second internal electrode is shown in FIGS. 5 and 6.

【0043】まず、内部電極の重なり状態の1例とし
て、図5には重なり面積が最大で得られる静電容量が最
大の場合を示した。図5に示すように、第2の内部電極
210〜240の形状は、第1の内部電極110〜14
0と同一形状を略180度回転させた形状であり、ま
た、第1の内部電極の容量形成電極と第2の内部電極の
容量形成電極との重なり面積、例えば第1の内部電極1
10の容量形成電極110aと第2の内部電極210の
容量形成電極210aとの重なり面積が最大となるよう
位置合わせしている。
First, as an example of the overlapped state of the internal electrodes, FIG. 5 shows the case where the overlapped area is maximum and the obtained electrostatic capacitance is maximum. As shown in FIG. 5, the shapes of the second internal electrodes 210 to 240 are the same as those of the first internal electrodes 110 to 14.
0 is a shape obtained by rotating the same shape as that of 0 by about 180 degrees, and the overlapping area of the capacitance forming electrode of the first internal electrode and the capacitance forming electrode of the second internal electrode, for example, the first internal electrode 1
The capacitance forming electrodes 110a of 10 and the capacitance forming electrodes 210a of the second internal electrodes 210 are aligned so that the overlapping area is maximized.

【0044】この容量形成電極の重なり面積を変更し、
得られる静電容量を変えるためには、第2の内部電極2
10〜240となる導体層の印刷時に、第1の内部電極
110〜140に対して略180度回転させるととも
に、図4の縦方向にずらして位置合わせして形成すれば
良い。例えば、導体層の印刷時に、マーク530とマー
ク550とを位置合わせし、マーク540とマーク56
0とを位置合わせする時、マーク530の531とマー
ク550の551とを位置合わせし、マーク540の5
41とマーク560の561とを位置合わせすれば、容
量形成電極の重なり面積は最大となり、マーク530の
531とマーク550の555とを位置合わせし、マー
ク540の541とマーク560の565とを位置合わ
せすれば、容量形成電極の重なり面積は最小となる。
By changing the overlapping area of the capacitance forming electrodes,
In order to change the obtained capacitance, the second internal electrode 2
When printing the conductor layers to be 10 to 240, they may be formed by rotating the first inner electrodes 110 to 140 by approximately 180 degrees and aligning them by shifting them in the vertical direction of FIG. For example, when printing the conductor layer, the marks 530 and 550 are aligned with each other, and the marks 540 and 56 are aligned.
When 0 is aligned, 531 of the mark 530 and 551 of the mark 550 are aligned, and 5 of the mark 540 is aligned.
When 41 and 561 of the mark 560 are aligned, the overlapping area of the capacitance forming electrode is maximized, the 531 of the mark 530 and the 555 of the mark 550 are aligned, and the 541 of the mark 540 and the 565 of the mark 560 are aligned. If combined, the overlapping area of the capacitance forming electrodes is minimized.

【0045】そして、例えば図6に示すように、第1の
内部電極110の容量形成電極110aと第2の内部電
極210の容量形成電極210aとの重なり面積を小さ
くすることができ、静電容量の小さな積層セラミックコ
ンデンサとなる。
Then, for example, as shown in FIG. 6, the overlapping area of the capacitance forming electrode 110a of the first internal electrode 110 and the capacitance forming electrode 210a of the second internal electrode 210 can be reduced, and the electrostatic capacitance can be reduced. It becomes a small monolithic ceramic capacitor.

【0046】次に、本発明の実施の形態1における積層
セラミックコンデンサが、ダミー電極と容量形成電極の
間隔を誘電体層1層当りの厚みの3倍以上とすることに
より、積層ずれ切断ずれ等により外部電極と対向する内
部電極との間隔が誘電体層1層当りの厚みの3倍以下に
近接した場合、これを容量測定により選別除去すること
ができ、したがって、外部電極と対向する内部電極との
間で絶縁破壊する危険性の高い製品をあらかじめ除去で
き信頼性の高い積層セラミックコンデンサとなるという
効果について説明する。なお、外部電極と対向する内部
電極との間隔が誘電体層1層当りの厚みの3倍以下に近
接した製品が、外部電極と対向する内部電極との間で絶
縁破壊する危険性が高いとしたのは、種々検討した結果
であり、内部電極の層間に比較して内部電極が同一層内
で絶縁破壊し易いためである。
Next, in the monolithic ceramic capacitor according to the first embodiment of the present invention, the distance between the dummy electrode and the capacitance forming electrode is set to be three times or more the thickness per one dielectric layer, whereby the lamination deviation and cutting deviation, etc. When the distance between the external electrode and the opposing internal electrode is close to 3 times or less of the thickness per one dielectric layer, it can be selectively removed by capacitance measurement. Therefore, the internal electrode facing the external electrode can be removed. The effect that a product having a high risk of dielectric breakdown between and can be removed in advance to form a highly reliable multilayer ceramic capacitor will be described. It should be noted that there is a high risk that a product in which the distance between the external electrode and the facing internal electrode is close to 3 times or less the thickness of one dielectric layer is dielectric breakdown between the external electrode and the facing internal electrode. This is because the results of various studies have been made, because the internal electrodes are more likely to cause dielectric breakdown in the same layer than between the layers of the internal electrodes.

【0047】図7は、図4の所望の切断位置510で切
断された場合の積層セラミックコンデンサの断面図であ
り、図8は、切断ずれにより図4の所望外の切断位置5
11で切断された場合の積層セラミックコンデンサの断
面図である。なお、説明をわかりやすくするために、図
7および図8においては第1の内部電極と第2の内部電
極とをそれぞれ1層のみを図示している。
FIG. 7 is a cross-sectional view of the monolithic ceramic capacitor when it is cut at the desired cutting position 510 in FIG. 4, and FIG. 8 is an undesired cutting position 5 in FIG.
FIG. 11 is a cross-sectional view of the monolithic ceramic capacitor when cut at 11. In order to make the description easy to understand, only one layer of each of the first internal electrode and the second internal electrode is shown in FIGS. 7 and 8.

【0048】図7に示すように、所望の切断位置510
で切断され作製された積層セラミックコンデンサは、第
1の内部電極110は、容量形成電極110aとこの容
量形成電極110aと第1の外部電極11とを接続する
引出し電極110bと容量形成電極110aに非接続で
第2の外部電極21に接続するダミー電極110cとを
有し、第2の内部電極210は、容量形成電極210a
とこの容量形成電極210aと第2の外部電極21とを
接続する引出し電極210bと容量形成電極210aに
非接続で第1の外部電極11に接続するダミー電極21
0cとを有した構成となっている。そして、この積層セ
ラミックコンデンサの容量は、第1の内部電極110の
容量形成電極110aと第2の内部電極210の容量形
成電極210aとの重なり部分で形成される静電容量C
1となる。
As shown in FIG. 7, the desired cutting position 510
In the monolithic ceramic capacitor manufactured by cutting in step 1, the first internal electrode 110 is not connected to the capacitance forming electrode 110a, the extraction electrode 110b connecting the capacitance forming electrode 110a and the first outer electrode 11, and the capacitance forming electrode 110a. A dummy electrode 110c connected to the second external electrode 21 by connection, and the second internal electrode 210 is the capacitance forming electrode 210a.
And a dummy electrode 21 that is connected to the first external electrode 11 without being connected to the lead electrode 210b that connects the capacitance forming electrode 210a and the second external electrode 21 and the capacitance forming electrode 210a.
And 0c. The capacitance of the monolithic ceramic capacitor is the capacitance C formed at the overlapping portion of the capacitance forming electrode 110a of the first internal electrode 110 and the capacitance forming electrode 210a of the second internal electrode 210.
It becomes 1.

【0049】しかしながら、図8に示すように、所望外
の切断位置511で切断され作製された積層セラミック
コンデンサは、第1の内部電極110は、容量形成電極
110a、引出し電極110bおよびダミー電極110
cとなるべき電極のいずれも、第1の外部電極11、第
2の外部電極21のいずれにも接続せずに誘電体層1層
当りの厚みの3倍以下の極めて近接した状態になり、第
2の内部電極210は、容量形成電極210aが第2の
外部電極21に接続し、引出し電極210bおよびダミ
ー電極210cとなるべき電極と接続した容量形成電極
210aの一部が第1の外部電極11に接続した構成と
なっている。そして、この積層セラミックコンデンサの
容量は、第1の内部電極110の容量形成電極110a
と第2の内部電極210の容量形成電極210aとの重
なり部分で形成される静電容量C1と、第1の内部電極
110の引出し電極110bおよびダミー電極110c
となるべき電極と第2の内部電極210の引出し電極2
10bおよびダミー電極210cとなるべき電極との重
なり部分で形成される静電容量C2とが直列接続された
容量となるので、この静電容量は、(C1×C2)/
(C1+C2)となり、C1に比して極めて小さな静電
容量となる。
However, as shown in FIG. 8, in the monolithic ceramic capacitor manufactured by cutting at an undesired cutting position 511, the first internal electrode 110 includes the capacitance forming electrode 110a, the extraction electrode 110b, and the dummy electrode 110.
None of the electrodes that should be c are connected to either the first external electrode 11 or the second external electrode 21 and are in a state of being extremely close to three times or less the thickness per one dielectric layer, In the second internal electrode 210, the capacitance forming electrode 210a is connected to the second external electrode 21, and a part of the capacitance forming electrode 210a connected to the lead electrode 210b and the electrode to be the dummy electrode 210c is the first external electrode. It is configured to be connected to 11. The capacitance of the monolithic ceramic capacitor is the capacitance forming electrode 110a of the first internal electrode 110.
And the capacitance C1 formed at the overlapping portion of the capacitance forming electrode 210a of the second internal electrode 210, the extraction electrode 110b of the first internal electrode 110, and the dummy electrode 110c.
Electrode to be used as the extraction electrode 2 of the second internal electrode 210
10b and the capacitance C2 formed in the overlapping portion of the electrode to be the dummy electrode 210c are connected in series, and this capacitance is (C1 × C2) /
(C1 + C2), which is an extremely small electrostatic capacitance as compared with C1.

【0050】したがって、静電容量を測定することによ
り、図8に示したような積層ずれ切断ずれ等により外部
電極と対向する内部電極との間隔が極めて近接した不良
品を選別除去することができ、外部電極と対向する内部
電極との間で絶縁破壊する危険性の高い製品をあらかじ
め除去でき信頼性の高い積層セラミックコンデンサが得
られる。
Therefore, by measuring the electrostatic capacitance, it is possible to selectively remove defective products in which the distance between the external electrode and the facing internal electrode is extremely close due to the stacking deviation, cutting deviation, etc. as shown in FIG. , A product with a high risk of dielectric breakdown between the external electrode and the opposing internal electrode can be removed in advance, and a highly reliable multilayer ceramic capacitor can be obtained.

【0051】(実施の形態2)以下、実施の形態2を用
いて、本発明の特に請求項5および請求項8に記載の発
明について積層セラミックコンデンサを例に説明する。
(Embodiment 2) Hereinafter, with reference to Embodiment 2, the present invention, particularly the inventions described in claims 5 and 8, will be described by taking a multilayer ceramic capacitor as an example.

【0052】以下、本発明の実施の形態2について図面
を参照して説明する。
The second embodiment of the present invention will be described below with reference to the drawings.

【0053】図9は本発明の実施の形態2における積層
セラミックコンデンサの内部電極の重なり状態の1例を
示す平面透視図であり、図10は本発明の実施の形態2
における積層セラミックコンデンサの内部電極の重なり
状態の他の例を示す平面透視図である。なお、説明をわ
かりやすくするために、図9および図10においては第
1の内部電極と第2の内部電極とをそれぞれ1層のみを
図示している。
FIG. 9 is a plan perspective view showing an example of the overlapping state of the internal electrodes of the laminated ceramic capacitor according to the second embodiment of the present invention, and FIG. 10 is the second embodiment of the present invention.
6 is a plan perspective view showing another example of the overlapping state of the internal electrodes of the monolithic ceramic capacitor in FIG. Note that, in order to make the description easy to understand, only one layer of each of the first internal electrode and the second internal electrode is shown in FIGS. 9 and 10.

【0054】図9および図10において、15は積層焼
結体、16〜19は第1の外部電極、26〜29は第2
の外部電極、160〜190は第1の内部電極、260
〜290は第2の内部電極である。
In FIGS. 9 and 10, 15 is a laminated sintered body, 16 to 19 are first external electrodes, and 26 to 29 are second.
External electrodes, 160 to 190 are first internal electrodes, 260
˜290 are second internal electrodes.

【0055】本実施の形態2における積層セラミックコ
ンデンサが上記実施の形態1と特に異なる点は、第1の
内部電極160〜190および第2の内部電極260〜
290の形状であり、図9および図10に示すように、
本実施の形態2における積層セラミックコンデンサは、
同一層に複数並設した内部電極の容量形成電極のピッチ
P2が複数対の外部電極のピッチP1と異なり、内部電
極の容量形成電極のピッチP2を外部電極のピッチP1
に比して小とした構成としている。
The monolithic ceramic capacitor according to the second embodiment is particularly different from the above-described first embodiment in that first internal electrodes 160 to 190 and second internal electrodes 260 to 260 are included.
290, and as shown in FIGS. 9 and 10,
The multilayer ceramic capacitor according to the second embodiment is
The pitch P2 of the capacitance forming electrodes of the internal electrodes arranged in parallel in the same layer is different from the pitch P1 of the plurality of pairs of external electrodes, and the pitch P2 of the capacitance forming electrodes of the internal electrodes is set to the pitch P1 of the external electrodes.
It has a smaller size than the above.

【0056】これにより、上記実施の形態1における図
5と本実施の形態2における図9とを比較すれば明らか
なように、本実施の形態2における積層セラミックコン
デンサは、容量形成電極の配置の自由度が増し、同一層
の容量形成電極の間隔が小さくできるので、外形寸法、
外部電極のピッチおよび外形と容量形成電極との間隔を
変えることなく、容量形成電極の面積が大きくでき小型
大容量化が可能な多連形の積層セラミックコンデンサと
なる。
Thus, as is clear from comparison between FIG. 5 in the first embodiment and FIG. 9 in the second embodiment, the laminated ceramic capacitor in the second embodiment has the arrangement of the capacitance forming electrodes. Since the degree of freedom is increased and the space between the capacitance forming electrodes in the same layer can be reduced, the external dimensions,
A multi-layer type multilayer ceramic capacitor in which the area of the capacitance forming electrode can be increased and the size and size of the capacitor can be increased without changing the pitch of the external electrodes and the interval between the capacitance forming electrode.

【0057】なお、図9および図10に示すように、本
実施の形態2における積層セラミックコンデンサが、誘
電体層と内部電極とを交互に積層した積層焼結体15と
この積層焼結体15の表面に設けた4対の対向する外部
電極16〜19および26〜29を備えている点、そし
て、内部電極は誘電体層を挟んで一方に4つ並設した第
1の内部電極160〜190と他方に4つ並設した第2
の内部電極260〜290とからなり、1個の素体であ
る積層焼結体15内に4個のコンデンサを内蔵した4連
形の積層セラミックコンデンサである点は、上記実施の
形態1と同様である。
As shown in FIGS. 9 and 10, the laminated ceramic capacitor according to the second embodiment includes a laminated sintered body 15 in which dielectric layers and internal electrodes are alternately laminated, and this laminated sintered body 15. Of the four internal electrodes 16 to 19 and 26 to 29 facing each other provided on the surface of the first internal electrode 160- 190 and the second one with four in parallel
Similar to the above-described first embodiment in that it is a quadruple-type monolithic ceramic capacitor which is composed of the internal electrodes 260 to 290 of FIG. Is.

【0058】また、いずれの内部電極も、容量形成電極
とこの容量形成電極と一方の外部電極とを接続する引出
し電極と容量形成電極に非接続で他方の外部電極に接続
するダミー電極とを1単位としてそれぞれ同一層に有
し、引出し電極およびダミー電極の幅はほぼ同一でかつ
容量形成電極に比して小としている点、さらに、第2の
内部電極260〜290の形状は第1の内部電極160
〜190と略同一形状を略180度回転させた形状とし
ている点は、上記実施の形態1と同様である。
In each internal electrode, a capacitance forming electrode, a lead electrode connecting the capacitance forming electrode and one external electrode, and a dummy electrode not connected to the capacitance forming electrode but connected to the other external electrode are connected to each other. Units are provided in the same layer, and the widths of the extraction electrode and the dummy electrode are substantially the same and smaller than that of the capacitance forming electrode. Furthermore, the shapes of the second internal electrodes 260 to 290 are the same as those of the first internal electrode. Electrode 160
Like 190 to 190, the same shape as that of 190 is rotated by 180 degrees, which is the same as the first embodiment.

【0059】したがって、本実施の形態2における積層
セラミックコンデンサも上記実施の形態1と同様の効果
が得られる。
Therefore, the monolithic ceramic capacitor according to the second embodiment also has the same effect as that of the first embodiment.

【0060】以下に、本発明の実施の形態2における積
層セラミックコンデンサの製造方法について説明する。
The method of manufacturing the laminated ceramic capacitor according to the second embodiment of the present invention will be described below.

【0061】図11は本発明の実施の形態2で用いた第
1の内部電極となる導体層パターン群を形成するための
印刷版のパターン図であり、容量形成電極となる矩形状
パターン601とこれに接続する引出し電極およびダミ
ー電極となる帯状パターン602とからなる導体層パタ
ーン600を縦横に多数個配列した導体層パターン群で
ある。また、上記実施の形態1と同様に、導体層パター
ン600の配列は、焼成後にダミー電極と容量形成電極
の間隔が誘電体層1層当りの厚みの3倍以上となるよう
に、ダミー電極となる帯状パターン602と容量形成電
極となる矩形状パターン601の間隔は、セラミック生
シートの厚みの4倍とした。
FIG. 11 is a pattern diagram of a printing plate for forming a conductor layer pattern group which becomes the first internal electrodes used in the second embodiment of the present invention, and a rectangular pattern 601 which becomes the capacitance forming electrodes. This is a conductor layer pattern group in which a large number of conductor layer patterns 600 each including a lead-out electrode connected to this and a strip-shaped pattern 602 serving as a dummy electrode are arranged vertically and horizontally. Further, as in the first embodiment, the conductor layer pattern 600 is arranged with dummy electrodes such that the distance between the dummy electrode and the capacitance forming electrode after firing is three times or more the thickness per dielectric layer. The interval between the strip-shaped pattern 602 and the rectangular pattern 601 serving as the capacitance forming electrode was set to 4 times the thickness of the ceramic green sheet.

【0062】そして、図12は本発明の実施の形態2で
用いた第2の内部電極となる導体層パターン群を形成す
るための印刷版のパターン図であり、図11の第1の内
部電極となる導体層パターン群を形成するための印刷版
のパターン図を180度回転させたパターンである。
FIG. 12 is a pattern diagram of a printing plate for forming a conductor layer pattern group used as the second internal electrode in the second embodiment of the present invention. The first internal electrode of FIG. It is a pattern obtained by rotating a pattern diagram of a printing plate for forming a conductor layer pattern group to be 180 degrees.

【0063】本実施の形態2における積層セラミックコ
ンデンサの製造方法が上記実施の形態1と特に異なる点
は、導体層パターン群を形成するために、図11および
図12に示した二つの印刷版を用いて内部電極となる導
体層を形成して積層体ブロックを作製する点であり、他
は上記実施の形態1と同様であるので詳細な説明は省略
する。
The manufacturing method of the laminated ceramic capacitor according to the second embodiment is particularly different from that of the above-mentioned first embodiment in that the two printing plates shown in FIGS. 11 and 12 are used to form the conductor layer pattern group. The other point is that the laminated body block is manufactured by forming a conductor layer to be an internal electrode, and the other details are the same as those in the above-described first embodiment, and therefore detailed description thereof is omitted.

【0064】まず、図11に示したパターンの印刷版を
取り付けたスクリーン印刷機と、図12に示したパター
ンの印刷版を取り付けたスクリーン印刷機の2台のスク
リーン印刷機を準備した。
First, two screen printing machines, a screen printing machine having a pattern printing plate shown in FIG. 11 and a screen printing machine having a pattern printing plate shown in FIG. 12, were prepared.

【0065】次に、支持板上に接着シートを介して上記
セラミック生シートを複数枚積層して下側の無効層を形
成した。続いて、図11に示したパターンの印刷版を用
いてスクリーン印刷法により、上記の無効層上にニッケ
ルを主成分とする金属ペーストで、下最外層の第1の内
部電極160〜190となる導体層を形成した。
Next, a plurality of the above-mentioned ceramic green sheets were laminated on the support plate via an adhesive sheet to form a lower ineffective layer. Then, a metal paste containing nickel as a main component is formed on the ineffective layer to form the first inner electrodes 160 to 190 of the lower outermost layer by a screen printing method using the printing plate having the pattern shown in FIG. A conductor layer was formed.

【0066】次に、この積層体の上に、図11の位置合
わせマーク630〜660と図12の位置合わせマーク
730〜760とを、マーク630とマーク730、マ
ーク640とマーク740、マーク650とマーク75
0、マーク660とマーク760とをそれぞれ位置合わ
せしてセラミック生シートを積層し、このセラミック生
シート上に図12に示したパターンの印刷版を用いてス
クリーン印刷法により、ニッケルを主成分とする金属ペ
ーストで、第2の内部電極260〜290となる導体層
を形成した。
Next, the alignment marks 630 to 660 shown in FIG. 11 and the alignment marks 730 to 760 shown in FIG. 12 are provided on the laminated body, and the marks 630 and 730, the marks 640 and 740, and the mark 650. Mark 75
No. 0, the mark 660 and the mark 760 are respectively aligned and a ceramic green sheet is laminated, and nickel is a main component by a screen printing method using a printing plate having the pattern shown in FIG. 12 on the ceramic green sheet. A conductor layer to be the second internal electrodes 260 to 290 was formed with a metal paste.

【0067】さらに、この積層体の上に、図11の印刷
版の位置合わせをして、セラミック生シートを積層し、
このセラミック生シート上に図11に示したパターンの
印刷版を用いてスクリーン印刷法により、ニッケルを主
成分とする金属ペーストで、第1の内部電極160〜1
90となる導体層を形成した。
Further, the printing plate shown in FIG. 11 is aligned on this laminated body, and a ceramic green sheet is laminated thereon,
The first internal electrodes 160 to 1 are formed on the ceramic green sheet by a screen printing method using a printing plate having the pattern shown in FIG.
A conductor layer of 90 was formed.

【0068】続いて、この積層体の上に、図12の印刷
版の位置合わせをして、セラミック生シートを積層し、
このセラミック生シート上に図12に示したパターンの
印刷版を用いてスクリーン印刷法により、ニッケルを主
成分とする金属ペーストで、第2の内部電極260〜2
90となる導体層を形成した。
Subsequently, the printing plate shown in FIG. 12 is aligned on this laminated body, and a ceramic green sheet is laminated thereon,
The second internal electrodes 260 to 2 are formed on the ceramic green sheet by a screen printing method using a printing plate having the pattern shown in FIG. 12 with a metal paste containing nickel as a main component.
A conductor layer of 90 was formed.

【0069】これら上記の第1の内部電極160〜19
0となる導体層の印刷、印刷版の位置合わせ、セラミッ
ク生シートの積層、第2の内部電極260〜290とな
る導体層の印刷、印刷版の位置合わせ、セラミック生シ
ートの積層を所望の回数繰り返した。そして、この上に
上記セラミック生シートを複数枚積層して上側の無効層
を形成し積層体ブロックを得た。なお、セラミック生シ
ートの厚み、導体層の厚みおよび積層数は、上記実施の
形態1と同一とした。
The above-mentioned first internal electrodes 160 to 19
Printing of a conductor layer to be 0, alignment of a printing plate, lamination of a ceramic green sheet, printing of a conductor layer to be the second internal electrodes 260 to 290, alignment of a printing plate, lamination of a ceramic green sheet a desired number of times. I repeated. Then, a plurality of the above-mentioned ceramic green sheets were laminated on this to form an ineffective layer on the upper side to obtain a laminated body block. The thickness of the ceramic green sheet, the thickness of the conductor layer, and the number of laminated layers were the same as those in the first embodiment.

【0070】次に、上記積層体ブロックを切断分離し、
脱バインダ処理した後焼成し、面取りして積層焼結体1
5を得て、次に、第1の外部電極16〜19および第2
の外部電極26〜29を形成して本実施の形態2におけ
る積層セラミックコンデンサを作製した。
Then, the laminate block is cut and separated,
After binder removal treatment, firing, chamfering, and laminated sintered body 1
5 and then the first outer electrodes 16-19 and the second
The external electrodes 26 to 29 were formed to produce the monolithic ceramic capacitor according to the second embodiment.

【0071】作製した本実施の形態2における積層セラ
ミックコンデンサは、長手方向寸法が3.2mm、幅方
向寸法が1.6mm、厚み方向寸法が0.85mmで、
外形の形状、寸法ともに上記実施の形態1と同一とし
た。
The produced monolithic ceramic capacitor according to the second embodiment has a lengthwise dimension of 3.2 mm, a widthwise dimension of 1.6 mm, and a thicknesswise dimension of 0.85 mm.
The external shape and dimensions are the same as those in the first embodiment.

【0072】以下に、図11および図12に示したパタ
ーンの印刷版二つで、本実施の形態2における積層セラ
ミックコンデンサおよびその製造方法が、上記実施の形
態1と同様に内部電極の重なり面積の変更ができ容易に
多種類の静電容量を得られる積層セラミックコンデンサ
となることについて、図9および図10を用いて説明す
る。
The laminated ceramic capacitor and the manufacturing method thereof according to the second embodiment using the two printing plates having the patterns shown in FIGS. 11 and 12 have the same overlapping area of the internal electrodes as the first embodiment. It will be described with reference to FIG. 9 and FIG. 10 that the laminated ceramic capacitor can be changed to easily obtain various kinds of electrostatic capacitance.

【0073】まず、内部電極の重なり状態の1例とし
て、図9には重なり面積が最大で得られる静電容量が最
大の場合を示した。図9に示すように、第2の内部電極
260〜290の形状は、第1の内部電極160〜19
0と同一形状を180度回転させた形状であり、また、
第1の内部電極の容量形成電極と第2の内部電極の容量
形成電極との重なり面積、例えば第1の内部電極160
の容量形成電極160aと第2の内部電極260の容量
形成電極260aとの重なり面積が最大となるよう位置
合わせしている。
First, as an example of the overlapping state of the internal electrodes, FIG. 9 shows the case where the capacitance obtained when the overlapping area is maximum is maximum. As shown in FIG. 9, the shapes of the second internal electrodes 260 to 290 are the same as those of the first internal electrodes 160 to 19.
It is the same shape as 0 but rotated 180 degrees, and
The overlapping area of the capacitance forming electrode of the first internal electrode and the capacitance forming electrode of the second internal electrode, for example, the first internal electrode 160
The capacitance forming electrode 160a and the capacitance forming electrode 260a of the second internal electrode 260 are aligned so that the overlapping area is maximized.

【0074】この容量形成電極の重なり面積を変更し、
得られる静電容量を変えるためには、図12のパターン
の印刷版を用いた第2の内部電極260〜290となる
導体層の印刷時に、図11の位置合わせマーク630〜
660に対して図12の位置合わせマーク730〜76
0を縦方向にずらして位置合わせして形成すれば良く、
例えば図10に示すように、第1の内部電極160の容
量形成電極160aと第2の内部電極260の容量形成
電極260aとの重なり面積を小さくすることができ、
小さな静電容量の積層セラミックコンデンサとなる。
By changing the overlapping area of the capacitance forming electrodes,
In order to change the obtained capacitance, the alignment marks 630 to 630 in FIG. 11 are printed when the conductor layer to be the second internal electrodes 260 to 290 is printed using the printing plate having the pattern in FIG.
Alignment marks 730 to 76 of FIG.
It may be formed by shifting 0 in the vertical direction and aligning it.
For example, as shown in FIG. 10, the overlapping area of the capacitance forming electrode 160a of the first internal electrode 160 and the capacitance forming electrode 260a of the second internal electrode 260 can be reduced,
It becomes a multilayer ceramic capacitor with a small capacitance.

【0075】また、本発明の実施の形態2における積層
セラミックコンデンサが、ダミー電極と容量形成電極の
間隔を誘電体層1層当りの厚みの3倍以上とすることに
より、積層ずれ切断ずれ等により外部電極と対向する内
部電極との間隔が誘電体層1層当りの厚みの3倍以下に
近接した場合、これを容量測定により選別除去すること
ができ、したがって、外部電極と対向する内部電極との
間で絶縁破壊する危険性の高い製品をあらかじめ除去で
き信頼性の高い積層セラミックコンデンサとなるという
効果については、上記実施の形態1と同様であるので、
説明を省略する。
Further, in the laminated ceramic capacitor according to the second embodiment of the present invention, the distance between the dummy electrode and the capacitance forming electrode is set to be three times or more the thickness per one dielectric layer, so that the lamination deviation and the cutting deviation may occur. When the distance between the external electrode and the facing internal electrode is close to 3 times or less of the thickness per one dielectric layer, it can be selectively removed by capacitance measurement. Therefore, the internal electrode facing the external electrode can be removed. Since the product having a high risk of dielectric breakdown between them can be removed in advance and a highly reliable multilayer ceramic capacitor can be obtained, it is the same as that of the first embodiment.
The description is omitted.

【0076】なお、上記実施の形態1および実施の形態
2においては、積層体ブロックの作製方法として、セラ
ミック生シートの積層、導体層のスクリーン印刷形成を
順次行う方法について説明したが、これに限られるもの
ではなく、あらかじめ導体層の印刷形成したセラミック
生シートを積層する方法や、セラミック生シートおよび
導体層を転写積層して形成する方法など公知の種々の方
法により行うことができる。
In the above-described first and second embodiments, as a method of manufacturing the laminated block, a method of sequentially laminating the ceramic green sheets and screen-printing the conductor layers has been described, but the method is not limited to this. However, it can be performed by various known methods such as a method of laminating a ceramic green sheet on which a conductor layer is printed and formed in advance, or a method of transferring and laminating a ceramic green sheet and a conductor layer.

【0077】また、内部電極となる導体層の形成方法と
して、上記実施の形態1では図4に示したパターンの一
つの印刷版でこれを交互に相対的に略180度回転させ
導体層を形成し、上記実施の形態2では図11および図
12に示したパターンの二つの印刷版を交互に用いて導
体層を形成した方法を説明したが、印刷版を一つ用いる
か二つ用いるかは導体層のパターンによって限定される
ものではなく、積層体ブロックの作製工程における生産
性、品質等を考慮して選択すれば良い。
As a method of forming a conductor layer to be an internal electrode, in the first embodiment, one printing plate having the pattern shown in FIG. 4 is alternately and relatively rotated by approximately 180 degrees to form a conductor layer. In the second embodiment, the method of forming the conductor layer by alternately using the two printing plates having the patterns shown in FIGS. 11 and 12 has been described. It is not limited by the pattern of the conductor layer, and may be selected in consideration of productivity, quality, etc. in the manufacturing process of the laminated body block.

【0078】さらにまた、図4、図11および図12に
示したパターンの印刷版では、導体層パターンは、帯状
パターンがすべて同方向となるよう配列した例を示した
が、必ずしもこのように配列する必要はなく、第1の内
部電極となる導体層パターン群を略180度回転させた
時、第1の内部電極となる導体層パターン群の帯状パタ
ーンと第2の内部電極となる導体層パターン群の帯状パ
ターンとが、交互に形成されるように配置すれば良い。
Furthermore, in the printing plates of the patterns shown in FIGS. 4, 11 and 12, the conductor layer patterns are arranged such that the strip-shaped patterns are all in the same direction, but they are not necessarily arranged in this way. When the conductor layer pattern group serving as the first internal electrode is rotated by approximately 180 degrees, the strip-shaped pattern of the conductor layer pattern group serving as the first internal electrode and the conductor layer pattern serving as the second internal electrode are not necessary. The band-shaped patterns of the groups may be arranged alternately.

【0079】そして、上記実施の形態1および実施の形
態2においては、1個の積層焼結体内に4個のコンデン
サを内蔵した4連形の積層セラミックコンデンサについ
て説明したが、複数対の外部電極のピッチと複数の内部
電極の容量形成電極のピッチとが異なるという構成を除
いて、上記実施の形態1および実施の形態2で説明した
構成を採用することにより、単一素体内に1個のコンデ
ンサのみを内蔵する一般的な積層セラミックコンデンサ
においても同様の効果が得られる。
In Embodiments 1 and 2 described above, a quadruple type monolithic ceramic capacitor in which four capacitors are incorporated in one monolithic sintered body has been described, but a plurality of pairs of external electrodes are used. By adopting the configurations described in the above-described first and second embodiments, except for the configuration in which the pitch of P and the pitch of the capacitance forming electrodes of the plurality of internal electrodes are different, The same effect can be obtained in a general monolithic ceramic capacitor containing only a capacitor.

【0080】そしてまた、上記実施の形態1および実施
の形態2においては、積層セラミックコンデンサを例に
説明したが、積層バリスタ、積層サーミスタなどの積層
セラミック電子部品においても、同様に、所望の電気的
特性を得るための内部電極の重なり面積の変更が最少1
種類の導体層パターンででき、容易に多種類の電気的特
性の積層セラミック電子部品を得ることができる。
Further, in the above-described first and second embodiments, the monolithic ceramic capacitor has been described as an example, but similarly in a monolithic ceramic electronic component such as a monolithic varistor and a monolithic thermistor, a desired electrical property is obtained. Minimal change in overlapping area of internal electrodes to obtain characteristics 1
It is possible to use various types of conductor layer patterns, and it is possible to easily obtain a multilayer ceramic electronic component having various types of electrical characteristics.

【0081】[0081]

【発明の効果】以上のように本発明は、誘電体層と内部
電極とを交互に積層した積層焼結体とこの積層焼結体の
表面に設けた対向する第1の外部電極と第2の外部電極
とを備えた積層セラミック電子部品であって、前記内部
電極は、誘電体層を挟んで設けた第1の内部電極と第2
の内部電極とを備え、前記第1および第2の内部電極
は、それぞれ同一層に容量形成電極とこの容量形成電極
と一方の外部電極とを接続する引出し電極と前記容量形
成電極に非接続で他方の外部電極に接続するダミー電極
とを有し、前記引出し電極および前記ダミー電極の幅は
ほぼ同一でかつ前記容量形成電極に比して小であり、前
記第2の内部電極の形状は、前記第1の内部電極と略同
一形状を略180度回転させた形状である積層セラミッ
ク電子部品であり、内部電極が容量形成電極部に比べ引
出し電極部の幅寸法を小さくして外部電極との接続部の
寸法を小さくする必要がある形状である場合において
も、所望の静電容量を得るための内部電極の重なり面積
の変更が最少1種類の導体層パターンででき、容易に多
種類の静電容量の積層セラミック電子部品が得られると
ともに、従来に比べて内部電極の重なり面積が大きくで
き、かつ変更できる重なり面積の幅つまり静電容量の範
囲が大きくできるという効果を奏するものである。
INDUSTRIAL APPLICABILITY As described above, according to the present invention, a laminated sintered body in which dielectric layers and internal electrodes are alternately laminated, a first outer electrode and a second external electrode provided on the surface of the laminated sintered body and facing each other. A multilayer ceramic electronic component, the internal electrode comprising a first internal electrode and a second internal electrode sandwiching a dielectric layer.
Internal electrodes, and the first and second internal electrodes are not connected to the capacitance forming electrode and the lead electrode connecting the capacitance forming electrode and one external electrode in the same layer, respectively. A dummy electrode connected to the other external electrode, the extraction electrode and the dummy electrode have substantially the same width and are smaller than the capacitance forming electrode, and the shape of the second internal electrode is A multilayer ceramic electronic component having a shape substantially the same as the first internal electrode rotated by approximately 180 degrees, wherein the internal electrode has a width dimension of the extraction electrode portion smaller than that of the capacitance forming electrode portion, Even if the size of the connection part needs to be reduced, the overlapping area of the internal electrodes can be changed with a minimum of one type of conductor layer pattern to obtain the desired capacitance, and various types of static layers can be easily formed. Capacitance stacking With ceramic electronic component can be obtained, it can be increased overlapping area of the internal electrodes as compared with the conventional, and the range of the width, i.e. the capacitance of the overlapping area can be changed in which an effect that it greatly.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態1における積層セラミック
電子部品の内部電極の構造を示す模式的分解斜視図
FIG. 1 is a schematic exploded perspective view showing a structure of internal electrodes of a monolithic ceramic electronic component according to a first embodiment of the present invention.

【図2】同積層セラミックコンデンサの積層焼結体の斜
視図
FIG. 2 is a perspective view of a multilayer sintered body of the multilayer ceramic capacitor.

【図3】同積層セラミックコンデンサの斜視図FIG. 3 is a perspective view of the monolithic ceramic capacitor.

【図4】本発明の実施の形態1で用いた内部電極となる
導体層パターン群を形成するための印刷版のパターン図
FIG. 4 is a pattern diagram of a printing plate for forming a conductor layer pattern group used as the internal electrodes used in the first embodiment of the present invention.

【図5】本発明の実施の形態1における積層セラミック
コンデンサの内部電極の重なり状態の1例を示す平面透
視図
FIG. 5 is a plan perspective view showing an example of an overlapping state of internal electrodes of the monolithic ceramic capacitor according to the first embodiment of the present invention.

【図6】同他の例を示す平面透視図FIG. 6 is a perspective plan view showing the other example.

【図7】所望の切断位置で切断された場合の積層セラミ
ックコンデンサの断面図
FIG. 7 is a cross-sectional view of a monolithic ceramic capacitor when cut at a desired cutting position.

【図8】所望外の切断位置で切断された場合の積層セラ
ミックコンデンサの断面図
FIG. 8 is a cross-sectional view of a monolithic ceramic capacitor when cut at an undesired cutting position.

【図9】本発明の実施の形態2における積層セラミック
コンデンサの内部電極の重なり状態の1例を示す平面透
視図
FIG. 9 is a plan perspective view showing an example of an overlapping state of internal electrodes of a laminated ceramic capacitor according to a second embodiment of the present invention.

【図10】同他の例を示す平面透視図FIG. 10 is a perspective plan view showing the other example.

【図11】本発明の実施の形態2で用いた第1の内部電
極となる導体層パターン群を形成するための印刷版のパ
ターン図
FIG. 11 is a pattern diagram of a printing plate for forming a conductor layer pattern group used as the first internal electrodes used in Embodiment 2 of the present invention.

【図12】同第2の内部電極となる導体層パターン群を
形成するための印刷版のパターン図
FIG. 12 is a pattern diagram of a printing plate for forming a conductor layer pattern group serving as the second internal electrode.

【図13】従来の多連形の積層セラミックコンデンサの
内部電極の構造を示す模式的分解斜視図
FIG. 13 is a schematic exploded perspective view showing the structure of internal electrodes of a conventional multi-layered monolithic ceramic capacitor.

【符号の説明】[Explanation of symbols]

10,15 積層焼結体 11〜14、16〜19 第1の外部電極 21〜24、26〜29 第2の外部電極 100 誘電体層 110〜140、160〜190 第1の内部電極 110a,160a,210a,260a 容量形成電
極 110b,210b 引出し電極 110c,210c ダミー電極 210〜240、260〜290 第2の内部電極 500,600 導体層パターン 501,601 矩形状パターン 502,602 帯状パターン
10, 15 Laminated sintered bodies 11-14, 16-19 First external electrodes 21-24, 26-29 Second external electrode 100 Dielectric layers 110-140, 160-190 First internal electrodes 110a, 160a , 210a, 260a Capacitance forming electrodes 110b, 210b Lead-out electrodes 110c, 210c Dummy electrodes 210-240, 260-290 Second inner electrodes 500,600 Conductor layer patterns 501,601 Rectangular patterns 502,602 Strip patterns

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E082 AB03 BC40 CC03 EE04 EE11 EE35 FG06 FG26 FG54 GG10 JJ03 JJ23 LL01 LL02 LL03 MM19 MM24 MM36 PP09    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5E082 AB03 BC40 CC03 EE04 EE11                       EE35 FG06 FG26 FG54 GG10                       JJ03 JJ23 LL01 LL02 LL03                       MM19 MM24 MM36 PP09

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 誘電体層と内部電極とを交互に積層した
積層焼結体とこの積層焼結体の表面に設けた対向する第
1の外部電極と第2の外部電極とを備えた積層セラミッ
ク電子部品であって、前記内部電極は、誘電体層を挟ん
で設けた第1の内部電極と第2の内部電極とを備え、前
記第1および第2の内部電極は、それぞれ同一層に容量
形成電極とこの容量形成電極と一方の外部電極とを接続
する引出し電極と前記容量形成電極に非接続で他方の外
部電極に接続するダミー電極とを有し、前記引出し電極
および前記ダミー電極の幅はほぼ同一でかつ前記容量形
成電極に比して小であり、前記第2の内部電極の形状
は、前記第1の内部電極と略同一形状を略180度回転
させた形状である積層セラミック電子部品。
1. A laminated body comprising a laminated sintered body in which dielectric layers and internal electrodes are alternately laminated, and a first external electrode and a second external electrode facing each other provided on the surface of the laminated sintered body. In the ceramic electronic component, the internal electrode includes a first internal electrode and a second internal electrode provided with a dielectric layer sandwiched therebetween, and the first and second internal electrodes are formed in the same layer. A capacitance forming electrode, a lead-out electrode connecting the capacitance forming electrode and one external electrode, and a dummy electrode not connected to the capacitance forming electrode and connected to the other external electrode, and the lead-out electrode and the dummy electrode The width is substantially the same and smaller than that of the capacitance forming electrode, and the shape of the second internal electrode is a shape obtained by rotating the same shape as the first internal electrode by about 180 degrees. Electronic components.
【請求項2】 ダミー電極と容量形成電極の間隔は誘電
体層1層当りの厚みの3倍以上である請求項1に記載の
積層セラミック電子部品。
2. The monolithic ceramic electronic component according to claim 1, wherein the distance between the dummy electrode and the capacitance forming electrode is three times or more the thickness per one dielectric layer.
【請求項3】 誘電体層と内部電極とを交互に積層した
積層焼結体とこの積層焼結体の表面に設けた複数対の対
向する第1の外部電極と第2の外部電極とを備えた多連
形の積層セラミック電子部品であって、前記内部電極
は、誘電体層を挟んで設けた第1の内部電極と第2の内
部電極とを備え、前記第1および第2の内部電極は、そ
れぞれ同一層に容量形成電極とこの容量形成電極と一方
の外部電極とを接続する引出し電極と前記容量形成電極
に非接続で他方の外部電極に接続するダミー電極とを有
し、前記引出し電極および前記ダミー電極の幅はほぼ同
一でかつ前記容量形成電極に比して小であり、前記第2
の内部電極の形状は、前記第1の内部電極と略同一形状
を略180度回転させた形状であり、前記第1および第
2の内部電極はそれぞれ複数を同一層に並設した構成で
ある積層セラミック電子部品。
3. A laminated sintered body in which dielectric layers and internal electrodes are alternately laminated, and a plurality of pairs of opposing first external electrodes and second external electrodes provided on the surface of the laminated sintered body. In the multi-layered multilayer ceramic electronic component, the internal electrode includes a first internal electrode and a second internal electrode sandwiching a dielectric layer, and the first and second internal electrodes are provided. The electrodes each have a capacitance forming electrode in the same layer, a lead electrode connecting the capacitance forming electrode and one external electrode, and a dummy electrode not connected to the capacitance forming electrode and connected to the other external electrode, The width of the lead electrode and the width of the dummy electrode are substantially the same and smaller than that of the capacitance forming electrode.
The shape of the internal electrode is a shape obtained by rotating the substantially same shape as the first internal electrode by approximately 180 degrees, and a plurality of the first and second internal electrodes are arranged side by side in the same layer. Multilayer ceramic electronic components.
【請求項4】 ダミー電極と容量形成電極の間隔は誘電
体層1層当りの厚みの3倍以上である請求項3に記載の
積層セラミック電子部品。
4. The monolithic ceramic electronic component according to claim 3, wherein the distance between the dummy electrode and the capacitance forming electrode is three times or more the thickness per one dielectric layer.
【請求項5】 複数対の外部電極および同一層に複数並
設した内部電極は、その外部電極のピッチと前記内部電
極の容量形成電極のピッチとが異なる請求項3に記載の
積層セラミック電子部品。
5. The monolithic ceramic electronic component according to claim 3, wherein a plurality of pairs of outer electrodes and a plurality of inner electrodes arranged in parallel in the same layer have different pitches of the outer electrodes and pitches of the capacitance forming electrodes of the inner electrodes. .
【請求項6】 セラミック生シートと内部電極となる導
体層とを交互に積層して積層体ブロックを作製する第1
工程と、この積層体ブロックを個片に切断分離し焼成し
て積層焼結体を作製する第2工程と、この積層焼結体に
外部電極を形成する第3工程と、これを検査する第4工
程とを備え、前記第1工程において、前記内部電極とな
る導体層の形成は、容量形成電極となる矩形状パターン
とこれに接続する引出し電極およびダミー電極となる帯
状パターンとからなる導体層パターンを縦横に多数個配
列した導体層パターン群を用いて行う第1電極形成工程
と、前記導体層パターン群と略同一の導体層パターン群
を略180度回転させて行う第2電極形成工程とを、交
互に繰り返して行う積層セラミック電子部品の製造方
法。
6. A first block for producing a laminate block by alternately laminating a ceramic green sheet and a conductor layer to be an internal electrode.
A step, a second step of cutting and separating the laminate block into individual pieces, and firing to produce a laminate sintered body; a third step of forming external electrodes on the laminate sintered body; and a step of inspecting this. In the first step, the formation of the conductor layer serving as the internal electrode includes the formation of a rectangular pattern serving as a capacitance forming electrode and a strip pattern serving as a lead electrode and a dummy electrode connected thereto. A first electrode forming step performed by using a conductor layer pattern group in which a large number of patterns are arranged vertically and horizontally, and a second electrode forming step performed by rotating a conductor layer pattern group substantially the same as the conductor layer pattern group by about 180 degrees. A method for manufacturing a monolithic ceramic electronic component, which is alternately and repeatedly performed.
【請求項7】 第2電極形成工程において、第1電極形
成工程と同一の導体層パターン群を用いこれを略180
度回転させて内部電極となる導体層を形成する請求項6
に記載の積層セラミック電子部品の製造方法。
7. The second electrode forming step uses substantially the same conductor layer pattern group as in the first electrode forming step,
7. A conductor layer to be an internal electrode is formed by rotating the conductor layer by 6 degrees.
A method for manufacturing a monolithic ceramic electronic component according to.
【請求項8】 第2電極形成工程において、第1電極形
成工程の導体層パターン群と略同一形状を略180度回
転させた形状の導体層パターン群を用いて内部電極とな
る導体層を形成する請求項6に記載の積層セラミック電
子部品の製造方法。
8. In the second electrode forming step, a conductor layer to be an internal electrode is formed by using a conductor layer pattern group having a shape obtained by rotating the same shape as the conductor layer pattern group in the first electrode forming step by about 180 degrees. The method for manufacturing a monolithic ceramic electronic component according to claim 6.
【請求項9】 第4工程において、静電容量を測定して
外部電極と対向する内部電極との間隔が近接した不良品
を選別除去する請求項6に記載の積層セラミック電子部
品の製造方法。
9. The method of manufacturing a multilayer ceramic electronic component according to claim 6, wherein in the fourth step, the capacitance is measured to screen and remove defective products in which the distance between the external electrode and the facing internal electrode is close.
JP2002075745A 2002-03-19 2002-03-19 Multilayer ceramic electronic component and manufacturing method thereof Expired - Lifetime JP3985557B2 (en)

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