JP2010103175A - Method for manufacturing multilayer capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method, capable of easily obtaining a multilayer capacitor which is equipped with a blank including an electrostatic capacity portion and an ESR control portion, and of improving the manufacturing yield. <P>SOLUTION: Internal electrode patterns 30, 40 are formed so that the internal electrode patterns 30, 40 is arranged alternately in a predetermined direction and a direction perpendicular to the predetermined direction and portions 33, 43, corresponding to the lead-out portions of the internal electrodes in the internal electrode patterns 30, 40 continue over a cut schedule line C1. Internal electrode patterns 60, 70 are formed so that the internal electrode patterns 60, 70 are arranged alternately in a predetermined direction and a direction perpendicular to the predetermined direction; portions 63, 65 and 73, 75 corresponding to the lead-out portions of the internal electrodes of the internal electrode patterns 60, 70 continue over cut schedule line C1, C2; and third and fourth internal electrode patterns are alternately connected, in one direction that crosses a predetermined offset direction and a direction perpendicular to the predetermined direction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer capacitor including an element body including a capacitance section and an ESR control section.

  As a multilayer capacitor, a capacitor having a substantially rectangular parallelepiped element body in which a plurality of internal electrodes are stacked with a dielectric layer interposed therebetween is known (for example, see Patent Document 1). In the multilayer capacitor described in Patent Document 1, the element body includes an electrostatic capacity unit and an ESR (Equivalent Series Resistance) control unit.

  The capacitance part is drawn out to one side and connected to the first polarity, and the second internal part is drawn to one side facing the one side and connected to the second polarity. Are arranged alternately with at least one dielectric layer interposed therebetween. The ESR control unit includes a third internal electrode that is drawn to one side surface from which the first internal electrode is drawn and one side surface adjacent to the one side surface and is connected to the first polarity, A fourth internal electrode that is drawn to one side from which the second internal electrode is drawn and one side that is adjacent to the one side, except for the two sides from which the internal electrode is drawn, and is connected to the second polarity And is configured.

In the capacitance part, the first and second internal electrodes are connected only to the terminal conductor, and in the ESR control part, the third and fourth internal electrodes are connected to the terminal conductor and the external electrode, respectively. Therefore, in the multilayer capacitor described in Patent Document 1, since the terminal conductor in which the first and second internal electrodes are connected in parallel is connected in series to the external electrode, the internal electrode is connected to the external electrode as in the prior art. High ESR can be realized as compared with the case of parallel connection.
JP 2003-168621 A

  When the multilayer capacitor described in Patent Document 1 is manufactured, since the first to fourth internal electrodes are included, generally, the first internal electrode pattern corresponding to the first internal electrode is formed. A ceramic green sheet, a ceramic green sheet on which a second internal electrode pattern corresponding to the second internal electrode is formed, a ceramic green sheet on which a third internal electrode pattern corresponding to the third internal electrode is formed, and a first It is necessary to prepare a ceramic green sheet on which a fourth internal electrode pattern corresponding to the four internal electrodes is formed. These ceramic green sheets are laminated in a predetermined order to obtain a ceramic green sheet laminate. Thereafter, the obtained ceramic green sheet laminate is cut along a predetermined planned cutting line to obtain a laminate chip for each multilayer capacitor unit, and this laminate chip is fired to obtain an element body. Yes.

  However, in the manufacturing method described above, it is necessary to prepare four types of ceramic green sheets in which the corresponding internal electrode patterns are independently formed in addition to the ceramic green sheets in which the internal electrode patterns are not formed. However, the manufacturing cost increases. Further, in the above manufacturing method, if a deviation occurs when the ceramic green sheets are laminated or the ceramic green sheet laminate is cut, the lead portion of the internal electrode may not be exposed on the side surface of the element body. In this case, it is impossible to realize the function as a capacitor, and the obtained multilayer capacitor becomes a defective product, resulting in a decrease in manufacturing yield.

  The present invention provides a multilayer capacitor manufacturing method capable of easily obtaining a multilayer capacitor including an element body including a capacitance section and an ESR control section and improving the manufacturing yield of the multilayer capacitor. The purpose is to do.

  The present invention includes a substantially rectangular parallelepiped element body in which a plurality of internal electrodes are stacked with a dielectric layer interposed therebetween, and the element body is drawn to one side surface and connected to a first polarity. Capacitance portion in which internal electrodes and second internal electrodes that are drawn out to one side surface that faces one side surface and are connected to the second polarity are alternately arranged with at least one dielectric layer interposed therebetween A third internal electrode that is drawn to one side surface from which the first internal electrode is drawn out and one side surface adjacent to the one side surface and is connected to the first polarity; The second internal electrode excluding the two extracted side surfaces has one side surface from which the second internal electrode is extracted and one side surface adjacent to the one side surface, and has a fourth internal electrode connected to the second polarity. And an ESR control unit A first manufacturing method for a capacitance portion in which a first internal electrode pattern corresponding to a first internal electrode and a second internal electrode pattern corresponding to a second internal electrode are formed. A plurality of ceramic green sheets, and a third internal electrode pattern corresponding to the third internal electrode and a fourth internal electrode pattern corresponding to the fourth internal electrode are formed. Preparing a plurality of second ceramic green sheets, and a plurality of first and second ceramic green sheets, each of the first ceramic green sheets and the second ceramic green sheets having one internal electrode Laminating the pattern in a predetermined direction to obtain a ceramic green sheet laminate, and the ceramic green sheet laminate to a predetermined cutting line The step of obtaining a multilayer chip for each multilayer capacitor unit and the step of firing the multilayer chip to obtain an element body, and preparing the first ceramic green sheet, And the second internal electrode patterns are alternately arranged in a predetermined direction and a direction orthogonal to the predetermined direction, and lead portions of the first and second internal electrodes in the first and second internal electrode patterns In the step of forming the first and second internal electrode patterns and preparing the second ceramic green sheet so that the portion corresponding to the line continues across the predetermined cutting line, the third and fourth internals are prepared. The electrode patterns are alternately arranged in a predetermined offset direction and a direction orthogonal to the predetermined direction, and the third and fourth internal electrode patterns in the third and fourth internal electrode patterns are drawn. The third and fourth internal electrode patterns alternate in one direction in which a portion corresponding to the protruding portion is continuous across a predetermined cutting line and intersects a predetermined offset direction and a direction orthogonal to the predetermined direction. The third and fourth internal electrode patterns are formed so as to be connected to each other.

  In the multilayer capacitor manufacturing method according to the present invention, as the ceramic green sheet on which the internal electrode pattern is formed, the first ceramic green sheet for the electrostatic capacitance portion on which the first and second internal electrode patterns are formed; It is only necessary to prepare two types of ceramic green sheets for the ESR control unit on which the third and fourth internal electrode patterns are formed, so that the manufacturing process is simplified and the manufacturing cost is reduced. Can be achieved.

  In the present invention, in the first and second internal electrode patterns formed on the first ceramic green sheet, a portion corresponding to the lead portion is continuous across a predetermined scheduled cutting line. Also, in the third and fourth internal electrode patterns formed on the second ceramic green sheet, the portion corresponding to the lead-out portion continues across a predetermined scheduled cutting line. For this reason, even when a deviation occurs when laminating the ceramic green sheets or cutting the ceramic green sheet laminate, the obtained laminate chip has the first to fourth internal electrode patterns in the first to fourth internal electrode patterns. The portion corresponding to the lead portion of the internal electrode 4 is always exposed on the side surface (cut surface). Therefore, according to the present invention, it is possible to suppress the generation of a defective product in which the first to fourth internal electrodes are not drawn out to the side surface of the element body, The provided multilayer capacitor can be manufactured with high yield.

  Preferably, the predetermined cutting line includes a first cutting line extending in a direction parallel to the predetermined offset direction, and a second cutting line orthogonal to the first cutting line, The portions corresponding to the lead portions of the third and fourth internal electrodes have different widths in a region straddling the first planned cutting line and a region straddling the second planned cutting line. In this case, a multilayer capacitor in which the width of the lead portion of the third internal electrode and the width of the lead portion of the fourth internal electrode are different can be easily obtained.

  Preferably, in the step of preparing the first ceramic green sheet, an electrode pattern for the dummy electrode is formed so as to have a distance from the first and second internal electrode patterns and straddle a predetermined cutting line, In the second step of preparing the ceramic green sheet, the electrode pattern for the dummy electrode is formed so as to have a gap from the third and fourth internal electrode patterns and to cross a predetermined planned cutting line. In this case, in the obtained laminated chip, the electrode pattern for the dummy electrode is necessarily exposed on the side surface (cut surface), and the element body in which the dummy electrode is also drawn out to the side surface can be obtained. The dummy electrode is for increasing the contact area with the outer conductor and improving the connection strength between the element body and the outer conductor when the outer conductor is formed on the element body. In addition, by forming the electrode pattern for the dummy electrode on the first and second ceramic green sheets, the electrode pattern functions as a step absorption layer, resulting from the thickness of the first to fourth internal electrode patterns. Generation | occurrence | production of the level | step difference which arises can be suppressed and a deformation | transformation of a laminated body chip | tip (element body) can be prevented.

  According to the present invention, a multilayer capacitor manufacturing method capable of easily obtaining a multilayer capacitor including an element body including an electrostatic capacitance section and an ESR control section and improving the manufacturing yield of the multilayer capacitor. Can be provided.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

(First embodiment)
First, the configuration of the multilayer capacitor 1 manufactured by the multilayer capacitor manufacturing method according to the first embodiment will be described with reference to FIGS. FIG. 1 is a perspective view showing the multilayer capacitor in accordance with the first embodiment. 2 is a diagram showing a layer configuration of the multilayer capacitor shown in FIG. 1, and FIG. 3 is a sectional view taken along line III-III in FIG.

  As shown in FIGS. 1 to 3, the multilayer capacitor 1 includes a substantially rectangular parallelepiped element body 2 and a plurality of external conductors disposed on the outer surface of the element body 2. The plurality of external conductors include an external electrode 3 (3A, 3B) formed on the side surface facing the longitudinal direction of the element body 2 and a terminal conductor 4 (4A) formed on the side surface facing the short direction of the element body 2. , 4B).

  As shown in FIG. 2, the element body 2 is laminated on a plurality of composite layers 5 in which internal electrodes 7 having different patterns are formed on a dielectric layer 6, and an outermost layer of the composite layer 5. And the dielectric layer 6 functioning as The dielectric layer 6 is made of a sintered body of a ceramic green sheet containing a dielectric ceramic, and the internal electrode 7 is made of a sintered body of a conductive paste. The actual multilayer capacitor 1 is integrated so that the boundary between the dielectric layers 6 and 6 is not visible.

  The external electrode 3 and the terminal conductor 4 are formed by baking a conductive paste containing conductive metal powder and glass frit. The external electrode 3 is an electrode connected to a predetermined polarity when the multilayer capacitor 1 is mounted. Further, the terminal conductor 4 is a conductor that connects in parallel internal electrodes 7 belonging to a later-described capacitance unit 11 in the element body 2 and is a so-called NC (No Contact) conductor that is not directly connected to the mounting board.

  The external electrode 3A is an electrode connected to, for example, + polarity (first polarity) when the multilayer capacitor 1 is mounted on the substrate, and one of the side surfaces 2a of the pair of side surfaces facing the longitudinal direction of the element body 2 is connected to the external electrode 3A. It is formed to cover. The external electrode 3 </ b> B is an electrode connected to, for example, a negative polarity (second polarity) when the multilayer capacitor 1 is mounted on the substrate, and the other side surface 2 b of the pair of side surfaces facing the longitudinal direction of the element body 2 It is formed to cover.

  The terminal conductor 4A is formed on one side surface 2c along the stacking direction among the side surfaces orthogonal to the pair of side surfaces 2a and 2b of the element body 2, and the terminal conductor 4B is formed on the other side surface 2d facing the side surface 2c. Has been. The terminal conductors 4 </ b> A and 4 </ b> B extend on the side surfaces 2 c and 2 d in a band shape in the above-described stacking direction, and have pad portions that protrude from the end surface of the element body 2 in the stacking direction. The external electrodes 3A and 3B and the terminal conductors 4A and 4B are in a state of being spaced apart by a predetermined distance and are electrically insulated from each other.

  A substrate 100 used for mounting the multilayer capacitor 1 has an anode land pattern 101A and a cathode land pattern 101B. The anode land pattern 101A and the cathode land pattern 101B are, for example, formed in a strip shape along the width direction of the external electrode 3A and the external electrode 3B, and are connected to predetermined circuit wiring. In the mounting structure of the multilayer capacitor 1, the external electrode 3A is bonded to the anode land pattern 101A, and the external electrode 3B is bonded to the cathode land pattern 101B. Further, the terminal conductor 4A and the terminal conductor 4B are not joined to either the anode land pattern 101A or the cathode land pattern 101B. That is, in the mounting structure of the multilayer capacitor 1, only the external electrode 3 </ b> A and the external electrode 3 </ b> B are bonded to the substrate 100.

  Next, the configuration of the element body 2 will be described in more detail.

  As shown in FIGS. 2 and 3, the element body 2 includes a capacitance unit 11 that mainly contributes to the capacitance of the multilayer capacitor, and an ESR control unit 12 that controls the ESR of the multilayer capacitor 1. Yes.

  As shown in FIG. 4, the capacitance portion 11 is formed by alternately stacking two composite layers 5A and 5B having different internal electrode shapes. As shown in FIG. 4A, the internal electrode 7A of the composite layer 5A has a main electrode portion 13A formed in the center portion and a lead portion 14A drawn from one side of the main electrode portion 13A. Yes. The main electrode portion 13A has a substantially rectangular shape. The lead portion 14A has a strip shape. An end portion of the lead portion 14A is exposed on the side surface 2c of the element body 2 and connected to the terminal conductor 4A.

  As shown in FIG. 4B, the internal electrode 7B of the composite layer 5B has a main electrode portion 13B formed in the center portion and a lead portion 14B drawn from one side of the main electrode portion 13B. Yes. The main electrode portion 13B has a substantially rectangular shape. In the first embodiment, the main electrode portion 13A and the main electrode portion 13B have the same shape. The lead portion 14B has a strip shape. The end of the lead portion 14B is exposed to the side surface 2d of the element body 2 opposite to the lead portion 14A and is connected to the terminal conductor 4B. In the first embodiment, the lead portion 14A and the lead portion 14B have the same shape.

  In the capacitance part 11, when viewed from the stacking direction, the part where the main electrode part 13A of the internal electrode 7A and the main electrode part 13B of the internal electrode 7B overlap each other is a capacity forming region. In the first embodiment, the entire surface of the main electrode portion 13A overlaps the entire surface of the main electrode portion 13B, so that a sufficient capacity forming region is secured.

  The ESR control unit 12 is disposed so as to sandwich the capacitance unit 11 when viewed from the stacking direction. As shown in FIG. 5, the ESR controller 12 is formed by two composite layers 5C and 5D having different internal electrode shapes. As shown in FIG. 5A, the internal electrode 7C of the composite layer 5C includes a main electrode portion 13C formed in the center portion, and lead portions 14C and 14D drawn from two different sides of the main electrode portion 13C. And have.

  The main electrode portion 13C has a substantially rectangular shape. The lead portions 14C and 14D have a strip shape. One end of the lead portion 14C is exposed on the side surface 2c of the element body 2 and is connected to the terminal conductor 4A. One end of the lead portion 14D is exposed on the side surface 2a of the element body 2 and connected to the external electrode 3A. The width of the lead portion 14D is set to be the same as the length of the short side of the main electrode portion 13C.

  With such a configuration of the composite layer 5C, the internal electrode 7A of the capacitance portion 11 is connected to the terminal conductor 4A via the lead portion 14A, and further, via the terminal conductor 4A and the lead portions 14C and 14D. It will be connected to the external electrode 3A. Therefore, the internal electrode 7A has a + polarity when mounted.

  The width of the lead portion 14C and the width of the lead portion 14A are set to be narrower than the width of the lead portion 14D. As a result, in the conductor portion (current path) connected from the internal electrode 7A to the external electrode 3A, a narrowed portion having a reduced cross-sectional area is formed.

  As shown in FIG. 5B, the internal electrode 7D of the composite layer 5D includes a main electrode portion 13D formed in the center portion and lead portions 14E and 14F drawn from two different sides of the main electrode portion 13D. And have. The main electrode portion 13D has a substantially rectangular shape. The lead portions 14E and 14F have a strip shape. One end of the lead portion 14E is exposed on the side surface 2d of the element body 2 and connected to the terminal conductor 4B. One end of the lead portion 14F is exposed on the side surface 2b of the element body 2 and connected to the external electrode 3B. The width of the lead portion 14F is set to be the same as the length of the short side of the main electrode portion 13D.

  With such a configuration of the composite layer 5D, the internal electrode 7B of the capacitance portion 11 is connected to the terminal conductor 4B via the lead portion 14E, and further, the terminal conductor 4B, the main electrode portion 13D, and the lead portion 14E. , 14F to be connected to the external electrode 3B. Therefore, the internal electrode 7B has a negative polarity when mounted.

  The width of the lead portion 14E and the width of the lead portion 14B are set to be narrower than the width of the lead portion 14F. As a result, in the conductor portion (current path) connected from the internal electrode 7B to the external electrode 3B, a narrowed portion having a narrow cross-sectional area is formed.

  In the multilayer capacitor 1 having the above-described configuration, the internal electrode 7 is connected only to the terminal conductor 4 in the capacitance unit 11, and the internal electrode 7 is connected to the terminal conductor 4 and the external electrode 3 in the ESR control unit 12. ing. Therefore, since the terminal conductor 4 to which the internal electrode 7 is connected in parallel is connected in series to the external electrode 3, a higher ESR is realized compared to the case where the internal electrode 7 is connected to the external electrode 3 in parallel as in the prior art. it can.

  In the multilayer capacitor 1, the internal electrodes 7A and the internal electrodes 7B having different polarities connected in the electrostatic capacitance unit 11 are alternately arranged, a lead portion 14A that connects the internal electrode 7A and the terminal conductor 4, and an internal electrode The lead portion 14B connecting the 7B and the terminal conductor 4B extends in the opposite direction toward the side surfaces 2c and 2d of the element body 2 facing each other. Therefore, as shown in FIG. 2, the direction of the flowing current is opposite between the capacitance forming region in the internal electrode 7A and the capacitance forming region in the internal electrode 7B, and a part of the magnetic field generated due to the current cancels out. Is done. Thereby, ESL can be reduced.

  Subsequently, a method for manufacturing the multilayer capacitor 1 having the above-described configuration will be described with reference to FIGS.

  FIG. 6 shows the procedure of the method for manufacturing the multilayer capacitor 1 according to the first embodiment. As shown in FIG. 6, the method for manufacturing the multilayer capacitor 1 according to the first embodiment includes the ceramic green sheet preparation step S <b> 1, the lamination step S <b> 2, the cutting step S <b> 3, the firing step S <b> 4, and the outer conductor forming step S <b> 5. I have.

  In the ceramic green sheet preparation step S1, a plurality of ceramic green sheets 20 shown in FIG. 7 are prepared. FIG. 7 is a plan view showing a ceramic green sheet.

  The ceramic green sheet 20 has a rectangular shape, and a plurality of internal electrode patterns are formed on the upper surface thereof. The plurality of internal electrode patterns include an internal electrode pattern 30 corresponding to the internal electrode 7A and an internal electrode pattern 40 corresponding to the internal electrode 7B. The internal electrode pattern 30 has a portion 31 corresponding to the main electrode portion 13A and a portion 33 corresponding to the lead portion 14A. The internal electrode pattern 40 has a portion 41 corresponding to the main electrode portion 13B and a portion 43 corresponding to the lead portion 14B.

  The internal electrode patterns 30 and the internal electrode patterns 40 are alternately arranged in the first direction (X direction in FIG. 7) and the second direction (Y direction in FIG. 7), and correspond to the lead portion 14A. The portion 33 and the portion 43 corresponding to the lead portion 14B are formed so as to extend across the planned cutting line C1. The internal electrode pattern 30 and the internal electrode pattern 40 adjacent in the second direction are continuous through the portions 33 and 43 corresponding to the respective lead portions 14A and 14B. The first direction is a direction parallel to one side of the ceramic green sheet 20, and the second direction is a direction parallel to one side of the ceramic green sheet 20 and a direction orthogonal to the first direction.

  In the ceramic green sheet preparation step S1, a plurality of ceramic green sheets 50 shown in FIG. 8 are prepared. FIG. 8 is a plan view showing a ceramic green sheet.

  The ceramic green sheet 50 has a rectangular shape, and a plurality of internal electrode patterns are formed on the upper surface thereof. The plurality of internal electrode patterns include an internal electrode pattern 60 corresponding to the internal electrode 7C and an internal electrode pattern 70 corresponding to the internal electrode 7D. The internal electrode pattern 60 has a portion 61 corresponding to the main electrode portion 13C, a portion 63 corresponding to the lead portion 14C, and a portion 65 corresponding to the lead portion 14D. The internal electrode pattern 70 includes a portion 71 corresponding to the main electrode portion 13D, a portion 73 corresponding to the lead portion 14E, and a portion 75 corresponding to the lead portion 14F.

  The internal electrode pattern 60 and the internal electrode pattern 70 are formed so as to be alternately arranged in the first direction (X direction in FIG. 8) and the second direction (Y direction in FIG. 8). In the internal electrode pattern 60 and the internal electrode pattern 70, a portion 63 corresponding to the lead portion 14C and a portion 73 corresponding to the lead portion 14E continue across the planned cutting line C1, and a portion 65 corresponding to the lead portion 14D. A portion 75 corresponding to the lead portion 14F is formed so as to continue across the planned cutting line C2, and further, the internal electrode patterns 60, 70 are alternately connected in one direction intersecting the first and second directions. ing. The internal electrode pattern 30 and the internal electrode pattern 40 which are adjacent in the second direction are continuous through the portions 63 and 73 corresponding to the respective lead portions 14C and 14E. The internal electrode pattern 30 and the internal electrode pattern 40 adjacent in the first direction are continuous through the portions 65 and 75 corresponding to the respective lead portions 14D and 14F. The internal electrode pattern 60 and the internal electrode pattern 70 are connected in a zigzag shape and extend in the one direction intersecting the first and second directions. The first direction is a direction parallel to one side of the ceramic green sheet 50, and the second direction is a direction parallel to one side of the ceramic green sheet 50 and perpendicular to the first direction.

  The ceramic green sheets 20 and 50 are, for example, a binder material (for example, an organic binder resin), a solvent, a plasticizer, and the like added to a dielectric material mainly composed of barium titanate, mixed and dispersed, and a ceramic slurry is applied onto the support. Thereafter, it is obtained by drying. The internal electrode patterns 30, 40, 60, 70 are formed, for example, by applying an electrode paste to the upper surface of the ceramic green sheets 20, 50 and then drying. The electrode paste is a paste-like composition obtained by mixing a binder resin, a solvent, or the like with a metal powder such as Ni, Ag, or Pd. As a method for applying the electrode paste, for example, there is a screen printing method.

  In the subsequent stacking step S2, as shown in FIG. 9, the first and second ceramic green sheets 20 and 50 together with the ceramic green sheets (not shown) in which the internal electrode pattern is not formed are combined. They are stacked in a third direction (Z direction in FIG. 9) perpendicular to the direction. Thereby, the ceramic green sheet laminate GM shown in FIG. 10 is obtained. At this time, the ceramic green sheets 20 and 50 are stacked such that the ceramic green sheets 20 and the ceramic green sheets 50 are displaced in the first direction by one internal electrode pattern. Further, the ceramic green sheets 20 and 50 are laminated so that the position of the internal electrode pattern 30 and the position of the internal electrode pattern 40 coincide with each other, and the position of the internal electrode pattern 60 and the position of the internal electrode pattern 70 coincide with each other. To do. That is, the ceramic green sheets 20 and 50 are portions 31, 41, 61, and 71 corresponding to the main electrode portions 13A, 13B, 13C, and 13D in the internal electrode patterns 30, 40, 60, and 70 when viewed from the third direction. Are stacked so that they overlap as a whole. The ceramic green sheet on which the internal electrode pattern is not formed constitutes the outermost layer of the ceramic green sheet laminate GM. The ceramic green sheets 20 and 50 may be laminated so that the ceramic green sheets 20 and the ceramic green sheets 50 are shifted in the second direction by one internal electrode pattern.

  In the subsequent cutting step S3, as shown in FIG. 11, the ceramic green sheet laminate GM is cut along the planned cutting lines C1 and C2. As a result, the multilayer chip MC of each multilayer capacitor 1 unit shown in FIG. 12 is obtained. FIG. 11 is an exploded plan view of the ceramic green sheet laminate GM for explaining the cutting step S3. The planned cutting line C1 and the planned cutting line C2 are orthogonal to each other.

  When the ceramic green sheet laminate GM is cut along the planned cutting line C1, the portions 33 and 43 corresponding to the continuous lead portions 14A and 14B are cut in the middle, and the cut surfaces correspond to the lead portions 14A and 14B. The portions 33 and 43 are exposed. Similarly, the portions 63 and 73 corresponding to the continuous lead portions 14C and 14E are cut in the middle, and the portions 63 and 73 corresponding to the lead portions 14C and 14E are exposed on the cut surface. When the ceramic green sheet laminate GM is cut along the planned cutting line C2, the portions 65 and 75 corresponding to the continuous lead portions 14D and 14F are cut in the middle, and the cut surfaces correspond to the lead portions 14D and 14F. Portions 65 and 75 are exposed. Therefore, portions 33, 43, 63, 73, 65, and 75 corresponding to the lead portions 14A, 14B, 14C, 14E, 14D, and 14F are exposed on the side surfaces of the multilayer chip MC.

  In the subsequent firing step S4, the multilayer chip MC is heated to perform drying, binder removal, and firing. Thereby, the element body 2 of the multilayer capacitor 1 is obtained.

  In the subsequent external conductor forming step S5, external electrodes 3A and 3B and terminal conductors 4A and 4B are formed on the outer surface of the element body 2. Thereby, the multilayer capacitor 1 described above is finally obtained. The external electrodes 3A and 3B and the terminal conductors 4A and 4B are formed by applying an electrode paste to the corresponding portions on the outer surface of the element body 2 and then baking and applying electroplating. For electroplating, for example, Cu, Ni and Sn can be used. As the electrode paste, for example, a paste mainly composed of Ag, Cu or Ni is used.

  As described above, in the manufacturing method according to the first embodiment, as the ceramic green sheet on which the internal electrode pattern is formed, the ceramic green sheet for the electrostatic capacitance part 11 on which the internal electrode patterns 30 and 40 are formed, and 20, Since it is only necessary to prepare two types of ceramic green sheets, the ceramic green sheet 50 for the ESR controller 12 in which the internal electrode patterns 60 and 70 are formed, the manufacturing process of the multilayer capacitor 1 is simplified and the manufacturing cost is reduced. Can be achieved.

  In the manufacturing method according to the first embodiment, in the internal electrode patterns 30 and 40 formed on the ceramic green sheet 20, the portions 33 and 43 corresponding to the lead portions 14A and 14B are continuous across the planned cutting line C1. . In the internal electrode patterns 60 and 70 formed on the ceramic green sheet 50, the portions 63 and 73 corresponding to the lead portions 14C and 14E are continuous across the planned cutting line C1, and the lead portions 14D and 14F are connected to the lead portions 14D and 14F. Corresponding portions 65 and 75 are continuous across the planned cutting line C2. Therefore, even when the ceramic green sheets 20 and 50 are laminated or when the ceramic green sheet laminate GM is cut, the obtained multilayer chip MC has the internal electrode patterns 30, 40, 60, The portions 33, 43, 63, 73, 65, 75 corresponding to the lead portions 14A, 14B, 14C, 14E, 14D, 14F in 70 are necessarily exposed on the side surfaces that are cut surfaces. Therefore, the generation of defective products in which the internal electrodes 7A, 7B, 7C, and 7D are not drawn out to the side surfaces 2a, 2b, 2c, and 2d of the element body 2 is suppressed, and the capacitance unit 11 and the ESR control unit 12 are included. Thus, the multilayer capacitor 1 including the protruding body 2 can be manufactured with a high yield.

(Second Embodiment)
Next, the configuration of the multilayer capacitor manufactured by the multilayer capacitor manufacturing method according to the second embodiment will be described with reference to FIGS. The multilayer capacitor in the second embodiment is different from the multilayer capacitor 1 in the first embodiment described above with respect to the shape of the internal electrodes 7C and 7D of the ESR control unit 12.

  Although illustration is omitted, the multilayer capacitor in the second embodiment includes the element body 2, the external electrodes 3A and 3B, and the terminal conductors 4A and 4B, as in the multilayer capacitor 1 described above. As shown in FIG. 12, the element body 2 is laminated on a plurality of composite layers 5 in which internal electrodes 7 having different patterns are formed on a dielectric layer 6 and an outermost layer of the composite layer 5. And the dielectric layer 6 functioning as As shown in FIG. 12, the element body 2 includes a capacitance unit 11 and an ESR control unit 12. The capacitance unit 11 has the same configuration as the capacitance unit 11 in the multilayer capacitor 1 described above.

  The ESR control unit 12 is formed by two composite layers 5C and 5D having different internal electrode shapes. As shown in FIG. 14A, the internal electrode 7C of the composite layer 5C includes a main electrode portion 13G formed in the central portion, and lead portions 14C and 14D drawn from two different sides of the main electrode portion 13G. And have. The main electrode portion 13G has a substantially rectangular shape, and is opposed to a substantially half portion on the external electrode 3B side of the main electrode portion 13A in the internal electrode 7A.

  The width of the lead portion 14D is set to be narrower than the width of the lead portion 14C and the width of the lead portion 14A. As a result, a constricted portion having a constricted cross-sectional area is formed at a position corresponding to the lead portion 14D on the current path connected from the internal electrode 7A to the external electrode 3A.

  As shown in FIG. 14B, the internal electrode 7C of the composite layer 5D includes a main electrode portion 13H formed at the center portion, and lead portions 14C and 14D drawn from two different sides of the main electrode portion 13H. And have. The main electrode portion 13H has a substantially rectangular shape, and is opposed to a substantially half portion on the external electrode 3A side of the main electrode portion 13B in the internal electrode 7B.

  The width of the lead portion 14F is set narrower than the width of the lead portion 14E and the width of the lead portion 14B. As a result, an aperture portion with a reduced cross-sectional area is formed at a position corresponding to the lead portion 14F on the current path that connects from the internal electrode 7B to the external electrode 3B.

  Even in the multilayer capacitor having the above-described configuration, high ESR can be realized as compared with the case of the multilayer capacitor 1 described above as compared with the conventional case where the internal electrode 7 is connected in parallel to the external electrode 3.

  In the multilayer capacitor according to the second embodiment, the width of the lead portion 14D of the internal electrode 7C and the width of the lead portion 14F of the internal electrode 7D in the ESR control unit 12 are larger than any width of the lead portions 14C, 14A, 14E, and 14B. Is also narrower. As a result, the cross-sectional area of the conductor portion connecting the internal electrode 7 and the external electrode 3 is reduced, and the ESR can be further improved.

  Then, with reference to FIGS. 15-19, the manufacturing method of the multilayer capacitor which has the above-mentioned structure is demonstrated.

  The manufacturing method of the multilayer capacitor according to the second embodiment includes each process of a ceramic green sheet preparation process, a lamination process, a cutting process, a firing process, and an external conductor forming process, as in the first embodiment.

  In the ceramic green sheet preparation step, a plurality of ceramic green sheets 20 shown in FIG. 7 are prepared. In the ceramic green sheet preparation step, a plurality of ceramic green sheets 50 shown in FIG. 15 are prepared. FIG. 15 is a plan view showing a ceramic green sheet.

  On the ceramic green sheet 50, an internal electrode pattern 60 corresponding to the internal electrode 7C and an internal electrode pattern 70 corresponding to the internal electrode 7D are formed. The internal electrode pattern 60 has a portion 67 corresponding to the main electrode portion 13G, a portion 63 corresponding to the lead portion 14C, and a portion 65 corresponding to the lead portion 14D. The internal electrode pattern 70 has a portion 77 corresponding to the main electrode portion 13H, a portion 73 corresponding to the lead portion 14E, and a portion 75 corresponding to the lead portion 14F.

  The internal electrode pattern 60 and the internal electrode pattern 70 are formed so as to be alternately arranged in the first direction (X direction in FIG. 15) and the second direction (Y direction in FIG. 15). In the internal electrode pattern 60 and the internal electrode pattern 70, a portion 63 corresponding to the lead portion 14C and a portion 73 corresponding to the lead portion 14E continue across the planned cutting line C1, and a portion 65 corresponding to the lead portion 14D. A portion 75 corresponding to the lead portion 14F is formed so as to continue across the planned cutting line C2, and further, the internal electrode patterns 60, 70 are alternately connected in one direction intersecting the first and second directions. ing. The internal electrode pattern 30 and the internal electrode pattern 40 which are adjacent in the second direction are continuous through the portions 63 and 73 corresponding to the respective lead portions 14C and 14E. The internal electrode pattern 30 and the internal electrode pattern 40 adjacent in the first direction are continuous through the portions 65 and 75 corresponding to the respective lead portions 14D and 14F. The internal electrode pattern 60 and the internal electrode pattern 70 are connected in a zigzag shape and extend in the one direction intersecting the first and second directions.

  In the subsequent stacking step, as shown in FIG. 16, the ceramic green sheets (not shown) in which the internal electrode pattern is not formed and the plurality of ceramic green sheets 20 and 50 are moved in the third direction (FIG. 16). In the Z direction). As a result, the ceramic green sheet laminate GM shown in FIG. 17 is obtained. At this time, the ceramic green sheets 20 and 50 are stacked such that the ceramic green sheets 20 and the ceramic green sheets 50 are displaced in the first direction by one internal electrode pattern. Further, the ceramic green sheets 20 and 50 are laminated so that the position of the internal electrode pattern 30 and the position of the internal electrode pattern 40 coincide with each other, and the position of the internal electrode pattern 60 and the position of the internal electrode pattern 70 coincide with each other. To do. That is, the ceramic green sheets 20 and 50 are portions 31, 41, 67, and 77 corresponding to the main electrode portions 13A, 13B, 13G, and 13H in the internal electrode patterns 30, 40, 60, and 70 when viewed from the third direction. Are stacked so that they overlap. In this case, the ceramic green sheets 20 and 50 may be laminated so that the ceramic green sheets 20 and the ceramic green sheets 50 are shifted in the second direction by one internal electrode pattern.

  In the subsequent cutting step, as shown in FIG. 18, the ceramic green sheet laminate GM is cut along the planned cutting lines C1 and C2. As a result, the multilayer chip MC of each multilayer capacitor 1 unit shown in FIG. 19 is obtained. FIG. 18 is an exploded plan view of the ceramic green sheet laminate GM for explaining the cutting process.

  When the ceramic green sheet laminate GM is cut along the planned cutting line C1, the portions 33 and 43 corresponding to the lead portions 14A and 14B are exposed on the cut surface, and the portions 63 and 73 corresponding to the lead portions 14C and 14E are respectively exposed. Exposed. When the ceramic green sheet laminate GM is cut along the planned cutting line C2, the portions 65 and 75 corresponding to the lead portions 14D and 14F are exposed on the cut surfaces, respectively. Therefore, portions 33, 43, 63, 73, 65, and 75 corresponding to the lead portions 14A, 14B, 14C, 14E, 14D, and 14F are exposed on the side surfaces of the multilayer chip MC.

  Through the subsequent firing step and external conductor forming step, the multilayer capacitor described above is finally obtained. The firing step and the outer conductor forming step are the same as the firing step S4 and the outer conductor forming step S5 in the first embodiment described above, and a description thereof is omitted.

  As described above, in the manufacturing method according to the second embodiment, similarly to the manufacturing method according to the first embodiment, the manufacturing process of the multilayer capacitor 1 is simplified, and the manufacturing cost can be reduced. The multilayer capacitor 1 including the element body 2 including the part 11 and the ESR control part 12 can be manufactured with high yield.

(Third embodiment)
Next, the configuration of the multilayer capacitor manufactured by the multilayer capacitor manufacturing method according to the third embodiment will be described with reference to FIGS. The multilayer capacitor in the third embodiment is different from the multilayer capacitor 1 in the first embodiment described above in that a dummy electrode is provided.

  Although not shown, the multilayer capacitor in the third embodiment includes an element body 2, external electrodes 3A and 3B, and terminal conductors 4A and 4B, as in the multilayer capacitor 1 described above. As shown in FIG. 20, the element body 2 is laminated on a plurality of composite layers 5 in which internal electrodes 7 having different patterns are formed on a dielectric layer 6, and an outermost layer of the composite layer 5. And the dielectric layer 6 functioning as As shown in FIG. 20, the element body 2 includes a capacitance unit 11 and an ESR control unit 12.

  As shown in FIG. 20, the capacitance part 11 is formed by alternately stacking a plurality of composite layers 5A and 5B having different internal electrode shapes. As shown in FIG. 21A, the composite layer 5A includes dummy electrodes 8A, 9A, and 10A in addition to the internal electrode 7A. The dummy electrodes 8A, 9A, and 10A are provided and spaced apart from the internal electrode 7A. One end of the dummy electrode 8A is exposed on the side surface 2a of the element body 2, and is connected to the external electrode 3A. One end of the dummy electrode 9A is exposed on the side surface 2b of the element body 2, and is connected to the external electrode 3B. One end of the dummy electrode 10A is exposed on the side surface 2d of the element body 2 and is connected to the terminal conductor 4B. The widths of the dummy electrodes 8A and 9A (the width in the short direction of the element body 2) are set to be substantially the same as the widths of the lead portions 14D and 14F. The width of the dummy electrode 10A is set to be substantially the same as the width of the lead portion 14B.

  As shown in FIG. 21B, the composite layer 5B includes dummy electrodes 8B, 9B, and 10B in addition to the internal electrode 7B. The dummy electrodes 8B, 9B, and 10B are provided and spaced apart from the internal electrode 7B. One end of the dummy electrode 8B is exposed to the side surface 2a of the element body 2, and is connected to the external electrode 3A. One end of the dummy electrode 9B is exposed on the side surface 2b of the element body 2, and is connected to the external electrode 3B. One end of the dummy electrode 10B is exposed on the side surface 2c of the element body 2, and is connected to the terminal conductor 4A. The widths of the dummy electrodes 8B and 9B (the width in the short direction of the element body 2) are also set to be substantially the same as the widths of the lead portions 14D and 14F. The width of the dummy electrode 10B is set to be substantially the same as the width of the lead portion 14A.

  As shown in FIG. 20, the ESR control unit 12 is formed of two composite layers 5C and 5D having different internal electrode shapes. As illustrated in FIG. 22A, the composite layer 5C includes dummy electrodes 9C and 10C in addition to the internal electrode 7C. The dummy electrodes 9C and 10C are provided and spaced apart from the internal electrode 7C. One end of the dummy electrode 9C is exposed on the side surface 2b of the element body 2, and is connected to the external electrode 3B. One end of the dummy electrode 10C is exposed on the side surface 2d of the element body 2, and is connected to the terminal conductor 4B. The width of the dummy electrode 9C (the width in the short direction of the element body 2) is set to be substantially the same as the width of the lead portion 14F. The width of the dummy electrode 10C is set to be substantially the same as the width of the lead portion 14B.

  As illustrated in FIG. 22B, the composite layer 5D includes dummy electrodes 8D and 10D in addition to the internal electrode 7D. The dummy electrodes 8D and 10D are provided and spaced apart from the internal electrode 7D. One end of the dummy electrode 8D is exposed on the side surface 2a of the element body 2, and is connected to the external electrode 3A. One end of the dummy electrode 10D is exposed on the side surface 2c of the element body 2, and is connected to the terminal conductor 4A. The width of the dummy electrode 8D (the width in the short direction of the element body 2) is set to be substantially the same as the width of the lead portion 14D. The width of the dummy electrode 10D is set to be substantially the same as the width of the lead portion 14A.

  In the element body 2, when viewed from the stacking direction, the dummy electrodes 8A, 8B, and 8D overlap with the lead portion 14D, the dummy electrodes 9A, 9B, and 9C overlap with the lead portion 14F, and the dummy electrodes 10A and 10C overlap with the lead portion 14A. The dummy electrodes 10B and 10D overlap the lead portion 14A.

  Even in the multilayer capacitor having the above-described configuration, high ESR can be realized as compared with the case of the multilayer capacitor 1 described above as compared with the conventional case where the internal electrode 7 is connected in parallel to the external electrode 3.

  Next, a method for manufacturing the multilayer capacitor having the above-described configuration will be described with reference to FIGS.

  The manufacturing method of the multilayer capacitor in accordance with the third embodiment includes each process of a ceramic green sheet preparation process, a lamination process, a cutting process, a firing process, and an external conductor forming process, as in the first and second embodiments.

  In the ceramic green sheet preparation step, a plurality of ceramic green sheets 20 shown in FIG. 23 are prepared. FIG. 23 is a plan view showing a ceramic green sheet.

  In addition to the internal electrode pattern 30 and the internal electrode pattern 40, the ceramic green sheet 20 includes a dummy electrode pattern 90 corresponding to the dummy electrodes 8A and 9B, a dummy electrode pattern 92 corresponding to the dummy electrodes 8B and 9A, and a dummy electrode 10A. , 10B, dummy electrode patterns 94 are formed. The dummy electrode pattern 90 includes a portion 90a corresponding to the dummy electrode 8A and a portion 90b corresponding to the dummy electrode 9B. The dummy electrode pattern 92 includes a portion 92a corresponding to the dummy electrode 8B and a portion 92b corresponding to the dummy electrode 9A. The dummy electrode pattern 94 includes a portion 94a corresponding to the dummy electrode 10A and a portion 94b corresponding to the dummy electrode 10B.

  The dummy electrode pattern 90 and the dummy electrode pattern 92 are formed so as to be alternately positioned between the internal electrode pattern 30 and the internal electrode pattern 40 in the first direction (X direction in FIG. 23). The dummy electrode pattern 90 is also formed such that a portion 90a corresponding to the dummy electrode 8A and a portion 90b corresponding to the dummy electrode 9B are continuous across the planned cutting line C2. The dummy electrode pattern 92 is also formed so that the portion 92a corresponding to the dummy electrode 8B and the portion 92b corresponding to the dummy electrode 9A are continuous across the planned cutting line C2. The dummy electrode patterns 90 are juxtaposed along the direction in which the planned cutting line C2 extends. The dummy electrode patterns 92 are juxtaposed along the direction in which the planned cutting line C2 extends.

  The dummy electrode pattern 94 is formed so as to be positioned between the internal electrode pattern 30 and the internal electrode pattern 40 in the second direction (Y direction in FIG. 23). The dummy electrode pattern 94 is also formed such that the portion 94a corresponding to the dummy electrode 10A and the portion 94b corresponding to the dummy electrode 10B are continuous across the planned cutting line C1.

  In the ceramic green sheet preparation step, a plurality of ceramic green sheets 50 shown in FIG. 24 are prepared. FIG. 24 is a plan view showing a ceramic green sheet.

  On the ceramic green sheet 50, in addition to the internal electrode pattern 60 and the internal electrode pattern 70, a dummy electrode pattern 96 corresponding to the dummy electrodes 8D and 9C and a dummy electrode pattern 98 corresponding to the dummy electrodes 10C and 10D are formed. ing. The dummy electrode pattern 96 includes a portion 96a corresponding to the dummy electrode 8D and a portion 96b corresponding to the dummy electrode 9C. The dummy electrode pattern 98 includes a portion 98a corresponding to the dummy electrode 10C and a portion 98b corresponding to the dummy electrode 10D.

  The dummy electrode patterns 96 are formed so as to be alternately positioned between the internal electrode patterns 60 and the internal electrode patterns 70 in the first direction (the X direction in FIG. 24). The dummy electrode pattern 96 is also formed such that a portion 96a corresponding to the dummy electrode 8D and a portion 96b corresponding to the dummy electrode 9C are continuous across the planned cutting line C2. The dummy electrode patterns 96 are juxtaposed along the direction in which the planned cutting line C2 extends.

  The dummy electrode pattern 98 is formed so as to be positioned between the internal electrode pattern 60 and the internal electrode pattern 70 in the second direction (Y direction in FIG. 24). The dummy electrode pattern 98 is also formed such that a portion 98a corresponding to the dummy electrode 10C and a portion 98b corresponding to the dummy electrode 10D are continuous across the planned cutting line C1.

  In the subsequent stacking step, as shown in FIG. 25, the ceramic green sheets (not shown) in which the internal electrode pattern is not formed and the plurality of ceramic green sheets 20 and 50 are moved in the third direction (FIG. 25). In the Z direction). Thereby, the ceramic green sheet laminated body GM shown in FIG. 26 is obtained.

  In the subsequent cutting step, as shown in FIG. 27, the ceramic green sheet laminate GM is cut along the planned cutting lines C1 and C2. As a result, the multilayer chip MC of each multilayer capacitor 1 unit shown in FIG. 28 is obtained. FIG. 27 is an exploded plan view of the ceramic green sheet laminate GM for explaining the cutting process.

  When the ceramic green sheet laminate GM is cut along the planned cutting line C1, portions 33 and 43 corresponding to the lead portions 14A and 14B, portions 63 and 73 corresponding to the lead portions 14C and 14E, and the dummy electrodes 10A, Portions 94a, 94b, 98a, and 98b corresponding to 10B, 10C, and 10D are exposed, respectively. When the ceramic green sheet laminate GM is cut along the planned cutting line C2, the portions 65 and 75 corresponding to the lead portions 14D and 14F, the portions 90a, 92a and 96a corresponding to the dummy electrodes 8A, 8B and 8D on the cut surface, and The portions 92b, 90b, 96b corresponding to the dummy electrodes 9A, 9B, 9C are exposed. Therefore, the multilayer chip MC corresponds to the lead portions 14A, 14B, 14C, 14E, 14D, 14F and the dummy electrodes 8A, 8B, 8D, 9A, 9B, 9C, 10A, 10B, 10C, 10D on the side surface. The portions 33, 43, 63, 73, 65, 75, 90a, 92a, 96a, 92b, 90b, 96b, 94a, 94b, 98a, and 98b are exposed.

  Through the subsequent firing step and external conductor forming step, the multilayer capacitor described above is finally obtained. The firing step and the outer conductor forming step are the same as the firing step S4 and the outer conductor forming step S5 in the first embodiment described above, and a description thereof is omitted.

  As described above, in the manufacturing method according to the third embodiment, as in the manufacturing methods according to the first and second embodiments, the manufacturing process of the multilayer capacitor 1 can be simplified, and the manufacturing cost can be reduced. The multilayer capacitor 1 including the element body 2 including the electrostatic capacitance unit 11 and the ESR control unit 12 can be manufactured with high yield.

  In the manufacturing method according to the third embodiment, in the dummy electrode pattern 90 formed on the ceramic green sheet 20, the portion 90a corresponding to the dummy electrode 8A and the portion 90b corresponding to the dummy electrode 9B cross the planned cutting line C2. It is continuous. In the dummy electrode pattern 92, the portion 92a corresponding to the dummy electrode 8B and the portion 92b corresponding to the dummy electrode 9A are continuous across the planned cutting line C2. In the dummy electrode pattern 94, a portion 94a corresponding to the dummy electrode 10A and a portion 94b corresponding to the dummy electrode 10B are continuous across the planned cutting line C1. In the dummy electrode pattern 96 formed on the ceramic green sheet 50, the portion 96a corresponding to the dummy electrode 8D and the portion 96b corresponding to the dummy electrode 9C are continuous across the planned cutting line C2. Also in the dummy electrode pattern 98, the portion 98a corresponding to the dummy electrode 10C and the portion 98b corresponding to the dummy electrode 10D are continuous across the planned cutting line C1. For this reason, in the multilayer chip MC, the dummy electrode patterns 90 to 98 (90a, 92a, 96a, 92b, 90b, 96b, 94a, 94b, 98a, 98b) are necessarily exposed on the side surfaces that are cut surfaces. The electrodes 8A, 8B, 8D, 9A, 9B, 9C, 10A, 10B, 10C, and 10D can also obtain the element body 2 drawn to the side surfaces 2a to 2d. The dummy electrodes 8A, 8B, 8D, 9A, 9B, 9C, 10A, 10B, 10C, and 10D are formed when the external electrodes 3A and 3B and the terminal conductors 4A and 4B are formed on the element body 2, respectively. The purpose is to increase the contact area between the terminal conductors 4A and 4B and improve the connection strength between the element body 2, the external electrodes 3A and 3B, and the terminal conductors 4A and 4B. Further, by forming the dummy electrode patterns 90 to 98 on the ceramic green sheets 20 and 50, the dummy electrode patterns 90 to 98 function as a step absorption layer, which is caused by the thickness of the internal electrode patterns 30, 40, 60, and 70. It is possible to prevent the occurrence of the level difference and prevent the multilayer chip MC (element body 2) from being deformed.

(Fourth embodiment)
Next, the configuration of the multilayer capacitor manufactured by the multilayer capacitor manufacturing method according to the fourth embodiment will be described with reference to FIGS. The multilayer capacitor in the fourth embodiment is different from the multilayer capacitor in the second embodiment described above in that a dummy electrode is provided.

  Although illustration is omitted, the multilayer capacitor in the fourth embodiment includes an element body 2, external electrodes 3A and 3B, and terminal conductors 4A and 4B, as in the multilayer capacitor 1 described above. As shown in FIG. 29, the element body 2 is laminated on a plurality of composite layers 5 in which internal electrodes 7 having different patterns are formed on a dielectric layer 6, and the outermost layer of the composite layer 5. And the dielectric layer 6 functioning as As shown in FIG. 29, the element body 2 includes a capacitance unit 11 and an ESR control unit 12.

  As shown in FIG. 29, the capacitance portion 11 is formed by alternately stacking a plurality of composite layers 5A and 5B having different internal electrode shapes. The composite layer 5A includes dummy electrodes 8A, 9A, and 10A in addition to the internal electrode 7A. The composite layer 5B includes dummy electrodes 8B, 9B, and 10B in addition to the internal electrode 7B.

  As shown in FIG. 29, the ESR controller 12 is formed of two composite layers 5C and 5D having different internal electrode shapes. As illustrated in FIG. 30A, the composite layer 5C includes dummy electrodes 9C and 10C in addition to the internal electrode 7C. As illustrated in FIG. 30B, the composite layer 5D includes dummy electrodes 8D and 10D in addition to the internal electrode 7D.

  Even in the multilayer capacitor having the above-described configuration, high ESR can be realized as compared with the case of the multilayer capacitor 1 described above as compared with the conventional case where the internal electrode 7 is connected in parallel to the external electrode 3.

  Next, a method for manufacturing the multilayer capacitor having the above-described configuration will be described with reference to FIGS.

  The manufacturing method of the multilayer capacitor in accordance with the fourth embodiment includes each process of a ceramic green sheet preparation process, a lamination process, a cutting process, a firing process, and an external conductor forming process, as in the first to third embodiments.

  In the ceramic green sheet preparation step, a plurality of ceramic green sheets 20 shown in FIG. 23 are prepared. On the ceramic green sheet 20, an internal electrode pattern 30, an internal electrode pattern 40, a dummy electrode pattern 90, a dummy electrode pattern 92, and a dummy electrode pattern 94 are formed. In the ceramic green sheet preparation step, a plurality of ceramic green sheets 50 shown in FIG. 31 are prepared. On the ceramic green sheet 50, an internal electrode pattern 60, an internal electrode pattern 70, a dummy electrode pattern 96, and a dummy electrode pattern 98 are formed. FIG. 31 is a plan view showing a ceramic green sheet.

  In the subsequent stacking step, as shown in FIG. 32, the ceramic green sheets (not shown) in which the internal electrode pattern is not formed and the plurality of ceramic green sheets 20 and 50 are moved in the third direction (FIG. 32). In the Z direction). Thereby, the ceramic green sheet laminated body GM shown in FIG. 33 is obtained.

  In the subsequent cutting step, as shown in FIG. 34, the ceramic green sheet laminate GM is cut along the planned cutting lines C1 and C2. As a result, the multilayer chip MC of each multilayer capacitor 1 unit shown in FIG. 35 is obtained. FIG. 34 is an exploded plan view of the ceramic green sheet laminate GM for explaining the cutting process.

  Through the subsequent firing step and external conductor forming step, the multilayer capacitor described above is finally obtained. The firing step and the outer conductor forming step are the same as the firing step S4 and the outer conductor forming step S5 in the first embodiment described above, and a description thereof is omitted.

  As described above, in the manufacturing method according to the fourth embodiment, as in the manufacturing methods according to the first to third embodiments, the manufacturing process of the multilayer capacitor 1 can be simplified, and the manufacturing cost can be reduced. The multilayer capacitor 1 including the element body 2 including the electrostatic capacitance unit 11 and the ESR control unit 12 can be manufactured with high yield.

  The preferred embodiments of the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  The number and order of lamination of the ceramic green sheets 20 and 50 are not limited to the above-described embodiment. For example, the ceramic green sheets 50 may be continuously laminated, or may be laminated between the ceramic green sheets 20. The number of ceramic green sheets 20 and 50 formed on the ceramic green sheets 20 and 50 is not limited to the above-described embodiment.

  As shown in FIG. 36, the dummy electrode patterns 90 and 92 may be formed continuously in the direction in which the planned cutting line C2 extends.

1 is a perspective view showing a multilayer capacitor according to a first embodiment. It is a figure which shows the layer structure of the multilayer capacitor shown in FIG. It is the III-III sectional view taken on the line in FIG. It is a top view which shows the composite layer of an electrostatic capacitance part. It is a top view which shows the composite layer of an ESR control part. It is a flowchart which shows the procedure of the manufacturing method of the multilayer capacitor which concerns on 1st Embodiment. It is a top view which shows a ceramic green sheet. It is a top view which shows a ceramic green sheet. It is a perspective view which shows the lamination | stacking order of the ceramic green sheet in a lamination process. It is a perspective view which shows a ceramic green sheet laminated body. It is the top view which decomposed | disassembled and represented the ceramic green sheet laminated body in order to demonstrate a cutting process. It is a perspective view which shows a laminated body chip | tip. It is a figure which shows the layer structure of the multilayer capacitor which concerns on 2nd Embodiment. It is a top view which shows the composite layer of an ESR control part. It is a top view which shows a ceramic green sheet. It is a perspective view which shows the lamination | stacking order of the ceramic green sheet in a lamination process. It is a perspective view which shows a ceramic green sheet laminated body. It is the top view which decomposed | disassembled and represented the ceramic green sheet laminated body in order to demonstrate a cutting process. It is a perspective view which shows a laminated body chip | tip. It is a figure which shows the layer structure of the multilayer capacitor which concerns on 3rd Embodiment. It is a top view which shows the composite layer of an electrostatic capacitance part. It is a top view which shows the composite layer of an ESR control part. It is a top view which shows a ceramic green sheet. It is a top view which shows a ceramic green sheet. It is a perspective view which shows the lamination | stacking order of the ceramic green sheet in a lamination process. It is a perspective view which shows a ceramic green sheet laminated body. It is the top view which decomposed | disassembled and represented the ceramic green sheet laminated body in order to demonstrate a cutting process. It is a perspective view which shows a laminated body chip | tip. It is a figure which shows the layer structure of the multilayer capacitor which concerns on 4th Embodiment. It is a top view which shows the composite layer of an ESR control part. It is a top view which shows a ceramic green sheet. It is a perspective view which shows the lamination | stacking order of the ceramic green sheet in a lamination process. It is a perspective view which shows a ceramic green sheet laminated body. It is the top view which decomposed | disassembled and represented the ceramic green sheet laminated body in order to demonstrate a cutting process. It is a perspective view which shows a laminated body chip | tip. It is a top view which shows the modification of a ceramic green sheet.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor, 2 ... Element body, 2a, 2b, 2c, 2d ... Side surface, 6 ... Dielectric layer, 7 (7A, 7B, 7C, 7D) ... Internal electrode, 8A, 8B, 8D, 9A, 9B, 9C, 10A, 10B, 10C, 10D ... dummy electrode, 11 ... electrostatic capacity unit, 12 ... ESR control unit, 13A, 13B, 13C, 13D, 13G, 13H ... main electrode unit, 14A, 14B, 14C, 14E, 14D, 14F ... drawer portion, 20, 50 ... ceramic green sheet, 30, 40, 60, 70 ... internal electrode pattern, 31, 41, 61, 67, 71, 77 ... portions corresponding to the main electrode portion, 33, 43 , 63, 65, 73, 75... Corresponding to the lead-out portion, 90, 92, 94, 96, 98. Step, S4 ... firing step, S5 ... outer conductor forming step, C1, C2 ... cutting line, GM ... ceramic green sheet laminate, MC ... laminate chip.

Claims (3)

A substantially rectangular parallelepiped element body in which a plurality of internal electrodes are stacked with a dielectric layer interposed therebetween, wherein the element body is drawn to one side surface and connected to a first polarity; A capacitance portion formed by alternately arranging at least one dielectric layer between the second internal electrodes that are drawn out to one side surface opposite to the one side surface and connected to the second polarity; A third internal electrode extending to the one side surface from which the first internal electrode is extracted and a side surface adjacent to the one side surface and connected to the first polarity; and the third internal electrode The second internal electrode excluding the two side surfaces from which the electrodes are drawn out is drawn to the one side surface from which the electrodes are drawn and one side surface adjacent to the one side surface, and is connected to the second polarity. ES having internal electrodes A method of manufacturing a multilayer capacitor and a control unit,
A first ceramic green sheet for the electrostatic capacitance portion on which a first internal electrode pattern corresponding to the first internal electrode and a second internal electrode pattern corresponding to the second internal electrode are formed; Preparing multiple sheets,
A plurality of second ceramic green sheets for the ESR control unit on which a third internal electrode pattern corresponding to the third internal electrode and a fourth internal electrode pattern corresponding to the fourth internal electrode are formed. A process of preparing sheets,
Laminating a plurality of the first and second ceramic green sheets such that the first ceramic green sheets and the second ceramic green sheets are displaced in a predetermined direction by one internal electrode pattern, Obtaining a ceramic green sheet laminate;
Cutting the ceramic green sheet laminate along a predetermined cutting line to obtain a laminate chip of each multilayer capacitor unit; and
Firing the laminate chip and obtaining the element body,
In the step of preparing the first ceramic green sheet, the first and second internal electrode patterns are alternately arranged in the predetermined direction and a direction orthogonal to the predetermined direction, and the first The first and second internal electrode patterns are arranged so that portions corresponding to the lead portions of the first and second internal electrodes in the second internal electrode pattern continue across the predetermined cutting line. Forming,
In the step of preparing the second ceramic green sheet, the third and fourth internal electrode patterns are alternately arranged in the predetermined direction and a direction orthogonal to the predetermined direction, and the third And a portion of the fourth internal electrode pattern corresponding to the lead portion of the third and fourth internal electrodes is continuous across the predetermined cutting line and is perpendicular to the predetermined direction. A method of manufacturing a multilayer capacitor, wherein the third and fourth internal electrode patterns are formed so that the third and fourth internal electrode patterns are alternately connected in one direction intersecting with. The predetermined planned cutting line includes a first planned cutting line extending in a direction parallel to the predetermined direction, and a second planned cutting line orthogonal to the first planned cutting line,
The portions corresponding to the lead portions of the third and fourth internal electrodes have different widths in a region straddling the first planned cutting line and a region straddling the second planned cutting line. The method for producing a multilayer capacitor according to claim 1. In the step of preparing the first ceramic green sheet, an electrode pattern for a dummy electrode is formed so as to have a distance from the first and second internal electrode patterns and straddle the predetermined cutting line,
In the step of preparing the second ceramic green sheet, an electrode pattern for a dummy electrode is formed so as to have a distance from the third and fourth internal electrode patterns and straddle the predetermined cutting line. The method for manufacturing a multilayer capacitor according to claim 1.

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