JP2000040634A - Manufacture of laminated ceramic capacitor - Google Patents

Manufacture of laminated ceramic capacitor

Info

Publication number
JP2000040634A
JP2000040634A JP10208916A JP20891698A JP2000040634A JP 2000040634 A JP2000040634 A JP 2000040634A JP 10208916 A JP10208916 A JP 10208916A JP 20891698 A JP20891698 A JP 20891698A JP 2000040634 A JP2000040634 A JP 2000040634A
Authority
JP
Japan
Prior art keywords
internal electrode
layer
inner electrodes
laminated
wide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10208916A
Other languages
Japanese (ja)
Inventor
Yukihito Yamashita
由起人 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10208916A priority Critical patent/JP2000040634A/en
Publication of JP2000040634A publication Critical patent/JP2000040634A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To specify the effective laminated area of a pair of inner electrodes for acquiring a required electrostatic capacity even if the printing precision in the width direction of the inner electrodes is deteriorate, by a method wherein the narrow width inner electrodes alternately laminated holding a ceramic layer are arranged in irregularly slid positions in the widthwise direction within both side range of the wide width inner electrodes. SOLUTION: Greensheets for ceramic layers 2 are laminated on the lower ineffective layers 3, and then the narrow width inner electrode 5 as the first layer are printed on the green sheets. Next, the greensheets are laminated on the inner electrodes layers 5 so as to print the widewidth inner electrodes 6 as the second layer paired with the first layer narrow width inner electrodes 5. In such a constitution, the greensheets, narrow width inner electrodes 5, ceramic layers 2, wide width inner electrodes 6 are alternately and successively laminated in a specific numbers and finally, after print-laminating the narrow width inner electrodes 5, upper ineffective layers 4 are pressure-laminated. At this time, the narrow width inner electrodes 5 are print-laminated in irregularly slid positions in the widthwise direction within the width dimensional range of the wide width inner electrodes 6.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は積層セラミックコン
デンサ(以降、積層コンデンサと称する)の製造方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer ceramic capacitor (hereinafter referred to as a multilayer capacitor).

【0002】[0002]

【従来の技術】従来の積層コンデンサの製造方法につい
て、図を用いて説明する。
2. Description of the Related Art A conventional method for manufacturing a multilayer capacitor will be described with reference to the drawings.

【0003】図6は従来の積層コンデンサのグリーン積
層体の斜視図、図7はその断面図、図8はその展開図、
図9は焼結体の斜視図、図10は完成品の斜視図であ
る。
FIG. 6 is a perspective view of a green laminate of a conventional multilayer capacitor, FIG. 7 is a cross-sectional view thereof, FIG.
FIG. 9 is a perspective view of a sintered body, and FIG. 10 is a perspective view of a finished product.

【0004】先ず、公知の積層コンデンサ製造方法を用
い、セラミック誘電体層(以降、セラミック層と称す
る)42グリーンシートを作製する。
[0004] First, a ceramic dielectric layer (hereinafter, referred to as a ceramic layer) 42 green sheet is manufactured by using a known multilayer capacitor manufacturing method.

【0005】次に作成したセラミック層42グリーンシ
ートを複数枚積層し下部無効層43、上部無効層44を
それぞれ作製する。
Next, a plurality of green sheets formed of the ceramic layer 42 are laminated to form a lower ineffective layer 43 and an upper ineffective layer 44, respectively.

【0006】次いで下部無効層43面上にセラミック層
42グリーンシートを積層し、その上に第一層目の内部
電極45を印刷する。続いて第一層目の内部電極45上
にセラミック層42グリーンシートを積層し、その上に
第一層の内部電極45と対になる第二層目の内部電極4
5を印刷する。このようにして順次セラミック層42グ
リーンシート、内部電極45を交互に所定層積層した
後、最後に上部無効層44を重ね、加圧積層して積層体
グリーンブロック(図示せず)を作製する。この時それ
ぞれの内部電極45は長方形の同一形状をしており、積
層体グリーンブロックを図6に示すグリーン積層体41
形状に切断した際に、内部電極45の短辺側の一方の端
部が交互に一層おきに、グリーン積層体41の対向する
異なる端面に露出するように、内部電極45の長手方向
に一層毎にずらして印刷積層する。
Next, a ceramic layer 42 green sheet is laminated on the lower ineffective layer 43 surface, and a first-layer internal electrode 45 is printed thereon. Subsequently, a ceramic layer 42 green sheet is laminated on the first-layer internal electrode 45, and a second-layer internal electrode 4 paired with the first-layer internal electrode 45 is formed thereon.
Print 5 In this way, the ceramic layer 42 green sheets and the internal electrodes 45 are sequentially laminated alternately in a predetermined layer, and finally the upper ineffective layer 44 is laminated and pressure laminated to produce a laminated green block (not shown). At this time, each of the internal electrodes 45 has the same rectangular shape, and the laminate green block is formed by a green laminate 41 shown in FIG.
When cut into a shape, one end portion on the short side of the internal electrode 45 is alternately placed every other layer so that it is exposed to different end surfaces facing each other of the green laminated body 41 so as to be exposed one by one in the longitudinal direction of the internal electrode 45. To print and stack.

【0007】その後、作製した積層体グリーンブロック
を図6に示すグリーン積層体41の形状に切断を行い、
続いて所定温度で焼成し図9に示すような焼結体47を
作製する。
[0007] Thereafter, the produced green block laminate is cut into a green laminate 41 shown in FIG.
Subsequently, firing is performed at a predetermined temperature to produce a sintered body 47 as shown in FIG.

【0008】得られた焼結体47のバレル研磨を行い、
焼結体47の内部に形成された内部電極45群を焼結体
47の両端面に露出させた後、内部電極45群が露出し
た端面部全体を覆うように外部電極48を形成し、図1
0に示すような積層コンデンサ49を製造する。
[0008] Barrel polishing of the obtained sintered body 47,
After exposing a group of internal electrodes 45 formed inside the sintered body 47 to both end surfaces of the sintered body 47, an external electrode 48 is formed so as to cover the entire end face portion where the group of internal electrodes 45 is exposed. 1
A multilayer capacitor 49 as shown in FIG.

【0009】[0009]

【発明が解決しようとする課題】しかしながら図7に示
したように内部電極45の幅方向の印刷精度が低下する
と、セラミック層42を挟んで対向する一対のそれぞれ
の内部電極45は有効重なり面積が小さくなり、静電容
量値が設計値より小さくなると共に、内部電極45の積
層数が多くなるにしたがって内部電極45の形成部の厚
さと、電極非形成部の厚さの差が大きくなり、焼結体の
外形が歪んだりまた、内部構造欠陥のデラミネーション
が発生したりするという問題点があった。
However, when the printing accuracy of the internal electrodes 45 in the width direction is reduced as shown in FIG. 7, the pair of internal electrodes 45 facing each other with the ceramic layer 42 interposed therebetween has an effective overlapping area. The capacitance value becomes smaller than the design value, and the difference between the thickness of the portion where the internal electrode 45 is formed and the thickness of the portion where the electrode is not formed increases as the number of stacked internal electrodes 45 increases. There has been a problem that the outer shape of the aggregate is distorted and delamination of internal structural defects occurs.

【0010】本発明は前記従来の問題点を解決し、内部
電極の幅方向の印刷精度が低下しても、一対の内部電極
の有効重なり面積が一定で、略設計値通りの静電容量が
得られ、かつ内部構造欠陥の発生を抑制することのでき
る積層コンデンサを提供することを目的とするものであ
る。
The present invention solves the above-mentioned conventional problems. Even if the printing accuracy in the width direction of the internal electrodes is reduced, the effective overlapping area of the pair of internal electrodes is constant, and the capacitance is substantially as designed. It is an object of the present invention to provide a multilayer capacitor which can be obtained and can suppress occurrence of internal structural defects.

【0011】[0011]

【課題を解決するための手段】前記目的を達成するため
に本発明は、幅広内部電極と幅狭内部電極を一対にして
セラミック層を挟んで交互に複数層積層し、しかも幅狭
内部電極は幅広内部電極の両側辺範囲内で幅方向に不規
則にずらす様に配置することで、内部電極の幅方向の印
刷精度が低下しても、一定の有効重なり面積が確保され
略設計値通りの静電容量を得ることができる。更に、幅
狭内部電極を積層コンデンサの幅方向に不規則にずらす
ことにより、内部電極群の重なり部分が積層コンデンサ
の幅方向で分散され、内部電極群の形成部分と非形成部
分との厚み差が少なくなり、焼結後の積層コンデンサの
変形、とデラミネーションの発生を抑制することができ
るものである。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of forming a pair of wide internal electrodes and narrow internal electrodes and alternately laminating a plurality of layers with a ceramic layer interposed therebetween. By arranging irregularly in the width direction within the range of both sides of the wide internal electrode, even if the printing accuracy in the width direction of the internal electrode is reduced, a certain effective overlapping area is secured and almost as designed. Capacitance can be obtained. Furthermore, by displacing the narrow internal electrodes irregularly in the width direction of the multilayer capacitor, the overlapping portion of the internal electrode group is dispersed in the width direction of the multilayer capacitor, and the difference in thickness between the portion where the internal electrode group is formed and the portion where the internal electrode group is not formed. And the deformation of the multilayer capacitor after sintering and the occurrence of delamination can be suppressed.

【0012】[0012]

【発明の実施の形態】本発明の請求項1に記載の発明
は、素体内部に内部電極とセラミック層を交互に複数層
積層し、内部電極の一方の端部をセラミック層を挟んで
一層おき交互に、素体の対向する異なる端面に露出さ
せ、両端面に露出した内部電極層の端部と電気的に接続
するように外部電極を形成した積層コンデンサにおい
て、内部電極はセラミック層を挟んで交互に積層した幅
広内部電極と幅狭内部電極よりなり、幅広内部電極は素
体の一方の端面に、また幅狭内部電極を対向するもう一
方の端面に露出させたことを特徴とする積層コンデンサ
の製造方法であって、これにより内部電極群の幅方向の
印刷精度が低下しても、セラミック層を挟んで対向する
ように積層された一対の幅広内部電極と幅狭内部電極間
の有効重なり面積を一定にすることが可能となり、設計
値通りの静電容量を有する積層コンデンサを得ることが
出来るという作用を有するものである。
BEST MODE FOR CARRYING OUT THE INVENTION According to the first aspect of the present invention, a plurality of internal electrodes and ceramic layers are alternately laminated inside a body, and one end of the internal electrode is sandwiched between ceramic layers. Alternately, in a multilayer capacitor that is exposed to different end faces facing the element body and external electrodes are formed so as to be electrically connected to ends of the internal electrode layers exposed at both end faces, the internal electrodes sandwich the ceramic layer. A wide internal electrode and a narrow internal electrode, which are alternately laminated in the above manner, wherein the wide internal electrode is exposed on one end face of the element body and the narrow internal electrode is exposed on the other end face facing the laminate. A method for manufacturing a capacitor, wherein even if the printing accuracy in the width direction of the internal electrode group is reduced, the effective width between a pair of wide internal electrodes and a narrow internal electrode stacked so as to face each other with a ceramic layer interposed therebetween. Constant overlapping area It becomes possible, and has the effect that it is possible to obtain a multilayer capacitor having a capacitance as designed for.

【0013】本発明の請求項2に記載の発明は、幅狭内
部電極は積層コンデンサの幅方向に、幅広内部電極の両
側辺からはみ出さない範囲内で不規則にずらして配置さ
せたことを特徴とする請求項1に記載の積層コンデンサ
の製造方法であって、これにより内部電極群の幅方向の
印刷精度が低下しても、セラミック層を挟んで対向する
ように積層された一対の幅広内部電極と幅狭内部電極間
の有効重なり面積を一定にすることが可能となり、設計
値通りの静電容量を得ることが出来ると共に、内部電極
群形成部分と非形成部分との厚み差が少なくなり、焼結
後の積層コンデンサの変形とデラミネーションの発生を
抑制することができるという作用を有するものである。
According to a second aspect of the present invention, the narrow internal electrodes are irregularly displaced in the width direction of the multilayer capacitor within a range not protruding from both sides of the wide internal electrodes. The method for manufacturing a multilayer capacitor according to claim 1, wherein even if the printing accuracy of the internal electrode group in the width direction is reduced, a pair of wide capacitors stacked so as to face each other with the ceramic layer interposed therebetween. The effective overlapping area between the internal electrode and the narrow internal electrode can be kept constant, the capacitance can be obtained as designed, and the thickness difference between the internal electrode group forming part and the non-forming part is small. In other words, it has an effect that deformation and delamination of the multilayer capacitor after sintering can be suppressed.

【0014】本発明の請求項3に記載の発明は、幅狭内
部電極を幅広内部電極より外層に配置することを特徴と
する請求項1または請求項2に記載の積層コンデンサの
製造方法であって、焼結後のバレル研磨で研磨されやす
い素体の上下無効層に近い側に幅狭内部電極を常に配置
しているため、幅が狭い幅狭内部電極であっても、最外
層の一方の端部を確実に素体端面に露出させることがで
き、外部電極との電気的接続が確保されるという作用を
有するものである。
According to a third aspect of the present invention, there is provided the method of manufacturing a multilayer capacitor according to the first or second aspect, wherein the narrow internal electrodes are arranged in an outer layer than the wide internal electrodes. Therefore, since the narrow internal electrodes are always arranged on the side near the upper and lower ineffective layers of the element body which is easily polished by barrel polishing after sintering, even if the internal electrodes are narrower, one of the outermost layers Can be reliably exposed to the end face of the element body, and has the effect of ensuring electrical connection with external electrodes.

【0015】本発明の請求項4に記載の発明は、最外層
の幅狭内部電極外方の無効層の厚さを、幅広内部電極と
幅狭内部電極に挟まれた有効層より厚くすることを特徴
とする請求項3に記載の積層セラミックコンデンサの製
造方法であって、無効層を、有効層より厚くしているた
め、積層コンデンサの外部電極間に高電圧を印加した時
の耐圧絶縁破壊は絶縁距離が短い有効層間で常に起こ
り、耐圧絶縁破壊電圧の低下を防ぐことができるという
作用を有するものである。
According to a fourth aspect of the present invention, the thickness of the ineffective layer outside the narrow inner electrode in the outermost layer is made larger than the effective layer sandwiched between the wide internal electrode and the narrow internal electrode. 4. The method for manufacturing a multilayer ceramic capacitor according to claim 3, wherein the ineffective layer is thicker than the effective layer, so that a withstand voltage breakdown when a high voltage is applied between external electrodes of the multilayer capacitor. Has an effect that it always occurs between the effective layers having a short insulation distance and can prevent a decrease in the breakdown voltage.

【0016】本発明の請求項5に記載の発明は幅広内部
電極側辺と素体側面までの幅を、幅広内部電極と幅狭内
部電極に挟まれた有効層の厚みより大きくすることを特
徴とする請求項1から請求項4のいずれか一つに記載の
積層セラミックコンデンサの製造方法であって、これに
より積層コンデンサの幅広内部電極側辺から素体側面ま
での距離が大きいため、積層セラミックコンデンサの外
部電極間に高電圧を印加した時の耐圧絶縁破壊は絶縁距
離が短い有効層間で常に起こり、耐圧絶縁破壊電圧の低
下を防ぐことができるという作用を有するものである。
The invention according to claim 5 of the present invention is characterized in that the width between the side of the wide internal electrode and the side surface of the element body is made larger than the thickness of the effective layer sandwiched between the wide internal electrode and the narrow internal electrode. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 4, wherein a distance from a side of the wide internal electrode of the multilayer capacitor to a side surface of the element body is large. The withstand voltage breakdown when a high voltage is applied between the external electrodes of the capacitor always occurs between effective layers having a short insulation distance, and has an effect of preventing a decrease in the withstand voltage breakdown voltage.

【0017】(実施の形態)図1から図5に本発明の一
実施形態の積層コンデンサを示した。図1はグリーン積
層体の斜視図、図2はグリーン積層体の断面図、図3は
グリーン積層体の展開図、図4は焼結体の斜視図、図5
は完成品の斜視図である。図1〜図5において、1はグ
リーン積層体、2はセラミック層、3は下部無効層、4
は上部無効層、5は幅狭内部電極、6は幅広内部電極、
7は焼結体、8は外部電極、9は完成品(積層コンデン
サ)である。
(Embodiment) FIGS. 1 to 5 show a multilayer capacitor according to an embodiment of the present invention. 1 is a perspective view of a green laminate, FIG. 2 is a cross-sectional view of the green laminate, FIG. 3 is a development view of the green laminate, FIG. 4 is a perspective view of a sintered body, and FIG.
Is a perspective view of the finished product. 1 to 5, 1 is a green laminate, 2 is a ceramic layer, 3 is a lower ineffective layer, 4
Is the upper inactive layer, 5 is the narrow internal electrode, 6 is the wide internal electrode,
7 is a sintered body, 8 is an external electrode, and 9 is a finished product (multilayer capacitor).

【0018】先ず、セラミック誘電体粉末とバインダ
ー、及び可塑剤を混合分散したスラリーからリバースロ
ール成形法を用い、セラミック層2用のグリーンシート
を作製する。
First, a green sheet for the ceramic layer 2 is prepared from a slurry in which a ceramic dielectric powder, a binder, and a plasticizer are mixed and dispersed by a reverse roll molding method.

【0019】作製したセラミック層2用のグリーンシー
トを複数枚積層し下部無効層3、上部無効層4をそれぞ
れ作製する。
A plurality of green sheets for the ceramic layer 2 are laminated to form a lower ineffective layer 3 and an upper ineffective layer 4, respectively.

【0020】次にセラミック層2用グリーンシートを下
部無効層3の上に積層し、その上に図3に示す様に第一
層目の幅狭内部電極5を印刷する。続いて第一層目の幅
狭内部分極5層の上にセラミック層2用のグリーンシー
トを積層し、その上に第一層目の幅狭内部電極5と対に
なる第二層目の幅広内部電極6を印刷する。このように
してセラミック層2用のグリーンシート、幅狭内部電極
5、セラミック層2、幅広内部電極6と交互に順次所定
数積層し、最後に幅狭内部電極5を印刷積層した後、上
部無効層4を重ね加圧積層して積層体グリーンブロック
(図示せず)を作製する。この時に図2に示す様に、幅
狭内部電極5は幅広内部電極6の幅寸法内で幅方向に不
規則にずらして印刷積層するため、幅狭内部電極5、及
び幅広内部電極6が幅方向の印刷精度が低下しても、有
効重なり面積が一定で小さくなることはなく、設計値通
りの静電容量を容易に得ることが出来る。更に幅狭内部
電極5の最下段と最上段のものを、共に幅広内部電極6
より下部無効層3、上部無効層4に近い側、即ちバレル
研磨で研磨されやすい側に配置しているため、最外層の
幅狭内部電極5の端部は確実に、焼結体7の一方の端面
に露出させることができ、焼結体7の端面部に形成する
外部電極8と確実に導通し設計値通りの静電容量を容易
に得ることが出来るようになる。
Next, a green sheet for the ceramic layer 2 is laminated on the lower ineffective layer 3, and a first-layer narrow internal electrode 5 is printed thereon as shown in FIG. Subsequently, a green sheet for the ceramic layer 2 is laminated on the first five narrow internal polarization layers, and a second wide electrode paired with the first narrow internal electrode 5 is formed thereon. The internal electrodes 6 are printed. In this manner, a predetermined number of the green sheets for the ceramic layer 2, the narrow internal electrodes 5, the ceramic layer 2, and the wide internal electrodes 6 are alternately laminated in order, and finally the narrow internal electrodes 5 are printed and laminated. The layers 4 are stacked and laminated under pressure to produce a laminate green block (not shown). At this time, as shown in FIG. 2, the narrow internal electrodes 5 are printed and laminated while being shifted irregularly in the width direction within the width dimension of the wide internal electrodes 6, so that the narrow internal electrodes 5 and the wide internal electrodes 6 have a wide width. Even if the printing accuracy in the direction decreases, the effective overlapping area does not become constant and small, and the capacitance as designed can be easily obtained. Further, the lowermost and uppermost narrow internal electrodes 5 are replaced with the wide internal electrodes 6.
Since it is disposed on the side closer to the lower ineffective layer 3 and the upper ineffective layer 4, that is, on the side that is easily polished by barrel polishing, the end of the narrowest internal electrode 5 in the outermost layer is surely placed on one side of the sintered body 7. At the end face of the sintered body 7, and the external electrode 8 formed on the end face of the sintered body 7 is reliably conducted, so that the capacitance as designed can be easily obtained.

【0021】また下部無効層3と上部無効層4の厚さ、
及び幅広内部電極6側辺から焼結体7側面までの幅を、
セラミック層2の厚さより大きくしているため、外部電
極8間に異常な高電圧が印加された時の耐圧絶縁破壊は
絶縁距離が短いセラミック層2間で常に起こり、耐圧絶
縁破壊電圧の低下を防止するようにしている。
The thickness of the lower invalid layer 3 and the upper invalid layer 4;
And the width from the side of the wide internal electrode 6 to the side of the sintered body 7
Since the thickness is larger than the thickness of the ceramic layer 2, the breakdown voltage breakdown when an abnormally high voltage is applied between the external electrodes 8 always occurs between the ceramic layers 2 having a short insulation distance, and the breakdown voltage breakdown voltage is reduced. I try to prevent it.

【0022】次いで作成した積層体グリーンブロックを
所定形状に切断し、図1に示すグリーン積層体1を得
る。
Next, the formed green laminate is cut into a predetermined shape to obtain a green laminate 1 shown in FIG.

【0023】その後、グリーン積層体1を所定温度で焼
成し図4に示す焼結体7を作製する。
Thereafter, the green laminate 1 is fired at a predetermined temperature to produce a sintered body 7 shown in FIG.

【0024】次に、焼結体7のバレル研磨を行い、焼結
体7の内部に形成された幅狭内部電極5、及び幅広内部
電極6群の一方の端部を焼結体7のそれぞれの端面に露
出させた後、焼結体7の端部全体を覆うように外部電極
8を形成し、図5に示すような積層コンデンサ9を完成
させた。
Next, barrel polishing of the sintered body 7 is performed, and one end of the narrow internal electrode 5 and the wide internal electrode 6 group formed inside the sintered body 7 Then, an external electrode 8 was formed so as to cover the entire end of the sintered body 7 to complete a multilayer capacitor 9 as shown in FIG.

【0025】このようにして作製した本実施形態の積層
コンデンサ9の3ロットと、従来品の積層コンデンサ4
9の3ロット、各々100個/ロットについて、20℃
の室温中で、測定周波数1MHz、測定電圧1Vrms
で静電容量を測定しその結果を図11に示した。尚試料
の積層コンデンサの電気特性は、公称静電容量が2.0
pF、静電容量許容差±0.25pF、CH特性で、寸
法は長さ2.0mm×幅1.25mm×厚さ0.65mm、内
部に形成した幅広内部電極6は長さ1.25mm×幅0.
45mm、幅狭内部電極5は長さ1.25mm×幅0.15
mmmとした。
The three lots of the multilayer capacitor 9 of the present embodiment thus manufactured and the conventional multilayer capacitor 4
9 lots, each 100 pieces / lot, 20 ° C
In room temperature, measurement frequency 1MHz, measurement voltage 1Vrms
The capacitance was measured by using the method shown in FIG. Note that the electrical characteristics of the sample multilayer capacitor are such that the nominal capacitance is 2.0
pF, capacitance tolerance ± 0.25 pF, CH characteristics, dimensions are 2.0 mm long × 1.25 mm wide × 0.65 mm thick, and the wide internal electrode 6 formed inside is 1.25 mm long × Width 0.
45 mm, narrow internal electrode 5 is 1.25 mm long x 0.15 width
mmm.

【0026】図11に示したように、本発明実施形態の
積層コンデンサの静電容量は、(d)〜(f)のごとく
設計値の2.0pFに極めて近い値で、標準偏差σが
0.054〜0.065と小さいのに対し、従来品は
(a)〜(c)のごとく設計値より3〜5%静電容量値
が小さく、しかも標準偏差σが0.077〜0.096
と大きくなっている。この結果から、本発明実施形態の
ごとく幅広内部電極6と幅狭内部電極5を、セラミック
層2を挟んで交互に複数層積層し、かつ幅狭内部電極5
は幅広内部電極6の幅寸法内で焼結体7の幅方向に不規
則にずらし印刷積層することで、幅狭内部電極5、及び
幅広内部電極6の幅方向の印刷精度が低下しても、電極
間の有効重なり面積が一定となり、設計値通りの静電容
量が得られると共に、焼結体7の外形形状の歪みも小さ
くなり内部構造欠陥のデラミネーションの発生も抑制す
ることができ、工業的に有効な手段となる。
As shown in FIG. 11, the capacitance of the multilayer capacitor according to the embodiment of the present invention is very close to the design value of 2.0 pF as shown in (d) to (f), and the standard deviation σ is 0. Whereas the conventional product has a 3-5% smaller capacitance value than the design value as shown in (a)-(c), and a standard deviation σ of 0.077-0.096.
And has become larger. From this result, as in the embodiment of the present invention, the wide internal electrodes 6 and the narrow internal electrodes 5 are alternately laminated in a plurality of layers with the ceramic layer 2 interposed therebetween.
Is irregularly shifted in the width direction of the sintered body 7 within the width dimension of the wide internal electrode 6 and printed and laminated, so that even if the printing accuracy in the width direction of the narrow internal electrode 5 and the wide internal electrode 6 decreases, In addition, the effective overlapping area between the electrodes becomes constant, the capacitance according to the design value is obtained, the distortion of the outer shape of the sintered body 7 is reduced, and the occurrence of delamination of internal structural defects can be suppressed. It is an industrially effective means.

【0027】[0027]

【発明の効果】以上本発明によれば、積層コンデンサの
内部電極を幅広内部電極と幅狭内部電極の二種類で形成
し、その二種類の内部電極をセラミック層を挟んで上下
に複数層積層することにより、内部電極の幅方向の印刷
精度が低下しても、略設計値通りの静電容量が得られる
と共に、焼結体の外形歪みが小さくデラミネーションの
発生を抑制した積層コンデンサを提供することが可能と
なる。
As described above, according to the present invention, the internal electrodes of the multilayer capacitor are formed of two types, a wide internal electrode and a narrow internal electrode, and the two types of internal electrodes are vertically stacked with a ceramic layer interposed therebetween. Accordingly, even if the printing precision in the width direction of the internal electrode is reduced, a capacitance almost as designed can be obtained, and a multilayer capacitor with reduced external distortion of the sintered body and suppression of delamination is provided. It is possible to do.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の積層セラミックコンデン
サのグリーン積層体の斜視図
FIG. 1 is a perspective view of a green laminate of a multilayer ceramic capacitor according to an embodiment of the present invention.

【図2】同グリーン積層体のA−A断面図FIG. 2 is a sectional view of the green laminate taken along line AA.

【図3】同グリーン積層体の展開図FIG. 3 is a development view of the green laminate.

【図4】同焼結体の斜視図FIG. 4 is a perspective view of the same sintered body.

【図5】同完成品の斜視図FIG. 5 is a perspective view of the completed product.

【図6】従来の積層セラミックコンデンサのグリーン積
層体の斜視図
FIG. 6 is a perspective view of a green laminate of a conventional multilayer ceramic capacitor.

【図7】同グリーン積層体のB−B断面図FIG. 7 is a sectional view of the green laminate taken along line BB.

【図8】同グリーン積層体の展開図FIG. 8 is a development view of the green laminate.

【図9】同焼結体の斜視図FIG. 9 is a perspective view of the same sintered body.

【図10】同完成品の斜視図FIG. 10 is a perspective view of the finished product.

【図11】(a)〜(f)は本発明実施形態品と従来品
の静電容量分布を示す図
FIGS. 11A to 11F are diagrams showing capacitance distributions of a product according to the embodiment of the present invention and a conventional product.

【符号の説明】[Explanation of symbols]

1 グリーン積層体 2 セラミック誘電体層 3 下部無効層 4 上部無効層 5 幅狭内部電極 6 幅広内部電極 7 焼結体 8 外部電極 9 積層コンデンサ DESCRIPTION OF SYMBOLS 1 Green laminated body 2 Ceramic dielectric layer 3 Lower ineffective layer 4 Upper ineffective layer 5 Narrow internal electrode 6 Wide internal electrode 7 Sintered body 8 External electrode 9 Multilayer capacitor

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 素体内部に内部電極とセラミック誘電体
層を交互に複数層積層し、前記内部電極の一方の端部を
前記セラミック誘電体層を挟んで一層おき交互に、前記
素体の対向する異なる端面に露出させ、前記両端面に露
出した内部電極層の端部と電気的に接続するように外部
電極を形成した積層セラミックコンデンサにおいて、前
記内部電極層はセラミック誘電体層を挟んで交互に積層
した幅広内部電極と幅狭内部電極よりなり、幅広内部電
極は素体の一方の端面に、また幅狭内部電極を対向する
もう一方の端面に露出させたことを特徴とする積層セラ
ミックコンデンサの製造方法。
An internal electrode and a ceramic dielectric layer are alternately laminated in a plurality of layers inside a body, and one end of the internal electrode is alternately arranged with the ceramic dielectric layer interposed therebetween so as to be alternately arranged. In a multilayer ceramic capacitor in which external electrodes are formed so as to be exposed to different end faces facing each other and electrically connected to ends of the internal electrode layers exposed to the both end faces, the internal electrode layers are sandwiched between ceramic dielectric layers. A multilayer ceramic comprising a wide internal electrode and a narrow internal electrode alternately laminated, wherein the wide internal electrode is exposed on one end face of the element body and the narrow internal electrode is exposed on the other end face opposite to the ceramic body. Manufacturing method of capacitor.
【請求項2】 幅狭内部電極は積層セラミックコンデン
サの幅方向に、幅広内部電極の両側辺からはみ出さない
範囲内で不規則にずらして配置させたことを特徴とする
請求項1に記載の積層セラミックコンデンサの製造方
法。
2. The device according to claim 1, wherein the narrow internal electrodes are irregularly shifted in the width direction of the multilayer ceramic capacitor within a range not protruding from both sides of the wide internal electrodes. Manufacturing method of multilayer ceramic capacitor.
【請求項3】 幅狭内部電極層を幅広内部電極層より外
層に配置することを特徴とする請求項1または請求項2
に記載の積層セラミックコンデンサの製造方法。
3. The method according to claim 1, wherein the narrow internal electrode layer is disposed outside the wide internal electrode layer.
3. The method for manufacturing a multilayer ceramic capacitor according to item 1.
【請求項4】 最外層の幅狭内部電極外方の無効層の厚
さを、幅広内部電極と幅狭内部電極に挟まれた有効層よ
り厚くすることを特徴とする請求項3に記載の積層セラ
ミックコンデンサの製造方法。
4. The method according to claim 3, wherein the thickness of the ineffective layer outside the narrowest internal electrode of the outermost layer is larger than that of the effective layer sandwiched between the wide internal electrode and the narrow internal electrode. Manufacturing method of multilayer ceramic capacitor.
【請求項5】 幅広内部電極側辺と素体側面までの幅
を、幅広内部電極と幅狭内部電極に挟まれた有効層の厚
みより大きくすることを特徴とする請求項1から請求項
4のいずれか一つに記載の積層セラミックコンデンサの
製造方法。
5. The method according to claim 1, wherein a width between a side of the wide internal electrode and a side surface of the element body is larger than a thickness of an effective layer sandwiched between the wide internal electrode and the narrow internal electrode. The method for manufacturing a multilayer ceramic capacitor according to any one of the above.
JP10208916A 1998-07-24 1998-07-24 Manufacture of laminated ceramic capacitor Pending JP2000040634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10208916A JP2000040634A (en) 1998-07-24 1998-07-24 Manufacture of laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10208916A JP2000040634A (en) 1998-07-24 1998-07-24 Manufacture of laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JP2000040634A true JP2000040634A (en) 2000-02-08

Family

ID=16564251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10208916A Pending JP2000040634A (en) 1998-07-24 1998-07-24 Manufacture of laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JP2000040634A (en)

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