JPH04286107A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPH04286107A
JPH04286107A JP3049505A JP4950591A JPH04286107A JP H04286107 A JPH04286107 A JP H04286107A JP 3049505 A JP3049505 A JP 3049505A JP 4950591 A JP4950591 A JP 4950591A JP H04286107 A JPH04286107 A JP H04286107A
Authority
JP
Japan
Prior art keywords
capacity
capacitance
electrode
internal electrodes
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3049505A
Other languages
Japanese (ja)
Inventor
Wataru Kurahashi
倉橋 渡
Takeshi Iino
飯野 猛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3049505A priority Critical patent/JPH04286107A/en
Publication of JPH04286107A publication Critical patent/JPH04286107A/en
Pending legal-status Critical Current

Links

Landscapes

  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To provide a laminated ceramic capacitor capable of adjusting its capacity without an outside shape in terms of a laminated ceramic capacitor used for various electronic equipment. CONSTITUTION:Out of internal electrodes 5, two and more layers on the upper side are formed as a capacity adjustable electrode 5a in such a fashion that they may be longer or wider than the other layers. In other words, the capacity of the internal electrodes 5 in the stage where no capacity adjustable electrode 5a is installed yet, is designed in such a fashion that its capacity may be slightly smaller that a target capacity value. The capacity under this condition is measured where the capacity, if insufficient, can be controlled by the capacity adjustable electrodes 5a of two layers and more.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は各種電子機器に使用され
る積層セラミックコンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor used in various electronic devices.

【0002】0002

【従来の技術】積層セラミックコンデンサは、小型で大
容量がとれるため、電子チューナ,ビデオテープレコー
ダ,ビデオカメラ等の各種電子機器に利用され、最近需
要が急増している。
2. Description of the Related Art Multilayer ceramic capacitors are small in size and have a large capacity, so they are used in various electronic devices such as electronic tuners, video tape recorders, and video cameras, and their demand has been rapidly increasing recently.

【0003】従来の積層セラミックコンデンサの構造は
、図6および図7に示すように、誘電体セラミック1と
、交互に異なる端部に達する内部電極2とが交互に複数
積層され、上記内部電極2を電気的に接続する両端部に
設けられた外部電極3からなる。図6は長さ方向の断面
図、図7は幅方向の断面図である。このような積層セラ
ミックコンデンサの静電容量(以下容量と呼ぶ)は、誘
電体セラミック1の誘電率と、対向する内部電極2の間
の誘電体セラミック1の厚みと、対向する内部電極2の
電極重なり部の面積と、その積層数とによって決まる。 この容量は、誘電体セラミック1と内部電極2を一体焼
結した時点で決まり、その後の容量調整は不可能であっ
た。
The structure of a conventional multilayer ceramic capacitor is, as shown in FIGS. 6 and 7, in which a plurality of dielectric ceramics 1 and internal electrodes 2 reaching different ends are alternately laminated. It consists of external electrodes 3 provided at both ends to electrically connect. FIG. 6 is a sectional view in the length direction, and FIG. 7 is a sectional view in the width direction. The capacitance (hereinafter referred to as capacitance) of such a multilayer ceramic capacitor is determined by the dielectric constant of the dielectric ceramic 1, the thickness of the dielectric ceramic 1 between the opposing internal electrodes 2, and the electrodes of the opposing internal electrodes 2. It is determined by the area of the overlapping part and the number of layers. This capacity was determined at the time when the dielectric ceramic 1 and the internal electrode 2 were sintered together, and it was impossible to adjust the capacity thereafter.

【0004】容量調整を行う方法としては、容量を目標
値より少し小さめに設計し、焼結後、積層体の表面に面
積可変の容量調整用の電極を設けた構造が提案されてい
る(例えば、実開昭49−70448号公報、実開昭5
3−23535号公報、実開昭55−32027号公報
)。
As a method for adjusting the capacitance, a structure has been proposed in which the capacitance is designed to be slightly smaller than the target value, and after sintering, an electrode for capacitance adjustment with a variable area is provided on the surface of the laminate (for example, , Utility Model Application Publication No. 49-70448, Utility Model Application Publication No. 5
3-23535, Japanese Utility Model Application Publication No. 55-32027).

【0005】[0005]

【発明が解決しようとする課題】しかし、上記のような
構造では、積層セラミックコンデンサの実使用状態を考
えると、積層体の表面にある容量調整用電極を絶縁物で
被覆する必要があった。
[Problems to be Solved by the Invention] However, in the above-described structure, considering the actual usage conditions of the multilayer ceramic capacitor, it is necessary to cover the capacitance adjusting electrode on the surface of the multilayer body with an insulating material.

【0006】このように従来提案されていた容量調整の
方法は、積層セラミックコンデンサの外観形状を変える
ものであり、実装上問題があった。
[0006] As described above, the conventionally proposed capacitance adjustment methods change the external shape of the multilayer ceramic capacitor, which poses problems in terms of mounting.

【0007】本発明はこのような課題を解決するもので
、外観形状を変えることなく容量調整が可能な積層セラ
ミックコンデンサを提供することを目的とするものであ
る。
[0007] The present invention has been made to solve these problems, and it is an object of the present invention to provide a multilayer ceramic capacitor whose capacity can be adjusted without changing its external shape.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に本発明の積層セラミックコンデンサは、誘電体セラミ
ックと、交互に異なる端部に達する内部電極とを交互に
複数積層し、両端部に上記内部電極を電気的に接続する
外部電極を具備し、かつ上記内部電極の内、上層側の2
層以上が容量調整用電極として少なくとも他の層より長
さが短いか、または幅が狭い構成としたものである。
[Means for Solving the Problems] In order to solve the above problems, the multilayer ceramic capacitor of the present invention has a plurality of dielectric ceramics and internal electrodes that alternately reach different ends, and has the above-described structure at both ends. It is equipped with an external electrode that electrically connects the internal electrodes, and the upper two of the internal electrodes are provided with an external electrode that electrically connects the internal electrodes.
At least one layer is shorter in length or narrower in width than the other layers as a capacitance adjusting electrode.

【0009】[0009]

【作用】このような本発明の構成によれば、設計段階で
容量の誤差を認識して設計できることとなる。つまり、
内部電極の内の容量調整用電極を設けない段階での容量
を目的の容量値より少し小さめに設計し、この状態での
実際の容量値を測定し、不足した容量を数層の容量調整
用電極を設けることにより調整可能としたためである。 したがって、外観形状を変えることなく、目標とする容
量値が簡単にして得られることとなる。
[Operation] According to the configuration of the present invention, it is possible to recognize the capacitance error at the design stage and perform the design. In other words,
The capacitance without the capacitance adjustment electrode of the internal electrodes is designed to be slightly smaller than the desired capacitance value, the actual capacitance value in this state is measured, and the insufficient capacitance is used to adjust the capacitance of several layers. This is because adjustment is possible by providing electrodes. Therefore, the target capacitance value can be easily obtained without changing the external shape.

【0010】0010

【実施例】以下、本発明の一実施例について図1および
図2により説明する。図1は本発明にかかる積層セラミ
ックコンデンサの長さ方向の断面図、図2は同じく幅方
向の断面図である。図1,図2において、4は誘電体セ
ラミック、5は上記誘電体セラミック4間に配置された
内部電極で、この内部電極5は交互に異なる端部に達す
る形となっている。また、5aは上層側の内部電極で、
容量調整用電極として働くものであり、2層以上の複数
層設けられている。この容量調整用電極としての上層側
の内部電極5aは、他の層の内部電極5より少なくとも
長さが短いか、または幅が狭い形となっている。6は上
記誘電体セラミック4と内部電極5,5aとが交互に複
数積層された積層体の両端部に設けられた外部電極で、
上記内部電極5,5aを電気的に接続している。
Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a longitudinal cross-sectional view of a multilayer ceramic capacitor according to the present invention, and FIG. 2 is a cross-sectional view of the same in the width direction. In FIGS. 1 and 2, 4 is a dielectric ceramic, and 5 is an internal electrode disposed between the dielectric ceramics 4. The internal electrodes 5 alternately reach different ends. In addition, 5a is an internal electrode on the upper layer side,
It functions as a capacitance adjusting electrode, and is provided with two or more layers. The internal electrode 5a on the upper layer side serving as the capacitance adjusting electrode is at least shorter in length or narrower in width than the internal electrodes 5 in other layers. Reference numeral 6 denotes external electrodes provided at both ends of a laminate in which the dielectric ceramic 4 and internal electrodes 5, 5a are alternately stacked;
The internal electrodes 5 and 5a are electrically connected.

【0011】次に、本発明における容量調整手段を具体
的実施例により説明する。まず、容量規格が270±1
3.5pFの積層セラミックコンデンサを製造するため
に、厚さ25μmの誘電体セラミックシートを長さ16
0mm×幅140mmの形状に裁断し、このシートを1
3枚積層圧着し、その最上層に位置するシート上に、内
部電極の幅1.0mm,同じく長さ3.92mm、印刷
間隔の幅方向0.5mm,同じく長さ方向0.56mm
となる図3の印刷パターンを用いて、パラジウムペース
トからなる内部電極を1層印刷した。図3において、5
は内部電極、7は誘電体セラミックシート、破線8は切
断位置を示す。また、切断ピッチは長さ方向が2.24
mm、幅方向が1.50mmである。次に、同じく厚さ
25μmの誘電体セラミックシート1枚を一番上に上記
内部電極5が印刷された上記13層の積層体上に積層圧
着し、そのシート上に図3の印刷パターンを幅方向に1
.50mmずらして内部電極5を印刷し、以下この操作
を4回繰り返し、内部電極5が交互に異なる端部に達す
るように長さ方向にずらし、5層並列となるようにした
。この積層体を30ブロック作製し、この状態での容量
を調べるため、1ブロックの積層体上に同じく厚さ25
μmの誘電体セラミックシートを18枚積層圧着し、こ
の積層体の総厚み900μmに本圧力をかけ、所定の位
置で長さ2.24mm×幅1.57mmに切断し、13
50℃で焼成した。次に、両端部を研磨紙で削り、イン
ジウム・ガリウム電極を塗布し外部電極とし、容量を5
個測定した。このときの容量の平均値が226.35p
Fであった。
Next, the capacity adjusting means according to the present invention will be explained with reference to specific examples. First, the capacity standard is 270±1
To manufacture a 3.5 pF multilayer ceramic capacitor, a 25 μm thick dielectric ceramic sheet is
Cut this sheet into a shape of 0 mm x width 140 mm, and
Three sheets are laminated and crimped, and on the topmost sheet, the internal electrode has a width of 1.0 mm and a length of 3.92 mm, and the print interval is 0.5 mm in the width direction and 0.56 mm in the length direction.
Using the printing pattern shown in FIG. 3, one layer of internal electrodes made of palladium paste was printed. In Figure 3, 5
7 indicates an internal electrode, 7 indicates a dielectric ceramic sheet, and broken line 8 indicates a cutting position. Also, the cutting pitch is 2.24 in the length direction.
mm, and the width direction is 1.50 mm. Next, one dielectric ceramic sheet with a thickness of 25 μm is laminated and pressed onto the 13-layer laminate on which the internal electrodes 5 are printed on top, and the printed pattern shown in FIG. 3 is printed on the sheet. 1 in direction
.. The internal electrodes 5 were printed with a 50 mm shift, and this operation was repeated four times, and the internal electrodes 5 were shifted in the length direction so as to reach different ends alternately, so that five layers were arranged in parallel. Thirty blocks of this laminate were produced, and in order to examine the capacity in this state, a layer of 25 mm thick was similarly placed on one block of the laminate.
18 μm dielectric ceramic sheets were laminated and pressure-bonded, the main pressure was applied to the total thickness of this laminate of 900 μm, and the sheet was cut into 2.24 mm long x 1.57 mm wide at a predetermined position.
It was fired at 50°C. Next, both ends were ground with abrasive paper, and an indium-gallium electrode was applied to form the external electrode, increasing the capacitance to 5.
Measured. The average value of the capacity at this time is 226.35p
It was F.

【0012】この容量をもとに、他の29ブロックの積
層体に、同じく厚さ25μmの誘電体セラミックシート
1枚を積層圧着し、図4に示すような印刷パターンを用
い、容量調整を行った。図4において、5aは容量調整
用の内部電極である。この容量調整は、容量調整用の第
1層の電極重なり部の面積が、図5(a)に示す下部の
内部電極5の電極重なり総面積の8%(即ち、長さ方向
が約67%、幅方向が約75%)となる容量調整用電極
としての内部電極5aを図3(b)に示すように印刷し
た。さらに、図4の印刷パターンを幅方向に1.50m
mずらして容量調整用電極としての内部電極5aを図5
(c)に示すように印刷する操作を3回繰り返し(この
とき内部電極5aも交互に異なる端部に達するように長
さ方向にずらされる。)、容量調整用電極としての内部
電極5aの4層の重なり部の総面積が、下部の内部電極
5の重なり部の総面積の20%にする。次に、同じく厚
さ25μmの誘電体セラミックシートをその積層体に1
4枚積層圧着し、この積層体の総厚み900μmに本圧
力をかけ、所定の位置で長さ2.24mm×幅1.57
mmに切断し、1350℃で焼成した。次に両端部を削
り、銀ペーストを塗布し、850℃で焼付け外部電極と
した。そして、容量を5個測定した結果、平均値が27
5.83pFであり、目標の容量値が得られた。
Based on this capacitance, one dielectric ceramic sheet having a thickness of 25 μm was laminated and pressure-bonded to the other 29 block stacks, and the capacitance was adjusted using a printed pattern as shown in FIG. Ta. In FIG. 4, 5a is an internal electrode for capacity adjustment. In this capacity adjustment, the area of the electrode overlap part of the first layer for capacity adjustment is 8% (that is, about 67% in the length direction) of the total electrode overlap area of the lower internal electrode 5 shown in FIG. 5(a). , about 75% in the width direction) was printed as shown in FIG. 3(b). Furthermore, the printing pattern in Figure 4 was added 1.50m in the width direction.
Fig. 5 shows the internal electrode 5a as a capacitance adjustment electrode shifted by
As shown in (c), the printing operation is repeated three times (at this time, the internal electrodes 5a are also shifted in the length direction so as to reach different ends alternately), and 4 of the internal electrodes 5a are used as capacitance adjustment electrodes. The total area of the overlapping parts of the layers is 20% of the total area of the overlapping parts of the lower internal electrodes 5. Next, a dielectric ceramic sheet with a thickness of 25 μm was placed on the laminate.
4 sheets were laminated and crimped, and the main pressure was applied to the total thickness of this laminate of 900 μm, and the length was 2.24 mm x width 1.57 mm at the predetermined position.
It was cut into mm pieces and fired at 1350°C. Next, both ends were shaved, silver paste was applied, and external electrodes were baked at 850°C. As a result of measuring the capacity of 5 pieces, the average value was 27
The target capacitance value was 5.83 pF.

【0013】図5は上述したように内部電極5,5aの
重なり部の形状を示しており、(a)は下部の内部電極
5による電極重なり状態、(b)は下部の内部電極5と
容量調整用電極としての内部電極5aとによる電極重な
り状態、(c)は容量調整用電極としての内部電極5a
による電極重なり状態をそれぞれ示す図である。点線は
下側の内部電極の形状を示している。
As described above, FIG. 5 shows the shape of the overlapping portion of the internal electrodes 5 and 5a, in which (a) shows the overlapped state of the lower internal electrode 5, and (b) shows the overlap between the lower internal electrode 5 and the capacitance. Electrode overlap state with internal electrode 5a as an electrode for adjustment, (c) internal electrode 5a as an electrode for capacity adjustment
FIG. The dotted line indicates the shape of the lower internal electrode.

【0014】本実施例では、容量調整用電極としての内
部電極5aにより4層の重なり部の総面積が、下側の内
部電極5の重なり部の総面積の20%である場合を示し
たが、これは容量調整用電極としての内部電極5aの形
状と積層数を変えることにより、広い範囲の容量調整が
可能となる。ここで、容量調整用電極としての内部電極
5aは、2層以上が容量調整用として少なくとも他の層
より長さが短いかまたは幅が狭ければ本来の目的を達成
できるものである。また、下側の内部電極5による容量
形成部が5層の場合を本実施例で示したが、これも1層
以上何層でも可能である。さらに、本実施例では対向す
る内部電極5,5a間にすべて同じ厚みの誘電体セラミ
ックシートを用いたが、厚みの異なるシートを用いても
容量調整用電極としての内部電極5aの重なり面積およ
び積層数を変えることで、容量調整が可能となることは
いうまでもない。
In this embodiment, the total area of the overlapping portion of the four layers due to the internal electrode 5a serving as the capacitance adjusting electrode is 20% of the total area of the overlapping portion of the lower internal electrode 5. By changing the shape of the internal electrode 5a as a capacitance adjusting electrode and the number of laminated layers, it is possible to adjust the capacitance in a wide range. Here, the internal electrode 5a serving as a capacitance adjusting electrode can achieve its original purpose if two or more layers are shorter in length or narrower than at least other layers for capacitance adjustment. Further, although this embodiment shows a case in which the capacitance forming portion formed by the lower internal electrode 5 has five layers, it is also possible to have one or more layers. Furthermore, in this embodiment, dielectric ceramic sheets having the same thickness were used between the opposing internal electrodes 5 and 5a, but even if sheets with different thicknesses are used, the overlapping area of the internal electrodes 5a as capacitance adjusting electrodes and the lamination Needless to say, the capacity can be adjusted by changing the number.

【0015】[0015]

【発明の効果】以上のように、本発明の構成によれば、
外観形状を変えることなく容量調整が可能である。そし
て、設計段階で容量の誤差を認識して設計することで、
誤差が大きく生じた場合でも容量調整が広い範囲で可能
であることは、積層セラミックコンデンサの製造上、実
用的価値は大きい。
[Effects of the Invention] As described above, according to the configuration of the present invention,
Capacity can be adjusted without changing the external shape. By recognizing capacity errors at the design stage,
The ability to adjust the capacitance over a wide range even when a large error occurs has great practical value in manufacturing multilayer ceramic capacitors.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例における積層セラミックコン
デンサの長さ方向の断面図
[Fig. 1] A longitudinal cross-sectional view of a multilayer ceramic capacitor in an embodiment of the present invention.

【図2】同実施例における幅方向の断面図[Figure 2] Cross-sectional view in the width direction of the same example

【図3】同実
施例における下側の内部電極の印刷パターンを説明する
[Fig. 3] A diagram illustrating the printing pattern of the lower internal electrode in the same example.

【図4】同実施例における容量調整用電極としての内部
電極の印刷パターンを説明する図
FIG. 4 is a diagram illustrating the printing pattern of internal electrodes as capacitance adjustment electrodes in the same example.

【図5】(a)は一実施例において下側の内部電極の重
なり状態を説明する図 (b)は同下側の内部電極と容量調整用電極としての内
部電極との重なり状態を説明する図 (c)は同じく容量調整用電極としての内部電極の重な
り状態を説明する図
FIG. 5(a) illustrates the overlapping state of the lower internal electrodes in one embodiment; FIG. 5(b) illustrates the overlapping state of the lower internal electrodes and the internal electrodes serving as capacitance adjustment electrodes; Figure (c) is also a diagram explaining the overlapping state of internal electrodes as capacitance adjustment electrodes.

【図6】従来の積層セラミックコンデンサの長さ方向の
断面図
[Figure 6] Longitudinal cross-sectional view of a conventional multilayer ceramic capacitor

【図7】同じく幅方向の断面図[Figure 7] Similarly cross-sectional view in the width direction

【符号の説明】[Explanation of symbols]

4  誘電体セラミック 5  内部電極 5a  容量調整用電極としての内部電極6  外部電
極 7  誘電体セラミックシート 8  切断位置
4 Dielectric ceramic 5 Internal electrode 5a Internal electrode 6 as a capacitance adjustment electrode External electrode 7 Dielectric ceramic sheet 8 Cutting position

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】誘電体セラミックと、交互に異なる端部に
達する内部電極とを交互に複数積層し、両端部に上記内
部電極を電気的に接続する外部電極を具備し、かつ上記
内部電極の内、上層側の2層以上が容量調整用電極とし
て少なくとも他の層より長さが短いか、または幅が狭い
構成とした積層セラミックコンデンサ。
Claim 1: A plurality of dielectric ceramics and internal electrodes reaching different ends are alternately laminated, and external electrodes are provided at both ends to electrically connect the internal electrodes, and the internal electrodes are connected to each other. A multilayer ceramic capacitor in which two or more of the upper layers serve as capacitance adjustment electrodes and are at least shorter in length or narrower in width than other layers.
JP3049505A 1991-03-14 1991-03-14 Laminated ceramic capacitor Pending JPH04286107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3049505A JPH04286107A (en) 1991-03-14 1991-03-14 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3049505A JPH04286107A (en) 1991-03-14 1991-03-14 Laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH04286107A true JPH04286107A (en) 1992-10-12

Family

ID=12832995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3049505A Pending JPH04286107A (en) 1991-03-14 1991-03-14 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH04286107A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015226026A (en) * 2014-05-29 2015-12-14 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110250A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110251A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015226026A (en) * 2014-05-29 2015-12-14 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110250A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor
JP2018110251A (en) * 2018-02-15 2018-07-12 太陽誘電株式会社 Multilayer ceramic capacitor

Similar Documents

Publication Publication Date Title
US10629376B2 (en) Multilayer ceramic capacitor having side members
JP5332475B2 (en) Multilayer ceramic electronic component and manufacturing method thereof
KR101762032B1 (en) Multi-layer ceramic electronic part and method for manufacturing the same
KR20150031907A (en) Multi-layered ceramic electronic part and board for mounting the same
JP2001185437A (en) Laminated ceramic capacitor
KR20210131241A (en) Multilayer ceramic capacitor
KR20190121145A (en) Multi-layered ceramic capacitor and method of manufacturing the same
KR20220040994A (en) Multilayer ceramic capacitor
JP2001210544A (en) Chip multilayer ceramic capacitor
JPH09153433A (en) Manufacture of laminated electronic component
JP2020027927A (en) Multilayer ceramic capacitor and method of manufacturing the same
JP3306814B2 (en) Manufacturing method of multilayer ceramic electronic component
JP2000340448A (en) Laminated ceramic capacitor
JPH04286107A (en) Laminated ceramic capacitor
JP2000106320A (en) Laminated ceramic capacitor
JP2005327999A (en) Laminated ceramic capacitor
JP2002299149A (en) Laminated ceramic capacitor
JPH11214244A (en) Monolithic ceramic capacitor
JP3266477B2 (en) Manufacturing method of multilayer capacitor
JP2001044059A (en) Multilayer ceramic capacitor
JPH0338812A (en) Laminated capacitor
JP2766085B2 (en) Manufacturing method of laminate
JP2534154Y2 (en) Multilayer ceramic capacitors
JPH0845770A (en) Manufacture of multilayer electronic component
JPH081876B2 (en) Manufacturing method of multilayer capacitor