JPH06333950A - Manufacture of insulated gate field effect semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture an insulated gate semiconductor device which has an excellent switching characteristic and can be used for high frequencies by accelerating the crystallinity of an island-like doped amorphous semiconductor by optical annealing by irradiating the semiconductor with a condensed linear light beam having a specific wavelength and scanning the semiconductor. CONSTITUTION:Light 10 having a wavelength of 250nm to 600nm is condensed into a linear light beam. In addition, an island-line amorphous semiconductor 2 the part of which is shielded by a gate and doped in a P- N-type is formed on a substrate l having an insulating surface. By positioning the semiconductor 2 so that the semiconductor 2 can be irradiated with the linear light beam 10 and, at the same time, scanning the semiconductor 2 in the direction nearly perpendicular to the length direction of the linear light beam 10, the doped amorphous semiconductor 2 is subjected to optical annealing by using the gate 4 as a mask so that the crystallinity of the semiconductor 2 can be accelerated. The linear light beam 10 can be generated by using, for example, a superhigh- voltage mercury lamp, parabolic mirror, and cylindrical quartz lens.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device used in semiconductor integrated circuits, liquid crystal display panels and the like.

[0002]

2. Description of the Related Art In a field effect transistor described in Japanese Patent Laid-Open No. 58-2073, an amorphous semiconductor layer is formed on an insulating substrate, and a source region and a drain region of the amorphous semiconductor layer are formed. By selectively irradiating light and annealing, a polycrystalline region is formed. As a result, the channel formation region is an amorphous region. That is,
In the field effect transistor disclosed in the publication, a part of an amorphous semiconductor region is selectively annealed to obtain a source region and a drain region.

[0003]

In the conventional insulated gate field effect semiconductor device, since the source region and the drain region are selectively annealed, the non-crystallized portion of the non-single crystal semiconductor layer always remains. . When an uncrystallized region remains in the insulated gate field effect semiconductor device as described above, a part of current also flows in this amorphous portion when operating as an insulated gate field effect semiconductor device. . Since the amorphous portion has a higher resistance than the crystallized portion, it is difficult for current to flow, and once it flows in, it accumulates and flows out slowly. That is, the insulated gate field effect semiconductor device in the conventional example has a long lifetime in which a current flows and has a hysteresis characteristic.

The channel forming region in the conventional insulated gate field effect semiconductor device is composed of a non-single-crystal semiconductor layer containing oxygen, carbon and nitrogen in an amount of 1 to 3 × 10 ²⁰ cm ^-3 . . When all of oxygen, carbon, and nitrogen are contained in such a high concentration, the insulated gate field effect semiconductor device has poor “ON” and “OFF” characteristics when switching. For example, in an insulated gate field effect semiconductor device using a non-single-crystal semiconductor containing oxygen, carbon, and nitrogen at such high concentrations as described above, good "ON" and "OFF" The frequency characteristic showing the characteristic is 1KH
It was about z. In order to solve the above problems,
It is an object of the present invention to provide a method for manufacturing an insulated gate field effect semiconductor device, which has good switching characteristics and can be used at high frequencies.

[0005]

(First Invention) In order to achieve the above object, a method for producing an insulated gate field effect semiconductor device according to the present invention comprises a step of linearly collecting light of 250 nm to 600 nm. Forming a semiconductor island-shaped non-single-crystal semiconductor provided on a substrate having an insulating surface and having a P-type or N-type impurity partially shielded by a gate, The non-single-crystal semiconductor is arranged so as to be irradiated with the condensed linear light, and the non-single-crystal semiconductor is scanned in a direction substantially perpendicular to the longitudinal direction of the linear light, so that the P-type or N-type semiconductor is scanned. And a step of photo-annealing a non-single-crystal semiconductor to which impurities are added using the gate as a mask to promote crystallinity.

(Second Invention) A method of manufacturing an insulated gate field effect semiconductor device according to the present invention is 250 nm to 600 nm.
Linearly converging light, a step of arranging the non-single crystal semiconductor on the substrate having an insulating surface to be irradiated with the condensed linear light, and the non-single crystal semiconductor The non-single crystal semiconductor is photo-annealed to promote crystallinity by scanning the condensed linear light in a direction substantially perpendicular to the longitudinal direction and scanning the condensed linear light. It consists of a process and.

[0007]

[Operation] An island-shaped non-single-crystal semiconductor is formed on a substrate having an insulating surface. A part of the non-single crystal semiconductor is shielded by the gate portion, so that P-type or N-type impurities are added. The impurity-added non-single-crystal semiconductor is irradiated with condensed linear light of 250 nm to 600 nm. The condensed linear light is scanned on the non-single crystal semiconductor in a direction substantially perpendicular to the longitudinal direction of the linear light. Upon irradiation with the linear light, the P-type or N-type impurity-added non-single-crystal semiconductor is photo-annealed using the gate as a mask. As a result, the crystallinity of the non-single-crystal semiconductor to which the above impurities are added is promoted.

As described above, according to the present invention, since the source region and the drain region to which the impurities are added are not selectively annealed, all non-single-crystal semiconductor layers other than the channel formation region are promoted to be crystallized. You can That is, in the insulated gate field effect semiconductor device according to the present invention, no amorphous portion having high resistance is left in the source region and the drain region. In addition, since the source region and the drain region do not have an amorphous portion where current hardly flows,
The current easily flows and does not flow during switching. Therefore, the insulated gate field effect semiconductor device of the present invention has a short lifetime in which a current flows and does not have a hysteresis characteristic. That is, the insulated gate field effect semiconductor device of the present invention has a small off-current and "O.
"N" and "OFF" could be performed with a high-speed response.

In the insulated gate field effect semiconductor device of the present invention, each of oxygen, carbon and nitrogen contains 5 × 10 ¹⁸ c.
m ^-3 or less, that is, I in which the above elements are reduced as much as possible
A P-type or N-type impurity is added to the non-single-crystal semiconductor layer, and a source region and a drain region are formed by promoting crystallization of only the region to which the impurity is added. The feature is that hydrogen, or a halogen element is added. The insulated gate field effect semiconductor device having such a structure is a non-single crystal semiconductor in the conventional example, for example, an I-type non-single crystal in which each of oxygen, carbon and nitrogen is 1 to 3 × 10 ²⁰ cm ^−3. While the semiconductor had such a switching characteristic that it could follow the frequency of 1 KHz, a good switching characteristic was obtained even at the frequency of 1 MHz. In the insulated gate field effect semiconductor device, all of oxygen, carbon and nitrogen in the I-type non-single crystal semiconductor layer are 5 × 10 ¹⁸ cm ^−3.
As shown below, all non-single-crystal semiconductor layers except for the channel formation region are formed from a source region and a drain region that promote crystallization by light irradiation, so that the switching characteristics at a higher frequency are improved. .

[0010]

Embodiments FIGS. 1A to 1C are vertical sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention. In FIG. 1, the substrate (1) is made of quartz glass, for example, and has a thickness of 1.1 m as shown in FIG. 1 (A).
m 2 and the size was 10 cm × 10 cm. This board
Silane (SiH ₄ ) plasma CVD (high frequency
At a temperature of 13.56 MHz and a substrate temperature of 210 ° C., a non-single-crystal semiconductor (2) containing an amorphous structure in which hydrogen was added to a concentration of 1 atomic% or more was formed to a thickness of 0.2 μm. Further, a gate insulating film (3) made of, for example, a silicon nitride film was laminated on the upper surface of the non-single crystal semiconductor (2) by a photo CVD method. That is, the gate insulating film (3) is made of disilane (Si
₂ H ₆ ) and ammonia (NH ₃ ) or hydrazine (N
Si ₃ N ₄ was prepared to a thickness of 1000 Å without using a mercury sensitization method by reaction with ₂ H ₄ ) (low pressure mercury lamp containing a wavelength of 2537 Å, substrate temperature 250 ° C.).

Thereafter, the portion except the region (5) forming the insulated gate field effect semiconductor device was removed by the plasma etching method. The plasma etching reaction is CF
The reaction was carried out at room temperature by introducing a reactive gas of ₄ + O ₂ (5%) and applying a frequency of 13.56 MHz to a parallel plate electrode (not shown). On the gate insulating film (3), N ⁺ conductive type microcrystalline or polycrystalline semiconductor was laminated to a thickness of 0.3 μm. An undesired part of the N ⁺ semiconductor film was removed by photoetching using the resist film (6). Then, using the gate portion composed of the resist film (6) and the gate electrode (4) of the N ⁺ semiconductor as a mask, the regions to be the source and the drain are ion-implanted at 1 × 10 ²⁰ cm ^−3. As shown in FIG. 1 (B), phosphorus was added to the concentration of 1 to form a pair of impurity regions (7) and (8).

Furthermore, after the resist film (6) of the gate electrode (4) is removed, the substrate (1) is exposed to strong light (1
The optical annealing of 0) was performed. That is, an ultra-high pressure mercury lamp (output 5KW, wavelength 250 nm to 600 nm, light diameter 15 m
m, length 180 mm), the back side uses a parabolic reflector and a quartz cylindrical lens (focal length 150
cm, the condensing part width 2 mm, and the length 180 mm), the linear irradiation part was constituted. The irradiation surface of the substrate (1) was scanned (scanned) at a speed of 5 cm / min to 50 cm / min with respect to this irradiation portion so that the entire surface of the substrate 10 cm × 10 cm was irradiated with intense light (10). . As a result, the gate electrode (4) was sufficiently polycrystallized by absorbing light because a large amount of phosphorus was added to the gate electrode (4) side. In addition, the impurity region (7),
(8) is the direction of scanning by melting and recrystallization once, that is, the melting and recrystallization are shifted (moved) in the X direction.
Let As a result, the crystal grain size could be increased because a growth mechanism was added as compared with the case where the entire surface was uniformly heated or irradiated with light.

The region polycrystallized by the intense light anneal does not have to extend to the entire region below the impurity regions (7) and (8). In FIG. 1, as indicated by broken lines (11) and (11 '), it is important that only the upper layer part thereof is crystallized and the impurity regions (7) and (8) are activated. further,
Edges (15), (15 ') of its source and drain regions
Are provided so as to enter the channel region side with respect to the ends (16) and (16 ′) of the gate electrode. Then, the channel forming region including the N-type impurity regions (7) and (8), the I-type non-single crystal semiconductor region (2), the junction interfaces (17) and (17 ') is a non-single crystal region in the I-type semiconductor region. It has a hybrid structure composed of a semiconductor and a crystallized semiconductor that enters from an impurity region. The degree of crystallized semiconductor in the I-type semiconductor region is determined by the scanning speed and intensity (illuminance) of the optical anneal.

After the step shown in FIG. 1B, the polyimide resin is coated on the entire surface to a thickness of 2 μm. Then, in the polyimide resin, after the electrode holes (13) and (13 ') are formed,
Aluminum om contact and its lead (1
4) and (14 ') are formed. This second layer lead (14), (1
4 ′) may be connected to the gate electrode (4) when formed. The result of this optical annealing is that the sheet resistance is 4 × 10 ^-3 (ohm cm) ^-1 to 1 × 10 ⁺² (ohm cm) before light irradiation.
It became ^-1 , and the electric conductivity characteristics were improved compared to before the photo-annealing.

FIG. 2 shows a drain current-gate voltage characteristic according to an embodiment of the present invention. When the lengths of the channel forming regions are 3 μm and 10 μm, V _th = + 2V and V _DD = 10V under the condition that the channel width is 1 mm, as indicated by symbols (21) and (22) in FIG. 2, respectively. At 1
Currents of × 10 ^-5 A and 2 × 10 ^-5 A were obtained. Note that the off-state current was (V _GG = 0V) 10 ⁻¹⁰ to 10 ⁻¹¹ (A), which was 10 ⁻⁴ times smaller than 10 ⁻⁶ (A) of the single crystal semiconductor. This embodiment employs a manufacturing process in which a coating film is gradually formed and processed from the lower side, so that large area and large scale integration can be performed. Therefore, a large area such as 30 cm x 30 c
It was possible to fabricate 500 × 500 insulated gate field effect semiconductor devices in a panel of m, and it could be applied as an insulated gate field effect semiconductor device for controlling a liquid crystal display element.

Since it is a low temperature treatment of 400 ° C. or less by the photo-annealing process, it was possible to prevent the polycrystallized or single crystallized semiconductor from releasing hydrogen or halogen element therein. Further, the optical annealing was performed not from the entire surface of the substrate at the same time, but from one end to the other end. For this reason, the light emitted from the cylindrical ultra-high pressure mercury lamp was condensed by the parabolic mirror and the quartz lens into a linear shape. The linearly condensed light was able to optically anneal the surface of the non-single-crystal semiconductor by scanning the substrate in a direction orthogonal to this. Since this optical annealing is performed with ultraviolet rays, crystallization is promoted inward from the surface of the non-single crystal semiconductor. Therefore, the sufficiently polycrystallized or single-crystallized impurity region near the surface can control the current flowing in the channel formation region in the immediate vicinity of the gate insulating film without any trouble.

During the light irradiation annealing step, the hydrogen or halogen element added to the channel formation region is not affected at all, and the state of the non-single crystal semiconductor can be maintained. It can be between 10 ³ and 1/10 ⁵ . Since the source region and the drain region are formed by optical annealing after forming the gate electrode, the characteristics are stabilized without depositing dirt on the interface of the gate insulator.
Further, as compared with the conventionally known method, not only quartz glass but also any substrate such as soda glass and heat resistant organic film can be used as the substrate material. Non-single-crystal semiconductor that constitutes the channel formation region, which is the interface of different materials
The formation of the gate insulator and the gate electrode is characterized by the fact that interface formation is less likely to occur because they can be formed by the process in the same reaction furnace without exposing them to the atmosphere.

In this embodiment, it is important that the oxygen, carbon and nitrogen of the non-single crystal semiconductor in the channel formation region have an impurity concentration of 5 × 10 ¹⁸ cm ^-3 or less. That is, in the conventionally known insulated gate field effect semiconductor device, the channel layer has 1 to 3 ×.
It is mixed at a concentration of 10 ²⁰ cm ^-3 . The P channel type insulated gate field effect semiconductor device using the non-single crystal semiconductor in the conventional example flows only a current which is ⅓ or less of the characteristic of the insulated gate field effect transistor device in this example. The hysteresis characteristic of the insulated gate field effect semiconductor device using the non-single crystal semiconductor in the above-mentioned conventional example has the drain electric field of 2 × 10 5 in addition to the I _DD ─V _GG characteristic.
It was observed when ⁶ V / cm or more was applied. Also,
As in this embodiment, the oxygen in the non-single crystal semiconductor is adjusted to 5 × 10 ^18.
If it is below cm ⁻³ , no hysteresis is observed even at a voltage of 3 × 10 ⁶ V / cm.

[0019]

According to the present invention, linear light is focused, and the entire surface of the substrate is scanned in a direction perpendicular to the longitudinal direction of the linear shape, and is melted and then recrystallized. , The crystal grain size was larger than that of uniformly heating, and the mobility of electrons or holes was improved. According to the present invention, since linear light having a wavelength of 600 nm or 250 nm is condensed, crystallization can be promoted from the surface of the non-single-crystal semiconductor to the inside thereof, and thus channel formation can be achieved. A current also flows very close to the gate insulating film in the region, which facilitates current control. According to the present invention, since light having a short wavelength is irradiated while scanning, the temperature of the light-irradiated portion does not rise and hydrogen or halogen elements are not degassed.

The insulated gate field effect semiconductor device manufactured by the above method has no hysteresis in the source voltage-drain current characteristics and has good switching characteristics at high frequencies. According to the present invention, since the entire I-type non-single-crystal semiconductor layer other than the channel formation region is promoted to be crystallized, the switching characteristics of the insulated gate field effect semiconductor device are further improved even at high frequencies. According to the present invention, since the source region and the drain region are formed by photo-annealing after forming the gate electrode, the characteristics of the insulated gate field effect semiconductor device can be obtained without depositing contaminants on the interface of the gate insulator. Stabilize.

[Brief description of drawings]

1A to 1C are vertical sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention.

FIG. 2 shows drain current-gate voltage characteristics according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Non-single crystal semiconductor 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area | region which forms an insulated gate field effect semiconductor device 6 ... Resist film 7, 8 ... Impurity region 10 ... Strong light 11,11 '... Dashed line 13,13' ... Hole 14,14 '... Lead 15,15' ... Ends of source region and drain region 16, 16 '... Edge of gate electrode 17, 17' ... Bonding interface

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H01L 21/26 L 8617-4M

Claims (2)

[Claims] 1. A process of linearly collecting light of 250 nm to 600 nm, and an island-shaped non-single-crystal semiconductor provided on a substrate having an insulating surface, wherein the gate shields the part. Forming a semiconductor to which a P-type or N-type impurity is added, and arranging the non-single-crystal semiconductor so as to be irradiated with the condensed linear light, and a longitudinal direction of the linear light. Scanning at a substantially right angle with respect to the P-type or N-type impurity-doped non-single-crystal semiconductor by using the gate as a mask to perform photo-annealing to promote crystallinity. And a method for manufacturing an insulated gate field effect semiconductor device. 2. A step of linearly focusing light of 250 nm to 600 nm, and a step of arranging a non-single crystal semiconductor on a substrate having an insulating surface so as to be irradiated with the focused linear light. Scanning the non-single-crystal semiconductor in a direction substantially perpendicular to the longitudinal direction of the condensed linear light; and scanning the non-single-crystal semiconductor by scanning the condensed linear light. A method for manufacturing an insulated gate field effect semiconductor device, comprising: annealing to promote crystallinity.