JPH06319084A - Defect detecting device for solid-state image pickup element and defect correcting device using detecting device - Google Patents

Abstract

PURPOSE:To obtain a defect detecting device capable of accurately detecting a defective picture element, by effectively amplifying only the level of a defect and corresponding also to a solid-state image pickup element having an oscillation correcting function. CONSTITUTION:At the time of detecting a defect, the CCD solid-state image pickup element 3 corresponding to oscillation correction is driven to read out a frame, the generation of a reading pulse XSG is stopped only for a prescribed field and during the stop period, vertical transfer clocks VCL are continuously generated. Thereby a timing generator 5 is controlled by a microcomputer 4, a defective picture element is detected by a defect detecting circuit 9 based upon the image pickup level of the element 3 and the address data of the defective picture element are stored in a RAM 23. A defect correcting pulse DEF is generated based upon the data read out from the RAM 23 and a defect correcting circuit 8 corrects the defect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect detection apparatus for detecting pixel (point) defects of a solid-state image pickup device and a defect correction apparatus using the same, and particularly in field reading (field storage mode) during normal image pickup. The present invention relates to a defect detection device for a driven solid-state image sensor and a defect correction device for the defect detection device.

[0002]

2. Description of the Related Art In a solid-state image pickup device formed of a semiconductor such as CCD, a defective pixel whose sensitivity is lowered due to a local crystal defect of the semiconductor may occur. In such a case,
It is known that image quality deterioration occurs due to the imaging output of the defective pixel. When detecting such defective pixels, conventionally, an expensive device such as an enormous memory or an averaging device is used in the inspection process in manufacturing the solid-state image sensor, and the defective pixel is detected for each solid-state image sensor. The defect data is added before shipment, and it is not automatically detected in the set. Therefore,
It was not possible to deal with pixel defects due to scratches or the like that occur due to some stress factor after shipment.

[0003]

Therefore, in recent years, there has been proposed a defect detection / correction system capable of detecting a defective pixel and correcting the defective pixel even when the defective pixel is incorporated in a device such as a video camera. By the way, since the level of the defect which is usually a problem is very small, the defective pixel cannot be easily detected. When the signal is amplified to increase the detection sensitivity, noise is also amplified. Therefore, it is desired to improve the detection sensitivity by effectively amplifying only the defect level.

In recent years, as one of the methods for correcting camera shake with a video camera, in the case of deriving a solid-state image pickup device having a number of pixels larger than the number of pixels required for normal image pickup, for example, an NTSC TV signal. There is known a method in which a solid-state image sensor compatible with the PAL system is used and a part of the pixel area thereof is used for camera shake correction. In the case of the solid-state image sensor having the image stabilization function, in actual operation, as will be described later in detail, not the normal read drive,
An operation of sweeping out signal charges of unused pixels is performed. Therefore, when detecting defects of this type of solid-state imaging device, the signal charges of some pixels are swept away under the above-mentioned driving conditions, and the information of all pixels cannot be read.

The present invention has been made in view of the above problems, and an object thereof is to detect defective pixels with high accuracy by effectively amplifying only the level of defects.
Moreover, it is an object of the present invention to provide a defect detection device that can be applied to a solid-state image sensor having a camera shake correction function and a defect correction device using the defect detection device.

[0006]

A defect detection apparatus according to the present invention is a solid-state image pickup device comprising photosensors two-dimensionally arranged in a matrix and vertical transfer registers arranged in each vertical column of the photosensors. The readout pulse for reading the signal charge from the photo sensor to the vertical transfer register and the vertical transfer clock for driving the vertical transfer register to vertically transfer the signal charge are generated, and the solid-state image sensor is read by the frame when the defect is detected. A timing generator for driving, a control means for stopping the generation of the read pulse for a predetermined field at the time of defect detection, and a control means for controlling the timing generator so as to continuously generate the vertical transfer clock during the stop period, and an image pickup by the solid-state image sensor. Defect detecting means for detecting a defective pixel based on the output level; It has a configuration that includes a memory for storing the defect data for the defective pixel.

[0007]

In a solid-state image pickup device driven by field reading, which is adopted as a general driving method, when a defect is detected, it is driven by frame reading and defect detection is performed by long-term storage driving. With frame read drive,
The signal charge accumulated in each pixel can be read over two fields without pixel mixing. Therefore, the defect inspection on a pixel-by-pixel basis can be performed in a short time. Moreover, since only the defect level can be amplified by long-term storage, defective pixels can be detected with high accuracy. In addition, in the case of long-time accumulation, by stopping the generation of the read pulse for a predetermined field and continuously generating the vertical transfer clock during this stop period, even in a solid-state image sensor compatible with camera shake correction, Defect inspection can be performed.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention having a digital signal processing configuration applied to a CCD camera, for example. In FIG. 1, a subject is imaged on an image pickup surface of a CCD solid-state image pickup device 3 by an optical system including a lens 1 and an aperture (IRIS) 2. The aperture 2 of this optical system is controlled to be opened / closed by the microcomputer 4 at the time of defect detection / correction described later. The timing generator 5 generates various signals at appropriate timings, reads out signal charges from each pixel (photosensor) in the CCD solid-state imaging device 3 to a vertical transfer register, performs vertical transfer by the vertical transfer register,
This is for driving horizontal transfer by the horizontal transfer register.

FIG. 2 shows a structural example of the CCD solid-state image pickup device 3 having a camera shake correction function. In the figure, a large number of photosensors 31 arranged two-dimensionally in a matrix,
The image pickup section 34 is configured by a plurality of vertical transfer registers 33 arranged in each vertical column of the photosensors 31 and vertically transferring the signal charges read through the read gate 32. The signal charges read to the vertical transfer register 33 are sequentially transferred to the horizontal transfer register 35 in units corresponding to one scanning line. The signal charges for one scanning line are sequentially transferred in the horizontal direction by the horizontal transfer register 35 and supplied to the charge detection unit 36.

The charge detection section 36 is composed of, for example, a floating diffusion amplifier, detects the signal charge transferred by the horizontal transfer register 35, converts it into a signal voltage, and outputs it as a TV signal. The horizontal transfer register 35 is continuously provided with an unnecessary charge discharging gate 37, and further, the unnecessary charge discharging gate 37 is continuously provided with an unnecessary charge discharging drain 38 for discharging charges in the horizontal transfer register 35. . The potential of the unnecessary charge discharging drain 38 becomes sufficiently deep,
A voltage is applied so that the charges existing in the horizontal transfer register 35 can flow in when the unnecessary charge discharging gate 37 is opened.

From the timing generator 5 described above, a read pulse XSG for reading out the signal charge accumulated in the photosensor 31 of the CCD solid-state image pickup device 3 to the vertical transfer register 33, and the signal charge read out by this read pulse XSG is vertically added. Vertical transfer clock VCL to be transferred
K, a horizontal transfer clock HCLK for horizontally transferring the signal charges transferred to the horizontal transfer register 35, a drain pulse SG for controlling on / off of the unnecessary charge discharging gate 37, and a switch pulse SP for controlling on / off of a switch 39 described later. Various timing signals, etc., are appropriately generated.
The switch 3 is provided between the output line of the charge detector 16 and the ground.
9 and the resistor 40 are connected in series. This switch 3
9 is normally in the off (open) state, and the switch pulse S
When P is applied, it is turned on (closed) to bring the output line to the ground level.

As the CCD solid-state image pickup device 3 for image stabilization having the above-mentioned structure, one having an image pickup area larger than the range shown on the screen, for example, in the case of deriving a TV signal of NTSC system, one of NTSC system is used. Also, a PAL system compatible with a large number of lines is used. Then, for example, when correcting the shake in the vertical direction, the signal charges of the upper and lower unnecessary portions of the image pickup unit 34 are transferred to the high-speed vertical transfer clock VCLK.
The high-speed transfer is carried out, and the unnecessary charges are discharged to the unnecessary charges discharging drain 38 through the unnecessary charges discharging gate 37 to use only the signal charges of the line corresponding to the NTSC system. That is, by moving the upper and lower unnecessary portions based on the motion data according to the amount of camera shake (the detection mechanism is not shown) that occurs during imaging, the blur of the surface reflected on the CCD solid-state image sensor 3 is absorbed. As a result, camera shake correction is realized.

The image pickup output of the CCD solid-state image pickup device 3 is S /
After passing through the H (sample / hold) & AGC (automatic gain control) circuit 6, it is A / D converted by the A / D converter 7 and supplied to the defect correction circuit 8 and the defect detection circuit 9 as, for example, 10-bit data. The image pickup output whose defect has been corrected by the defect correction circuit 8 is subjected to various kinds of signal processing by the signal processing circuit 10 to be output as a luminance (Y) signal and a chroma (C) signal. Become.

The defect detection circuit 9 detects the defective pixel by comparing the image pickup output level of the CCD solid-state image pickup device 3 in a frame read drive with a predetermined detection level, and a comparator 21 based on the detection output of the comparator 21. Address detection conversion circuit 22 for specifying the address of the defective pixel and converting the address in the frame read drive into the address in the field read drive, and the address data provided by the address detection conversion circuit 22 in odd and even numbers. RAM23 for each field
It consists of and. The read address from the RAM 23 is supplied to the correction pulse generation circuit 12. The correction pulse generation circuit 12 generates a defect correction pulse DEF at a timing according to the read address from the RAM 23 and supplies it to the defect correction circuit 8.

By the way, normally, the defective pixels of the CCD solid-state image pickup device 3 are present in units of one pixel. When the CCD solid-state image pickup device 3 is operated in the field reading drive (field storage mode) which is adopted as a general drive system, the signal charges of the photo sensor 31 accumulated for one field period are adjacent in the vertical direction. The two pixels are mixed and output. Therefore, the signal charges of all pixels are read out for each field, and the defect of one pixel is output over two fields by changing the line. Therefore, the defect correction requires correction of two fields for one pixel.

For this reason, when attempting to detect a defect by the field read drive, the inspection over two fields is required. That is, in the field read drive, all pixels are read out for each field. Therefore, in order to amplify the defect level by extending the accumulation time of the signal charges in each pixel, the accumulation operation is required for each field. The time is simply calculated twice, and the time required for defect detection becomes long. FIG. 3 is a timing chart of field read driving, (A)
Shows the case of normal operation, and (B) shows the case of long-term storage.

In FIG. 3, VD is a vertical synchronizing signal of an NTSC TV signal, FLD is an (EVEN / ODD) discrimination signal, and XS.
G is a read pulse for reading the signal charge from each pixel, ST / SP is a defect detection start / stop signal (starting rising, stopping falling), VCLK is a vertical transfer clock, S / H OUT is a CCD solid-state image sensor Sample hold output of 3 imaging output, W pulse is defect detection pulse, DE
F indicates each defect correction pulse. In the sample-hold output S / H OUT, the pulse a represents a defect output with a small level, and the pulse b represents a defect output with a large level.

By the way, in the system for image stabilization, in the normal read operation, only the signal charges of the pixels of NTSC are read out as described above. Therefore, all the pixels to be used, in this example, all the pixels of PAL are read. The inspection will not be possible. Therefore, in the present invention, the CCD solid-state image pickup device 3 is set to the frame read drive (frame accumulation mode) and read at the time of defect detection so that the defect detection does not take time and can be applied to a system corresponding to the camera shake correction. Pulses XSG1, XSG2 and vertical transfer clock V
The timing of CLK is controlled. Figure 4
A timing chart in the case of frame read drive is shown in FIG. In the figure, (A) shows the case of normal operation,
(B) shows the case of normal long-time accumulation, and (C) shows the case of long-time accumulation in response to camera shake.

As is clear from FIG. 2C, at the time of camera shake correction, it is necessary to read out the signal charges for the number of pixels in the PAL system, so it is necessary to read out the signal charges in one field over two fields. I understand. Therefore, in order to read out the signal charges of both odd (ODD) and even (EVEN) fields, for example, in the case of the example of FIG.
Since the field immediately after the reading of the odd field becomes the odd field again, the reading of the even field is performed from the fourth field after the odd field, so that it takes a total of 5 fields. Further, the read timing of each field signal at that time is shifted by a time corresponding to three fields.

Therefore, in order to make the signal charge storage time of each field uniform, it is necessary to shift the storage start timing in advance in accordance with the read timing, and therefore the storage start timing is shifted by three fields. . From this, the number of fields accumulated in the ground is n
Then, the total detection time in the frame read driving is n + 5 fields. In such reading of the drive timing, the detection of the defective pixel and the storage of the address thereof can be finished regardless of the field at the start of the defect detection. That is, only the fields at the end are different, and it does not matter which field is later stored in the defective data.

In this driving method, when the timing for stopping the reading of the signal charges is designated by the number of pulses of the vertical synchronizing signal VD, the reading pulse XSG is stopped by ST / SP.
The number of counts of the vertical synchronizing signal VD after the rise of the signal (START) may be performed at the following timing. That is, the read pulse XSG to be stopped is 1, 3 to n-2,
It becomes n, n + 1, n + 3. Here, the number of accumulated fields n is a value arbitrarily determined from the setting of the detection accuracy and the detection lower limit. In addition, while the read pulse XSG is stopped,
The vertical transfer clock VCLK is a continuous pulse without being modulated during vertical blanking.

The above-described defect detection operation in the frame read drive is timed by the microcomputer 4 so that the generation of the read pulse XSG is stopped at the above timing and the vertical transfer clock VCLK is continuously generated during this stop period. It is realized by controlling the generator 5. As described above, by performing the defect detection by the frame read drive, the detection time can be significantly shortened as compared with the case of the field read drive. FIG. 5 shows a timing chart when, for example, 10 frames (20 fields) are stored. In the same figure, (A) shows a case of normal long-time accumulation, and (B) shows a case of long-time accumulation corresponding to camera shake. In the case of FIG. 6B, the total detection time is 20 fields + 5 in the frame read drive.
It only takes time in the field. On the other hand, in the field read drive, since the storage operation is required for each field,
The accumulation time simply takes twice as long.

Next, the algorithm for defect detection and defect correction according to the present invention will be described with reference to the flowchart of FIG. When the power of the CCD camera is turned on, the microcomputer 4 first closes the diaphragm 2 and then the CCD solid-state image sensor 3
A black state is set in which no light is incident on (step S1), and then the CCD solid-state imaging device 3 is driven by frame reading (step S2). Then, the read pulses XSG1 and XSG2 generated from the timing generator 5 for the CCD solid-state image sensor 3 are stopped (step S).
3). As described above, by stopping the read pulses XSG1 and XSG2, as is apparent from the timing chart of FIG. 4B, signal charges can be accumulated in each photosensor 31 for a long time, so that a pixel defect signal is substantially generated. Since amplification is possible, defective pixels can be detected with high accuracy.

Next, the image pickup output of the CCD solid state image pickup device 3 is inputted as an inspection signal to the comparator 21 of the defect detection circuit 9 (step S4). In the defect detection circuit 9,
The defective pixel is detected by the comparison output of the comparator 21 when the image pickup output level of the CCD solid-state image pickup device 3 becomes equal to or higher than a predetermined detection level (step S5), and then the address of the defective pixel is detected by the address detection conversion circuit 22. At the same time, the line address in the frame read drive is converted into the line address in the field read drive (steps S6 and S7), and the line address data is stored in the RAM 23 (step S8). From the above,
A series of processes for defect detection in the frame read drive is completed.

After the series of processes for defect detection is completed, when the normal image pickup mode in which defect correction is required is performed (step S9), the timing generator 5 reads the CCD solid-state image pickup device 3 in the field by the control of the microcomputer 4. Drive (step S10). In this field read driving state, the address data of the defective pixel is read from the RAM 23 and given to the correction pulse generation circuit 12 (step S11). The correction pulse generation circuit 12 generates a defect correction pulse at the timing given by the read data from the RAM 23 (step S1).
2) Supply to the defect correction circuit 8.

The defect correction circuit 8 specifies the image pickup output of the defective pixel in the CCD output by this defect correction pulse, and replaces the image pickup output of the defective pixel with the pixel output of the previous pixel, for example. Correction is performed (step S13). Then, it is determined whether or not the lens diaphragm 2 is opened (step S14). If it is not opened, the lens diaphragm 2 is opened and light is incident on the CCD solid-state image sensor 3 (step S15), and the normal imaging mode is set. enter. Or later,
The above-described series of defect correction processing is repeatedly executed until the imaging mode ends.

As described above, when the defect is detected, the CCD solid-state image pickup device 3 is driven by frame reading and by storing for a long time. In the frame reading driving, the signal charge accumulated in each pixel is spread over two fields. Since it is possible to read out without pixel mixture, defect inspection in pixel units can be performed in a short time, and since only the defect level can be amplified by long-term accumulation, defective pixels can be accurately detected. Further, when the read pulse XSG is stopped for a predetermined field during long-term storage and the vertical transfer clock VCLK is continuously generated during this stop period, the CCD solid-state image sensor 3 is capable of image stabilization. Defect inspection can be performed on all pixels, even if they are the same.

In the above embodiment, the case where the present invention is applied to the CCD solid-state image pickup device 3 compatible with camera shake correction has been described, but the present invention can also be applied to this type of CCD solid-state image pickup device. The present invention is not limited to the above, and can be applied to a normal CCD solid-state image pickup device as well.
Pixel defects can be detected by the same operation regardless of whether it is compatible with the TSC system or the PAL system. Further, although the case where the signal processing system in the CCD video camera is configured digitally has been described in the above embodiment, the present invention is not limited to this, and the present invention is also applied to the case where it is configured analogically. I will get it.

Further, in the case where the timing generator 5 is configured to generate all the timing signals based on the vertical synchronizing signal VD, it is desired to stop the generation of the read pulse XSG with respect to the vertical synchronizing signal VD input to the timing generator 5. Even if the portion is blanked, the drive operation for defect detection similar to that in the above embodiment can be realized.

[0030]

As described above, according to the present invention,
In a solid-state imaging device driven by field readout, which is adopted as a general drive method, when a defect is detected, it is driven by frame readout and also by long-term storage. Since the accumulated signal charges can be read out over two fields without pixel mixture, defect inspection in pixel units can be performed in a short time, and only the defect level can be amplified by accumulation for a long time. The defective pixel can be detected with high accuracy.

Further, during the long-time storage driving, the generation of the read pulse is stopped for a predetermined field and the vertical transfer clock is continuously generated during this stop period. Even in
Defect inspection can be performed on all pixels. Further, since it can be easily realized only by controlling the timing of the read pulse and the vertical transfer clock, it can be easily applied to the existing camera system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention of a digital signal processing configuration applied to a CCD camera.

FIG. 2 is a block diagram showing a configuration example of a CCD solid-state imaging device compatible with camera shake correction.

3A and 3B are timing charts at the time of field read driving, in which FIG. 3A shows a case of normal operation, and FIG. 3B shows a case of camera shake response and long-time storage.

4A and 4B are timing charts during frame read driving, in which FIG. 4A is a case of normal operation, FIG. 4B is a case of normal long-time accumulation, and FIG. 4C is a case of long-time accumulation for camera shake. Are shown respectively.

FIG. 5 is a timing chart when 10 frames (20 fields) are accumulated, (A) shows a case of normal long-term accumulation, and (B) shows a case of long-term accumulation in response to camera shake.

FIG. 6 is a flowchart showing an algorithm for defect detection and defect correction according to the present invention.

[Explanation of symbols]

 3 CCD solid-state image sensor 4 Microcomputer 5 Timing generator 8 Defect correction circuit 9 Defect detection circuit 12 Correction pulse generation circuit 21 Comparator 22 Address detection conversion circuit 23 RAM

Claims (4)

[Claims] 1. A solid-state imaging device comprising photosensors arranged two-dimensionally in a matrix and vertical transfer registers arranged in each vertical column of the photosensors, wherein signal charges are transferred from the photosensors to the vertical transfer registers. A timing generator for generating a read pulse for reading and a vertical transfer clock for driving the vertical transfer register to vertically transfer signal charges, and driving the solid-state imaging device by frame reading at the time of defect detection, and defect detection. Occasionally, the generation of the read pulse is stopped for a predetermined field, and the control means controls the timing generator to continuously generate the vertical transfer clock during this stop period; and a defect based on the image output level of the solid-state image sensor. Defect detecting means for detecting a pixel, Defect detection apparatus characterized by comprising a memory for storing the defect data of are. 2. The defect detecting apparatus according to claim 1, wherein the solid-state image sensor has a camera shake correction function. 3. A defect correction device using the defect detection device according to claim 1 or 2, wherein the correction pulse generation means generates a defect correction pulse at a timing given by the defect data read from the memory, A defect correction device, comprising: a defect correction means for performing defect correction on an image pickup output of the solid-state image pickup device in response to a defect correction pulse. 4. The defect correction apparatus according to claim 3, wherein the timing generator drives the solid-state imaging device by field reading during normal imaging.