JPH0698227A - Variable system clock type digital electronic still camera - Google Patents

Abstract

PURPOSE:To provide a variable system clock type digital electronic still camera which can reduce the noises of quantization caused by the A/D conversion and the signal interference caused between the sensors and then can ensure the high picture quality even at a low illuminance by securing such a circuit constitution that can reduce the clock frequency or can increase the clock cycle even at a low illuminance of an object. CONSTITUTION:The image of an object is inputted to a signal processing circuit 8 via an image pickup system, a CDS circuit 5, an A/D converter 7, etc. A system control CPU 13 decides whether the object has a low illuminance or not according to a fact whether the level of the luminance signal supplied from the circuit 8 is higher than a prescribed level or not. If a low illuminance is confirmed, the system clock outputted from a synchronizing signal/timing signal generating circuit 11 is controlled so that the system clock has the frequency lower than that of an NTSC system. Furthermore a CCD driving circuit 10, the converter 7, and the driving circuit of a liquid crystal display 17 can operate in a normal way in response to the system clock of the low frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital electronic still camera using a solid-state image pickup device having a single-plate or double-plate structure, and more specifically, the frequency of a system clock is set freely in order to improve image quality in low illuminance. The present invention relates to a digital electronic still camera that can be changed to.

[0002]

2. Description of the Related Art A digital electronic still camera has been actively proposed, and a single-plate or double-plate image pickup device is used in an image pickup portion of the electronic still camera in order to reduce costs. Since the sensor array of this image sensor has a structurally limited plane, color filters for detecting color components are arranged in the horizontal direction. As a result, the resolution obtained from the total number of sensors is lower than that of a method in which light is hierarchized in the light incident direction, that is, the vertical direction like the photosensitive portion of a silver salt film. However, in order to suppress the cost increase of the device, a configuration in which the number of image pickup devices and A / D converters per device is one is generally adopted. In such a case, for example, in a primary color type single-chip image sensor, color filters are arranged in a checkered pattern on the entire surface of each sensor, a video signal corresponding to the color filter is taken out, and converted into a luminance signal and a color difference signal by a signal processing circuit. There are many types of digital electronic still cameras. When the sensor output of the image pickup device is converted into a digital signal, the signals are output from each sensor in an array of, for example, GRGBGRGB ..., Therefore, the A / D conversion is sequentially digitally converted in time. Therefore, GRGB ...
The Nyquist frequency becomes equal to the sample frequency corresponding to the scanning speed of the sensor, and aliasing distortion occurs, and there is a problem that color signals are mixed due to interference between GRGB signals. It was Especially when the illuminance of the subject is low, the image quality is extremely deteriorated.

[0003]

Therefore, in order to reduce the cost of the system, it is required to realize a circuit configuration with good performance even if the number of image pickup devices and A / D converters used per device is one. The present invention meets the above-mentioned demands, and its purpose is to:
In a digital electronic still camera using a single-plate type or two-plate type image pickup device, even if the illuminance of the subject is low, the circuit configuration is such that the clock frequency can be low, that is, the clock cycle can be lengthened, so that a quantum at the time of A / D conversion can be obtained. It is an object of the present invention to provide a system clock variable digital electronic still camera that can reduce noise, reduce signal interference between sensors, and obtain good image quality even in low illuminance.

[0004]

In order to achieve the above object, a system clock variable type digital electronic still camera according to the present invention is a digital electronic still camera using a solid-state image pickup device having a single-plate or two-plate configuration. And a digital signal processing circuit for outputting the level of the illuminance of the subject, and an NTS.
In addition to the C system clock, a system clock oscillator circuit capable of outputting a clock having a lower frequency than this system clock, and a capacity switching circuit are provided so as to operate properly with respect to the variable processing time associated with the variable system clock. And a digital liquid crystal drive circuit that synchronizes with a clock output from the system clock oscillator circuit, a digital liquid crystal drive circuit that synchronizes with a clock output from the system clock oscillator circuit, and a display using the digital liquid crystal drive circuit. The level of the illuminance of the subject output by the driven liquid crystal display device for monitoring and the digital signal processing circuit is determined, it is determined that the level is lower than a predetermined value, and the still subject is determined based on the setting of the photographing mode setting circuit. If it is determined that the system clock oscillation circuit outputs The lock frequency is changed so as to be smaller than the system clock frequency, and the A / D converter, the solid-state image sensor drive circuit, the digital liquid crystal drive circuit, and the CDS circuit are driven in accordance with the changed clock. And a control means for controlling as described above.

[0005]

According to the above construction, the level of the video signal is detected to determine that the illuminance of the subject is low, and in this state, the means for increasing the system clock period is used to store the accumulation time even for the subject of low illuminance. A good image is obtained by the increase of the video signal component (increased sensitivity) and the noise suppression effect by the reduction of interference between signals between sensors.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 is a schematic diagram for explaining the structure of a single-plate solid-state image sensor used in a digital electronic still camera according to the present invention, and FIG. 2 is a timing chart for explaining the operation of this solid-state image sensor. First, the structure of the solid-state image sensor will be described with reference to FIGS. 1 and 2. Light receiving sensors 31 and 32 corresponding to the total number of pixels on the frame screen are arranged in a matrix. These light receiving sensors are composed of photodiodes. Of these, the light receiving sensor 31 accumulates the signal charges corresponding to the first field of the frame scanning, and the light receiving sensor 32 accumulates the signal charges corresponding to the second field. On the front surface of these light receiving sensors, for example, G vertical stripes, R and B checkered color filters for obtaining the G, R and B primary color luminance signals are arranged as shown in the figure.

A signal reading gate (readout gate) 34 is provided between each light receiving sensor and the vertical transfer portion 33. These signal read gates 34 open their gates all at once at the timing of a read pulse input from a drive circuit (not shown), and transfer the signal charges accumulated in the light receiving sensors 31 and 32 to the vertical transfer unit 33. ing. The signal charges transferred to the vertical transfer unit 33 are sequentially transferred in the vertical direction (downward in the drawing) by the vertical drive pulses φV1 to φV3 supplied from the drive circuit, and the horizontal transfer unit 3
Enter 5. The signal charge that has entered the horizontal transfer portion 35 is further supplied with a horizontal drive pulse φH1 supplied from the drive circuit,
The signal is sequentially transferred in the horizontal direction (to the left in the drawing) by .phi.H2 and is output via the floating diffusion amplifier 36.

Next, the operation of the solid-state image sensor will be described. During the charge storage time, a signal charge proportional to the intensity of incident light is stored in each light receiving sensor. When the time T _V (1/60 seconds) for one field elapses and the next vertical synchronizing signal arrives, the timing generator (not shown) outputs the second read pulse P _R2 to the drive circuit. As a result, the potential barrier of the signal read gate 34 is lowered, and the signal charges 37 accumulated in all the light receiving sensors 31 and 32 are simultaneously transferred to the electrodes forming the vertical transfer unit 33. Then, the signal charge 3 transferred to each electrode
7 are sequentially transferred to the horizontal transfer section 35 by the vertical drive pulses φV1 to φV3. In the horizontal transfer section 35, the signal charges are sequentially transferred in the horizontal direction by the horizontal drive pulses φH1 and φH2. Then, the video signal is output via the floating diffusion amplifier 36.

FIG. 3 shows an embodiment of the present invention and is a schematic configuration diagram of a digital electronic still camera using the single-plate solid-state image pickup device. Reflected light from a subject (not shown) passes through the lens 1, the iris 2, and the optical filter 3 to C
It is imaged on CD4. From the output signal photoelectrically converted by the CCD 4, a noise component induced by a clock or the like is removed by the CDS circuit 5. This signal is further input to the gamma correction circuit 6, nonlinearly amplified and gamma corrected.
The gamma-corrected signal is converted into a digital signal by the A / D converter 7, and the parallel digital signal is converted into a signal processing circuit 8.
Sent to. The signal processing circuit 8 converts the luminance signal and the color difference signal. The memory control circuit 15 controls writing and reading with respect to the memory card 16. When a writing instruction is received from the system control CPU 13 via the memory interface 14, the signal from the signal processing circuit 8 is designated by the memory card 16. Record in the address area. When the release 12 is pressed and a photographing instruction signal is input, the system control CPU 13 issues a writing instruction to the memory control circuit 15.

The signal processing circuit 8 sends the level signal of the luminance signal to the system control CPU 13. The system control CPU 13 determines whether or not the subject has a brightness higher than a predetermined level. When the brightness is higher than the predetermined level, the system control CPU 13 instructs the sync signal timing signal generation circuit 11 to use the NTSC system 14.3.
Outputs the MHz system clock. When the brightness is lower than a predetermined level, a clock having a frequency lower than that of the system clock is output. When the display unit is a CRT, it is designed by the scanning of the NTSC system, and since the original image cannot be reproduced by the scanning of the electron beam, the liquid crystal display 17 is used as the display device. As a matter of course, the circuit for driving the liquid crystal display 17 is composed of a synchronous drive circuit that can correctly reproduce an image even if the system clock changes. Images before and after shooting can be monitored on the liquid crystal display 17. Other circuits are also configured to operate in synchronization with the system clock. That is, the system clock has a frequency (14.
Naturally, it operates at 3 MHz), but each circuit is configured to operate normally even when the system clock changes. In particular, if the circuit itself is a digital circuit, it is easy to handle it if it is a synchronous type circuit. For example, it is an A / D converter or the like. However, in the analog circuit section, it is necessary to consider the correspondence.

The circuit considered in this way is the CDS circuit 5. FIG. 4 is a circuit diagram showing an embodiment of the CDS circuit. The signal from the CCD 4 is input to the base of the transistor 29, which is emitter-follower-coupled, and the limiter circuit 21 suppresses an excessive signal. In the sample and hold circuits 22, 23 and 24, the unnecessary signals of the reset signal and noise included in the CCD output signal are subtracted by the sample signals of φ1 and φ2, and the output of the CDS circuit, that is, V _{OUT of the} differential amplifier 25 is subtracted. , A video signal component corresponding to the brightness of the subject is extracted. If the system clock becomes longer in this sample hold circuit, φ1,
Since the interval between the φ2 sample signals becomes long, the voltage of the sample hold decreases. In order to avoid this, the control signal V received from the system control CPU 13
_{At CT} , the analog SW circuit (capacitance switching circuit) 26 is turned on to add the electric capacity Ch '. This prevents the sample-and-hold voltage from dropping and improves the reduction of the video signal component.

FIG. 5 is a circuit diagram showing details of the CCD drive circuit, the synchronization signal timing signal generation circuit and the LCD. The synchronization signal timing signal generation circuit 11 includes an oscillator control circuit 11a that controls the oscillation circuit under the instruction of the system control CPU 13, an oscillator 11b that generates a variable system clock by the oscillator control circuit 11a, and a timing generation circuit 11c that outputs a timing signal. It consists of and. The CCD drive circuit 10 is composed of a horizontal drive circuit 10a and a vertical drive circuit 10b which generate timing control signals for driving the image pickup device. The liquid crystal display 17 is composed of a synchronous LCD drive circuit 17a and a liquid crystal section 17b.

FIG. 6 is a diagram showing the structure of a synchronous LCD drive circuit. Control signals from the horizontal drive circuit 10a, the timing generation circuit 11c, and the vertical synchronization signal are applied to the signal electrode drive circuit 39 and the scan electrode drive circuit 40. The video amplifier 38 has a D / A converter inside, and the digital data is converted into an analog signal and amplified to an appropriate level. The amplified data is applied to the analog switch 41, and when the output terminal voltage of the signal electrode drive circuit 39 is input to the analog switch 41, the video signal is output to the output terminal X-1 of the analog switch 41. When the output terminal Y-1 of the scan electrode drive circuit 40 is output at this timing, the gate of the TF transistor 42 becomes active, and the video signal is applied to the liquid crystal cell 43 corresponding to one pixel. The transparency of the liquid crystal changes depending on the magnitude of this signal,
A reproduced pattern is obtained by generating a brightness pattern on the liquid crystal screen. Reference numeral 44 denotes the electric capacity of the liquid crystal cell, which functions to store the video signal for one field period. When each output of the signal electrode drive circuit 39 and the scan electrode drive circuit 40 is sequentially output, each TF transistor whose signal terminal intersects is turned on, and the image captured from the CCD is reproduced on the liquid crystal display device.

The capacitance 44 of the liquid crystal cell is set to one cycle even if the scanning period of one field is changed from 1/60 seconds to 1/30 seconds by the system control CPU in order to increase the sensitivity when photographing a dark subject. The electric capacity is large enough to hold the analog video signal within the time. Since the synchronous LCD drive circuit is configured in this way, the liquid crystal display can display the image of the subject without being disturbed even if the system clock deviates from the frequency of the NTSC system.

FIG. 7 is a diagram for explaining the operation sequence of the digital electronic still camera according to the present invention. The photographer sets the mode by the photographing mode setting circuit 18 before starting the photographing. The shooting mode is either a mode for a fast-moving subject (sport mode) or a mode for a relatively slow-moving subject. The system control CPU 13 determines that the mode is the sports mode (ST
1), the CCD 4 is controlled to be a high-speed shutter (ST2), and the synchronization signal timing signal generation circuit 1
1 is controlled to generate an NTSC system clock (ST3). On the other hand, if it is determined in ST1 that the mode is not the sports mode, then it is determined whether or not the mode is slow motion (ST4). In the slow-moving mode, the CCD 4 is controlled so as to have a medium-speed shutter (S
At T5), the sync signal timing signal generation circuit 11 is further controlled to generate an NTSC system clock (ST6). If it is determined in ST4 that the slow-moving mode is not set, it is determined that the subject is a still subject (S
T7). Next, it is determined whether or not the subject is darker than a predetermined value based on the level signal of the luminance signal from the signal processing circuit 8 (S
T8).

When the subject is darker than the predetermined value, the system control CPU 13 controls the oscillation circuit of the sync signal timing signal generation circuit 11 so as to lengthen the clock cycle (ST9). As a result, the time of one frame is T =
(1/30 seconds) × N. However, N is an integer. In the case of fine exposure control, N = 2 ⁿ (EV) may be selected. If the subject is not darker than the predetermined value, ST3
The clock is set in the NTSC system as in the case of 6 (ST1
0). As described above, the frequency of the system clock is determined and shooting is performed (ST11).

[0017]

As described above, the present invention has a circuit configuration in which the frequency of the system clock can be freely changed, and even in the case of a subject with low illuminance, by lowering the clock frequency, that is, increasing the clock cycle, There is an effect that a high-quality image can be obtained by the effect of increasing the sensitivity due to the increase of the accumulation time, reducing the quantization noise at the time of A / D conversion, and reducing the interference between signals between the sensors.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a primary color type image sensor.

FIG. 2 is a waveform diagram of a video signal from the image sensor of FIG.

FIG. 3 is a circuit block diagram showing an embodiment of a digital electronic still camera according to the present invention.

[Fig. 4] CD compatible with a system clock variable
It is a circuit diagram which shows the Example of S circuit.

FIG. 5 is a circuit diagram showing details of a CCD drive circuit, a synchronization signal timing signal generation circuit, and an LCD.

FIG. 6 is a diagram for explaining a configuration of a synchronous LCD drive circuit.

FIG. 7 is a flowchart for explaining an operation sequence of the digital electronic still camera according to the present invention.

[Explanation of symbols]

1 Lens 2 Iris 3 Optical Filter 4 CCD 5 CDS Circuit 6 Gamma Correction Circuit 7 A / D Converter 8 Signal Processing Circuit 9 Iris Control Circuit 10 CCD Driving Circuit 11 Synchronous Signal Timing Signal Generation Circuit (System Clock Oscillation Circuit) 12 Release 13 System control CPU 14 Memory interface 15 Memory control circuit 16 Memory card 17 Liquid crystal display 18 Shooting mode setting circuit 21 Limiter circuit 22, 23, 24 Sample and hold circuit 25 Differential amplifier 26 Capacitance switching circuit 38 Video amplifier 39 Signal electrode drive circuit 40 Scanning Electrode drive circuit 41 TF transistor 43 Liquid crystal cell

Claims (1)

[Claims] 1. A digital electronic still camera using a single-plate or two-plate solid-state image pickup device, a shooting mode setting means for setting a shooting mode, and a digital signal processing circuit for outputting a level of illuminance of an object. In addition to the NTSC system clock, a system clock oscillator circuit that can output a clock with a lower frequency than this system clock, and a capacity switching circuit that operates correctly with respect to the variable processing time due to the variable system clock are provided. CDS
A circuit, a solid-state image pickup device drive circuit synchronized with the clock output from the system clock oscillator circuit, a digital liquid crystal drive circuit synchronized with the clock output from the system clock oscillator circuit, and display driven by the digital liquid crystal drive circuit The monitor liquid crystal display device and the level of the illuminance of the subject output by the digital signal processing circuit are determined, it is determined that the level is lower than a predetermined value, and it is determined that the subject is a still subject based on the setting of the shooting mode setting circuit. In this case, the frequency of the clock output from the system clock oscillator circuit is changed so as to be smaller than the frequency of the system clock, and the A / D converter, the solid-state image sensor drive circuit, and the Digital liquid crystal drive circuit and the CD
A system clock variable type digital electronic still camera system comprising: control means for controlling the S circuit to drive.