JP3531601B2 - Memory control method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method, and more particularly, to a memory control method for storing data of a detected defective pixel in a memory when a pixel (point) defect of a solid-state image sensor is detected. .

[0002]

2. Description of the Related Art In a solid-state image pickup device formed of a semiconductor such as CCD, a defective pixel whose sensitivity is lowered due to a local crystal defect of the semiconductor may occur. In such a case,
It is known that image quality deterioration occurs due to the imaging output of the defective pixel.

Conventionally, in the case of detecting such a defective pixel, an expensive device such as an enormous memory or an averaging device is used in an inspection process in manufacturing the solid-state image pickup device, and the defect is detected for each solid-state image pickup device. Defect data about pixels is added before shipment, and it is not automatically detected in the set. Therefore, it has not been possible to deal with any pixel defect due to a scratch or the like that occurs due to some stress factor after shipment.

Therefore, in recent years, there has been proposed a defect detection / correction system capable of detecting a defective pixel and correcting the defective pixel even when the defective pixel is incorporated in a device such as a video camera. In this type of defect detection / correction system, when detecting and scanning one screen, defective pixels are sequentially detected from the edge of the screen, and defect data for the pixels are sequentially stored in a memory.

The defect data stored at the time of this defect detection is
Address data for specifying the absolute position of the defective pixel or level data indicating the size of the defect level is added to the address data. Therefore, when the defect detection and correction system is actually installed in a device such as a video camera, the data amount that can store the defect data is limited by the storage capacity of the memory, and in general, within 10 defective pixels. The amount of data is reasonable.

[0006]

However, in the conventional defect detection and correction system, defect detection is sequentially inspected from the first line in the screen, and when a defective pixel is detected, the defect data is stored in the memory in real time. Since the scanning of one frame is completed, the number of defective pixels that exist is supposed to be the memory storage capacity (for example, 10).
If it exceeds, there is a problem that the defective data for the defective pixel detected thereafter cannot be stored.

In particular, when the defect detection level is fixed to an arbitrary value without selecting the defect level (size) depending on the size, it is detected after the allowable number corresponding to the storage capacity of the memory is exceeded. For defective pixels, even if the defect level is very large, the defect data cannot be stored, so that defect correction can be performed only on the first half of the screen regardless of the size of the defect level.

The present invention has been made in view of the above problems, and an object thereof is to effectively use a memory having a limited storage capacity to detect defects efficiently over the entire screen. It is to provide a memory control method that enables the above.

[0009]

In order to achieve the above object, in the method of controlling a memory according to the present invention, data of defective pixels of a solid-state image pickup device are sequentially stored in a memory, and the amount of data exceeding the storage capacity of this memory is exceeded. When the defective pixel data is detected, that is, when the number of defective pixels exceeding the memory storage allowable number is detected, the defective pixel data stored in the memory is cleared.

When performing the defect inspection, when the number of detected defective pixels exceeds the storage allowable number of the memory, the stored contents of the memory are cleared to reduce the defect detection sensitivity and detect the defect again. It becomes possible to operate. Then, the defect detection is performed again with the lowered defect detection sensitivity, and this process is repeated until the number of defective pixels falls within the allowable range. As a result, it is possible to detect an allowable number of defective pixels from those having a high defect level. Therefore, a memory having a limited storage capacity can be effectively used.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of a digital signal processing circuit of a CCD camera to which the first embodiment of the present invention is applied. In FIG. 1, a subject is imaged on an image pickup surface of a CCD solid-state image pickup device 3 by an optical system including a lens 1 and an aperture (IRIS) 2. The aperture 2 of this optical system is controlled to be opened / closed by the microcomputer 4 at the time of defect detection / correction described later.

The timing generator 5 generates various signals at appropriate timings, reads out signal charges from each pixel (photosensor) in the CCD solid-state image pickup device 3 to the vertical transfer register, performs vertical transfer by the vertical transfer register, The horizontal transfer is driven by the horizontal transfer register.

The image pickup output of the CCD solid-state image pickup device 3 is S /
After passing through the H (sample / hold) & AGC (automatic gain control) circuit 6, it is A / D converted by the A / D converter 7 and supplied to the defect correction circuit 8 and the defect detection device 9 as, for example, 10-bit data. The image pickup output whose defect has been corrected by the defect correction circuit 8 is subjected to various kinds of signal processing by the signal processing circuit 10 to be output as a luminance (Y) signal and a chroma (C) signal. Become.

Here, a specific structure of the defect detecting device 9 will be described. This defect detecting device 9 detects a defective pixel by comparing the image pickup output level of the CCD solid-state image pickup device 3 with a predetermined detection level.
And an address detection circuit 22 for specifying the address of the defective pixel based on the detection output of the comparator 21, and a RAM 23 for storing the address data given by the address detection circuit 22 for each odd / even field.
It is configured to have and.

The RAM 23 has a storage capacity capable of storing defective data of, for example, about 10 defective pixels. R
The read address from the AM23 is the correction pulse generation circuit 1
2 is supplied. This correction pulse generation circuit 12 has RA
A defect correction pulse is generated at a timing corresponding to the read address from M23 and supplied to the defect correction circuit 8.

The defect detecting device 9 further includes a counter (defect number detecting means) 25 for counting the number of defective pixels based on the detection output of the comparator 21, and the comparator 21.
And a detection level setting circuit (control means) 26 for setting the detection level (reference level) and controlling the detection level based on the number detected by the counter 25.

Specifically, the detection level setting circuit 26 is
Normally, a certain detection level is given to the comparator 21, and when the number of detections by the counter 25 exceeds the number corresponding to the storage capacity of the RAM 23 (10 in this example), the detection level of the comparator 21 is set higher than before. It also controls to raise. Thus, increasing the detection level of the comparator 21 means decreasing the defect detection sensitivity.

Next, FIG. 2 shows an algorithm for defect detection and defect correction when the defect detection device having the above-mentioned configuration is used.
It will be described in accordance with the flowchart of.

When the power of the CCD camera is turned on, the microcomputer 4 first closes the lens diaphragm 2 to bring the CCD solid-state image pickup device 3 into a completely black state with no light incident (step S
1), followed by a read pulse XSG1, generated from the timing generator 5 for the CCD solid-state image sensor 3.
The XSG2 is stopped (step S2). As described above, by stopping the read pulses XSG1 and XSG2,
As is clear from the timing chart of (B), since the signal charges can be accumulated in the photosensor for a long time, the pixel defect signal can be substantially amplified, and thus the defect detection sensitivity can be improved.

FIG. 3 is a timing chart in the frame read drive (frame accumulation mode),
(A) shows a case of normal operation, and (B) shows a case of long-time accumulation.

In FIG. 3, VD is a vertical synchronizing signal in an NTSC TV signal, FLD is an (EVEN / ODD) discrimination signal, XSG1 and XSG2 are read pulses for reading signal charges from each pixel, and ST / SP is defect detection. Start / stop signal (starting rising, stopping falling), VCLK
Is a vertical transfer clock, S / H OUT is a sample hold output of the image pickup output of the CCD solid-state image pickup device 3, and W pulse is a defect detection pulse. Further, in the sample hold output S / H OUT, the pulse a represents a defect output having a small level, and the pulse b represents a defect output having a large level.

Next, the image pickup output of the CCD solid state image pickup device 3 is inputted to the comparator 21 as an inspection signal, and the image pickup output level in this comparator 21 is compared with a predetermined detection level given by the detection level setting circuit 26 (step S3). ). Then, the defective pixel is detected by the comparison output of the comparator 21 when the image pickup output level of the CCD solid-state image pickup device 3 becomes equal to or higher than a predetermined detection level (step S4).

Next, the address of the defective pixel is detected by the address detection circuit 22 based on the detection output of the comparator 21 (step S5), and at the same time, the number of detected defective pixels is counted by the counter 25 (step S6). Then, it is determined whether or not the number counted by the counter 25, that is, the number N of defective pixels detected exceeds a predetermined number N ₀ (10 in this example) (step S7). If N ≦ N ₀ , a step is performed. The address data detected in S5 is stored in the RAM 23 (step S8).

On the other hand, in the case of N> N ₀ , it means that the number of detected defective pixels exceeds the allowable storage number of the RAM 23.
The defective data of the defective pixel detected this time is stored in the RAM 2
Since it cannot be stored in RAM 3, RAM23
Clear all the defect data stored in (Step S
9), the comparator 2 by the detection level setting circuit 26
The detection level of 1 is set higher than that (step S10), and then the process returns to step S2 to repeat the defect detection process again until the number of defective pixels falls within the storage allowable number of the RAM 23.

After the series of processes for defect detection is completed, when shifting to the normal imaging mode in which defect correction is required (step S11), first, the address data for the defective pixel is read from the RAM 23 and the correction pulse is read. It is given to the generation circuit 12 (step S12). The correction pulse generation circuit 12 generates a defect correction pulse at the timing given by the address data read from the RAM 23 (step S13), and supplies this defect correction pulse to the defect correction circuit 8.

The defect correction circuit 8 identifies the image pickup output of the defective pixel in the CCD output by the defect correction pulse, and replaces the image pickup output of the defective pixel with the image pickup output of the preceding pixel, for example. Correction is performed (step S14). Then, it is determined whether or not the lens diaphragm 2 is opened (step S15). If it is not opened, the lens diaphragm 2 is opened and light is incident on the CCD solid-state image sensor 3 (step S16), and the normal imaging mode is set. enter. Or later,
The above-described series of defect correction processing is repeatedly executed until the imaging mode ends.

As described above, when the defect inspection is performed, the number of detected defective pixels is counted, and the detected number is the RAM 2
When the storage allowable number of 3 is exceeded, the defect detection sensitivity is lowered by setting the detection level of the comparator 21 higher than before, and re-inspection is repeated until the number of defective pixels falls within the allowable range, thereby determining defective pixels. Since it is possible to detect and correct an allowable number of defects having a large defect level, the RAM 23 having a limited storage capacity can be effectively used to efficiently detect defects and correct the defects along the entire screen. It can be carried out. In addition, since the permissible number is detected from the pixels having a high defect level and the correction is performed, the deterioration of the image quality due to the correction can be suppressed to the maximum.

FIG. 4 is a block diagram showing another example of a digital signal processing circuit to which the second embodiment of the present invention is applied. In the figure, the same parts as those in FIG. The description thereof will be omitted as it will be repeated.

Defect detecting device 9'in this signal processing circuit
2 is provided with a timing control circuit 27 as a control means for controlling the defect detection sensitivity in place of the detection level setting circuit 26 in the first embodiment, and the other configuration is the same as that of FIG.

The timing control circuit 27 has read pulses XSG1 and XSG generated from the timing generator 5.
This is for controlling the timing of SG2, and in the long time accumulation in the defect detection mode (see FIG. 3B), the number detected by the counter 25 corresponds to the storage capacity of the RAM 23 (in this example, When the number exceeds 10), the period for stopping the read pulses XSG1 and XSG2 is shortened so that the signal charge storage time is set shorter than before.

FIG. 5 is a flow chart showing an algorithm for defect detection and defect correction when the defect detection apparatus having the above-mentioned configuration is used. The difference from the flow chart of FIG. 2 is only the processing of step S10 '. . In step S10 ′, when it is determined in step S7 that N> N ₀ , a process of setting the signal charge storage time shorter than before is performed. Thus, shortening the signal charge storage time means lowering the defect detection sensitivity.

Therefore, after the processing of step S10 ',
By returning to step S2 and repeating the defect detection operation until the number of defective pixels falls within the allowable range, it is possible to detect an allowable number of defective pixels starting from the one having a high defect level, as in the case of the first embodiment. Therefore, it is possible to effectively use the RAM 23 having a limited storage capacity to efficiently detect defects over the entire screen.

In each of the above embodiments, the case where the signal processing system in the CCD camera is digitally configured has been described, but the present invention is not limited to this, and FIG.
As shown in FIG. 6, the same can be applied to the case of analog configuration.

FIG. 6 shows a circuit configuration corresponding to the first embodiment. In case of analog configuration, S / H & AG
Sampling pulse SP of S / H circuit in C circuit 6
By controlling the timings of 1 and SP2, for example, it is possible to perform defect correction in which the imaging output of the defective pixel is replaced with the imaging output of the previous pixel. Therefore, the timing control circuit 13 that controls the timing of the timing generator 5 may be provided to control the timing of the sampling pulses SP1 and SP2 based on the address data read from the RAM 23.

Further, in each of the above-described embodiments, the defect detection is performed at power-on and the defect data regarding the defective pixel is stored in the RAM 23. However, the defect detection mode is set before the power is cut off, and in this defect detection mode. It is also possible to store the detected defect data in a non-volatile memory such as an E ² PROM.

[0037]

As described above, according to the present invention,
When performing the defect inspection, when the amount of detected defective pixel data exceeds the storage capacity of the memory, the defective pixel data stored in the memory is cleared and the defect detection is performed again with the lowered defect detection sensitivity. Performed and detected with this lowered defect detection sensitivity
To store the data of the defective pixel in the memory
This allows you to effectively use the limited memory capacity.
You can Especially, clearing and missing data of defective pixels
The process of re-detection of defects by lowering the Recessed detection sensitivity by repeated until the number of defective pixels is within the allowable, it is possible to detect only the allowed number from those as defective pixel defect levels greater, limited By effectively using a memory having the above storage capacity, it becomes possible to detect defects efficiently over the entire screen.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a digital signal processing circuit of a CCD camera to which a first embodiment of the present invention is applied.

FIG. 2 is a flowchart showing an algorithm for defect detection and defect correction according to the first embodiment.

3A and 3B are timing charts in frame read driving, in which FIG. 3A shows a case of normal operation and FIG. 3B shows a case of long-time storage.

FIG. 4 is a flowchart showing an algorithm for defect detection and defect correction according to the first embodiment.

FIG. 5 is a flowchart showing an algorithm for defect detection and defect correction according to the second embodiment.

FIG. 6 is a block diagram showing a case where an analog signal processing configuration is adopted.

[Explanation of symbols]

3 ... CCD solid-state image sensor, 4 ... Microcomputer, 5 ... Timing generator, 8 ... Defect correction circuit, 9, 9 ′, 9 ″ ...
Defect detection device, 12 ... Correction pulse generation circuit, 13, 27
... Timing control circuit, 21 ... Comparator, 22 ... Address detection circuit, 23 ... RAM, 25 ... Counter, 26
... Detection level setting circuit

Claims (4)

(57) [Claims] 1. A method for controlling a memory for storing data of defective pixels of a solid-state image sensor, comprising : storing data of defective pixels of the solid-state image sensor in order in a memory, the amount of defects exceeding a storage capacity of the memory. Defect detection sensitivity lower than when the data of the defective pixel stored in the memory is cleared when the data of the pixel is detected , and then until the clear is performed.
The data of the defective pixel detected by is stored in the memory.
A method of controlling a memory characterized by: 2. The defective pixels stored in the memory
Clear the data, and then detect with the low defect detection sensitivity described above.
A process for storing the data of the defective pixel that is output in the memory
Data of the detected defective pixel is stored in the memory.
2. The method for controlling a memory according to claim 1, wherein the process is repeated until the amount is reached . 3. The method of controlling a memory according to claim 1, wherein the memory is a RAM. 4. The method of controlling a memory according to claim 1, wherein the defective pixel data is address data for specifying an absolute position of the defective pixel.