JPH06319086A - Defect detecting device for solid-state image pickup element and defect correcting circuit using the detecting device - Google Patents

Abstract

PURPOSE:To obtain a defect detecting device capable of accurately detecting a defective picture element, by effectively amplifying only the level of a defect and corresponding to a solid-state image pickup element having oscillation correcting function. CONSTITUTION:At the time of detecting a defect in a CCD solid-state image pickup element driven by field reading and corresponding to oscillation correction, the generation of a reading pulse XSG is stopped only for prescribed fields, and during the stop period, vertical transfer clocks VCLK are continuously generated. Thereby a timing generator 5 is controlled by a microcomputer 4, a defective picture element is detected by a defect detecting circuit 9 based upon the image pickup output level of the element 3 and the address data of the defective picture element are stored in a RAM 23. A defect correcting pulse DEF is generated based upon the data read out from the RAM 23 and defect correction is executed by a defect correcting circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect detection device for detecting pixel (point) defects of a solid-state image pickup device and a defect correction device using the same, and more particularly to a solid-state driven in field reading (field accumulation mode). The present invention relates to an image sensor defect detection device and a defect correction device thereof.

[0002]

2. Description of the Related Art In a solid-state image pickup device formed of a semiconductor such as CCD, a defective pixel whose sensitivity is lowered due to a local crystal defect of the semiconductor may occur. In such a case,
It is known that image quality deterioration occurs due to the imaging output of the defective pixel. When detecting such defective pixels, conventionally, an expensive device such as an enormous memory or an averaging device is used in the inspection process in manufacturing the solid-state image sensor, and the defective pixel is detected for each solid-state image sensor. The defect data is added before shipment, and it is not automatically detected in the set. Therefore,
It was not possible to deal with pixel defects due to scratches or the like that occur due to some stress factor after shipment.

[0003]

Therefore, in recent years, there has been proposed a defect detection / correction system capable of detecting a defective pixel and correcting the defective pixel even when the defective pixel is incorporated in a device such as a video camera. By the way, since the level of the defect which is usually a problem is very small, the defective pixel cannot be easily detected. If you amplify the signal to increase its detection sensitivity,
Noise is also amplified. Therefore, it is desired to improve the detection sensitivity by effectively amplifying only the defect level.

In recent years, as one of the methods for correcting camera shake with a video camera, in the case of deriving a solid-state image pickup device having a number of pixels larger than the number of pixels required for normal image pickup, for example, an NTSC TV signal. There is known a method in which a solid-state image sensor compatible with the PAL system is used and a part of the pixel area thereof is used for camera shake correction. In the case of the solid-state image sensor having the image stabilization function, in actual operation, as will be described later in detail, not the normal read drive,
An operation of sweeping out signal charges of unused pixels is performed. Therefore, when detecting defects of this type of solid-state imaging device, the signal charges of some pixels are swept away under the above-mentioned driving conditions, and the information of all pixels cannot be read.

The present invention has been made in view of the above problems, and an object thereof is to detect defective pixels with high accuracy by effectively amplifying only the level of defects.
Moreover, it is an object of the present invention to provide a defect detection device that can be applied to a solid-state image sensor having a camera shake correction function and a defect correction device using the defect detection device.

[0006]

A defect detection apparatus according to the present invention is a solid-state image pickup device comprising photosensors two-dimensionally arranged in a matrix and vertical transfer registers arranged in each vertical column of the photosensors. A timing generator that drives a read pulse for reading signal charges from the photosensor to the vertical transfer registers and a vertical transfer clock for driving the vertical transfer registers to vertically transfer the signal charges, and drives by field reading when a defect is detected. And a control means for controlling the timing generator so as to stop the generation of the read pulse for a predetermined field at the time of defect detection and continuously generate the vertical transfer clock during this stop period, and based on the image output level of the solid-state image sensor. Defect detecting means for detecting defective pixels by It has a configuration that includes a memory for storing the defect data for.

[0007]

In the solid-state image pickup device driven by the field readout which is adopted as a general drive system, defect detection is performed by the same field readout drive as the drive system at the time of normal image pickup, and by long-term storage drive. . According to this, since it is not necessary to convert the address data, the circuit configuration can be simplified, and only the level of the defect can be amplified by long-time storage, so that the defective pixel can be accurately detected. In addition, in the case of long-time accumulation, by stopping the generation of the read pulse for a predetermined field and continuously generating the vertical transfer clock during this stop period, even in a solid-state image sensor compatible with camera shake correction, Defect inspection can be performed.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention having a digital signal processing configuration applied to a CCD camera, for example. In FIG. 1, a subject is imaged on an image pickup surface of a CCD solid-state image pickup device 3 by an optical system including a lens 1 and an aperture (IRIS) 2. The aperture 2 of this optical system is controlled to be opened / closed by the microcomputer 4 at the time of defect detection / correction described later. The timing generator 5 generates various signals at appropriate timings, reads out signal charges from each pixel (photosensor) in the CCD solid-state imaging device 3 to a vertical transfer register, performs vertical transfer by the vertical transfer register,
This is for driving horizontal transfer by the horizontal transfer register.

FIG. 2 shows a structural example of the CCD solid-state image pickup device 3 having a camera shake correction function. In the figure, a large number of photosensors 31 arranged two-dimensionally in a matrix,
The image pickup section 34 is configured by a plurality of vertical transfer registers 33 arranged in each vertical column of the photosensors 31 and vertically transferring the signal charges read through the read gate 32. The signal charges read to the vertical transfer register 33 are sequentially transferred to the horizontal transfer register 35 in units corresponding to one scanning line. The signal charges for one scanning line are sequentially transferred in the horizontal direction by the horizontal transfer register 35 and supplied to the charge detection unit 36.

The charge detection section 36 is composed of, for example, a floating diffusion amplifier, detects the signal charge transferred by the horizontal transfer register 35, converts it into a signal voltage, and outputs it as a TV signal. The horizontal transfer register 35 is continuously provided with an unnecessary charge discharging gate 37, and further, the unnecessary charge discharging gate 37 is continuously provided with an unnecessary charge discharging drain 38 for discharging charges in the horizontal transfer register 35. . The potential of the unnecessary charge discharging drain 38 becomes sufficiently deep,
A voltage is applied so that the charges existing in the horizontal transfer register 35 can flow in when the unnecessary charge discharging gate 37 is opened.

From the timing generator 5 described above, a read pulse XSG for reading out the signal charge accumulated in the photosensor 31 of the CCD solid-state image pickup device 3 to the vertical transfer register 33, and the signal charge read out by this read pulse XSG is vertically added. Vertical transfer clock VCL to be transferred
K, a horizontal transfer clock HCLK for horizontally transferring the signal charges transferred to the horizontal transfer register 35, a drain pulse SG for controlling on / off of the unnecessary charge discharging gate 37, and a switch pulse SP for controlling on / off of a switch 39 described later. Various timing signals, etc., are appropriately generated.
The switch 3 is provided between the output line of the charge detector 16 and the ground.
9 and the resistor 40 are connected in series. This switch 3
9 is normally in the off (open) state, and the switch pulse S
When P is applied, it is turned on (closed) to bring the output line to the ground level.

As the CCD solid-state image pickup device 3 for image stabilization having the above-mentioned structure, one having an image pickup area larger than the range shown on the screen, for example, in the case of deriving a TV signal of NTSC system, one of NTSC system is used. Also, a PAL system compatible with a large number of lines is used. Then, for example, when correcting the shake in the vertical direction, the signal charges of the upper and lower unnecessary portions of the image pickup unit 34 are transferred to the high-speed vertical transfer clock VCLK.
The high-speed transfer is carried out, and the unnecessary charges are discharged to the unnecessary charges discharging drain 38 through the unnecessary charges discharging gate 37 to use only the signal charges of the line corresponding to the NTSC system.

That is, the amount of camera shake that occurs during imaging of the upper and lower unnecessary portions (the detection mechanism is not shown).
By moving based on motion data according to
The shake of the surface of the D solid-state image sensor 3 is absorbed, and the camera shake correction is realized. The image pickup output of the CCD solid-state image pickup device 3 is passed through an S / H (sample / hold) & AGC (automatic gain control) circuit 6 and then A / D converted by an A / D converter 7 to correct defects as, for example, 10-bit data. Circuit 8
And the defect detection circuit 9. The image pickup output whose defect has been corrected by the defect correction circuit 8 is subjected to various kinds of signal processing by the signal processing circuit 10 to be output as a luminance (Y) signal and a chroma (C) signal. Become.

The defect detection circuit 9 is a CCD solid-state image pickup device 3.
Of the defective pixel by comparing the imaging output level of the defective pixel with a predetermined detection level, an address detecting circuit 22 for specifying the address of the defective pixel based on the detection output of the comparator 21, and the address detecting circuit 22. The address data given by
It is composed of a RAM 23 for storing each even field. The read address from the RAM 23 is supplied to the correction pulse generation circuit 12. The correction pulse generation circuit 12 generates a defect correction pulse DEF at a timing according to the read address from the RAM 23 and supplies it to the defect correction circuit 8.

By the way, normally, the defective pixels of the CCD solid-state image pickup device 3 are present in units of one pixel. When the CCD solid-state image pickup device 3 is operated by the field reading drive (field storage mode) which is adopted as a general drive system, the signal charge of the photo sensor 31 accumulated for one field period is vertical. It will be mixed and output between two adjacent pixels. Therefore, the signal charges of all pixels are read out for each field, and the defect of one pixel is output over two fields by changing the line. Therefore, the defect correction requires correction of two fields for one pixel.

Therefore, if defect detection is to be performed by field read driving, inspection must be performed in field units. That is, in the field read drive, all pixels are read out for each field, and therefore, in order to amplify the defect level by extending the accumulation time of signal charges in each pixel, a storage operation is required for each field. 3A and 3B are timing charts of field read driving, in which FIG. 3A shows a case of normal operation and FIG. 3B shows a case of long-time storage.

In FIG. 3, VD is a vertical synchronizing signal of an NTSC TV signal, FLD is an (EVEN / ODD) discrimination signal, and XS.
G is a read pulse for reading the signal charge from each pixel, ST / SP is a defect detection start / stop signal (starting rising, stopping falling), VCLK is a vertical transfer clock, S / H OUT is a CCD solid-state image sensor Sample hold output of 3 imaging output, W pulse is defect detection pulse, DE
F indicates each defect correction pulse. In the sample-hold output S / H OUT, the pulse a represents a defect output with a small level, and the pulse b represents a defect output with a large level.

By the way, in the system for image stabilization, in the normal read operation, only the signal charges of the pixels of NTSC are read out as described above. Therefore, all the pixels to be used, in this example, all the pixels of PAL are read. The inspection will not be possible. Therefore, the operation of the defect detection according to the present invention in the field read drive in the system for image stabilization will be described below. First, the horizontal address count is performed by the horizontal transfer clock HCLK, and the vertical address count is performed by the vertical transfer clock VCLK. As a result, in any operating state, the count number of defective lines is always constant.

In the reading of such drive timing,
It is possible to finish the detection of the defective pixel and the storage of the address thereof regardless of the field at the time of starting the defect detection. That is, only the fields at the end are different, and it does not matter which field is later stored in the defective data. In this driving method, when the timing for stopping the reading of the signal charges is designated by the number of pulses of the vertical synchronizing signal VD, if the number of fields to be accumulated is n, the reading pulse XSG
Is stopped when the ST / SP signal rises (STAR
It may be performed at the following timing with the count number of the vertical synchronizing signal VD after T).

That is, the read pulse XSG to be stopped
Is 1 to n, n + 2, (n + 3) to 2n + 3, 2n + 5
Becomes Here, the number n of fields to be accumulated is an odd value of 3 or more, and is a value arbitrarily determined from the setting of the detection accuracy and the detection lower limit. Note that, while the read pulse XSG is stopped, the vertical transfer clock VCLK is a continuous pulse without being modulated during vertical blanking. In the defect detection operation in the field read drive described above, the microcomputer 4 stops the generation of the read pulse XSG for odd fields of 3 or more and continuously generates the vertical transfer clock VCLK during this stop period. It is realized by controlling 5.

Next, the algorithm of defect detection and defect correction according to the present invention will be described with reference to the flowchart of FIG. When the power of the CCD camera is turned on, the microcomputer 4 first closes the lens diaphragm 2 to bring the CCD solid-state image sensor 3 into a completely black state with no light incident (step S
1) Then, the read pulse XSG generated from the timing generator 5 for the CCD solid-state image sensor 3 is stopped (step S2). Thus, the read pulse X
As shown in the timing chart of FIG. 3B, the signal charge can be accumulated in each photosensor 31 for a long time by stopping the SG, so that the pixel defect signal can be substantially amplified, so that the defective pixel can be accurately detected. It can be detected well.

Next, the image pickup output of the CCD solid-state image pickup device 3 is inputted to the comparator 21 as an inspection signal, and the image pickup output level in this comparator 21 is compared with a predetermined detection level given by the detection level setting circuit 26 (step S3). ). Then, the defective pixel is detected by the comparison output of the comparator 21 when the image pickup output level of the CCD solid-state image pickup device 3 becomes equal to or higher than a predetermined detection level (step S4). Then, based on the detection output of the comparator 21, the address detection circuit 22 detects the horizontal / horizontal position of the defective pixel.
Vertical address data is generated (step S5), and this address data is stored in the RAM 23 (step S).
6).

After the series of processing for defect detection is completed, when the normal image pickup mode in which the defect correction is required is to be performed (step S7), the address data for the defective pixel is read from the RAM 23 and the correction pulse generating circuit is read. 12 (step S8). The correction pulse generation circuit 12 is
The defect correction pulse DEF is generated at the timing given by the address data read from the RAM 23 (step S9), and this defect correction pulse DEF is supplied to the defect correction circuit 8.

The defect correction circuit 8 uses this defect correction pulse D.
The EF is used to identify the image pickup output for the defective pixel in the CCD output, and for example, the image pickup output of the defective pixel is replaced with the image pickup output one pixel before (step S10). Then, it is judged whether or not the lens diaphragm 2 is opened (step S11). If it is not opened, the lens diaphragm 2 is opened and light is made incident on the CCD solid-state image sensor 3 (step S12), and a normal imaging mode is set. enter. After that, the series of defect correction processes described above is repeatedly executed until the imaging mode ends.

As described above, in the CCD solid-state image pickup device 3 driven by the field read-out which has been adopted as a recent general drive system, the field read-out drive is the same as that of the drive system at the time of normal image pickup, and the length is long. By performing defect detection by time accumulation drive, there is no need to convert address data, so the circuit configuration can be simplified, and since only the defect level can be amplified by long-term accumulation, defective pixels can be detected accurately. it can. Further, when the read pulse XSG is stored for a long time, the generation of the read pulse XSG is stopped for an odd field of 3 or more, and the vertical transfer clock VCLK is continuously generated during this stop period.
Even if the CCD solid-state image sensor 3 is compatible with camera shake correction, defect inspection can be performed on all pixels.

In the above-described embodiment, the case where the present invention is applied to the CCD solid-state image pickup device 3 for camera shake correction has been described, but the present invention can also be applied to this type of CCD solid-state image pickup device. The present invention is not limited to the above, and can be applied to a normal CCD solid-state image pickup device as well.
Pixel defects can be detected by the same operation regardless of whether it is compatible with the TSC system or the PAL system. Further, although the case where the signal processing system in the CCD video camera is configured digitally has been described in the above embodiment, the present invention is not limited to this, and the present invention is also applied to the case where it is configured analogically. I will get it.

Further, in the case where the timing generator 5 is configured to generate all timing signals with the vertical synchronizing signal VD as a reference, it is desired to stop the generation of the read pulse XSG with respect to the vertical synchronizing signal VD input to the timing generator 5. Even if the portion is blanked, the drive operation for defect detection similar to that in the above embodiment can be realized.

[0028]

As described above, according to the present invention,
In the field-reading drive solid-state image sensor, the same field-reading drive as in the normal image-pickup method, and the defect detection by the long-time storage drive make it unnecessary to convert address data. Since the circuit configuration can be simplified and only the defect level can be amplified by long-term storage, defective pixels can be detected with high accuracy. Further, in the long-time storage drive, the generation of the read pulse is stopped for a predetermined field and the vertical transfer clock is continuously generated during this stop period, so that even in a solid-state image sensor compatible with camera shake correction, Defect inspection can be performed on all pixels.
Further, since it can be easily realized only by controlling the timing of the read pulse and the vertical transfer clock, it can be easily applied to the existing camera system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention of a digital signal processing configuration applied to a CCD camera.

FIG. 2 is a block diagram showing a configuration example of a CCD solid-state imaging device compatible with camera shake correction.

3A and 3B are timing charts of field read driving, in which FIG. 3A shows a case of normal operation, and FIG. 3B shows a case of camera shake response and long-time storage.

FIG. 4 is a flowchart showing an algorithm for defect detection and defect correction according to the present invention.

[Explanation of symbols]

 3 CCD solid-state image sensor 4 Microcomputer 5 Timing generator 8 Defect correction circuit 9 Defect detection circuit 12 Correction pulse generation circuit 21 Comparator 22 Address detection circuit 23 RAM

Claims (3)

[Claims] 1. A solid-state imaging device comprising photosensors arranged two-dimensionally in a matrix and vertical transfer registers arranged in each vertical column of the photosensors, wherein signal charges are transferred from the photosensors to the vertical transfer registers. A timing generator for generating a read pulse for reading and a vertical transfer clock for driving the vertical transfer register to vertically transfer signal charges, and driving the solid-state imaging device by field reading at the time of defect detection; Occasionally, the generation of the read pulse is stopped for a predetermined field, and the control means controls the timing generator to continuously generate the vertical transfer clock during this stop period; and a defect based on the image output level of the solid-state image sensor. Defect detecting means for detecting a pixel, and the defective pixel Defect detection apparatus characterized by comprising a memory for storing the defect data with. 2. The defect detecting apparatus according to claim 1, wherein the solid-state image sensor has a camera shake correction function. 3. A defect correction device using the defect detection device according to claim 1 or 2, wherein the correction pulse generation means generates a defect correction pulse at a timing given by the defect data read from the memory, A defect correction device, comprising: a defect correction means for performing defect correction on an image pickup output of the solid-state image pickup device in response to a defect correction pulse.