JP2009207195A - Image data processing apparatus, imaging system, image data processing method, computer program, and computer-readable storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a defect correction of data outputted in real time from an image sensor without needing a frame memory which is needed conventionally. <P>SOLUTION: The address of a specific pixel of an image sensor 101 is stored into a memory portion 106; a current row address of the pixel data outputted from the image sensor 101 is indicated by a row counter 108; matching of the row address of the specific pixel read from the memory portion 106 by a memory fetch portion 107 and the current row address indicated by the counter 108 is detected by an address decode portion 109; a correction of the pixel data which correspond to the current address and are output from the image sensor 101 is conducted by an image correction portion 103; and a defect correction of the pixel data from the image sensor 101 can be made, which allows the frame memory needed conventionally to be made unnecessary. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image data processing apparatus, an imaging system, an image data processing method, a computer program, and a computer-readable storage medium, and is particularly suitable for use in correcting data from an image sensor.

An image sensor has a pixel point defect with a certain probability. Conventionally, the point defect has been corrected by the following method.
1) The address of the point defect of the pixel is previously stored in the memory.
2) Store data from the image sensor in the frame memory.
3) The pixel data corresponding to the address stored in the memory among the pixel data stored in the frame memory is interpolated by calculation using the peripheral pixel data.

  However, this method requires a frame memory that supports the entire screen, which leads to an increase in cost, and the number of frames that can be output per unit time is increased because the calculation is performed after one image data is taken. There were problems such as reduction by defect correction processing.

  In addition, when this method is adopted, in order to finish the processing within the time that can withstand actual use, it is necessary for the processing IC to operate with a clock faster than the processing operation of the image sensor. In some cases, the noise generated by the IC is transmitted to the image sensor, and the image quality deteriorates.

  The present invention has been made in view of the above-described problems, and it is an object of the present invention to make it possible to perform defect correction of data output from an image sensor in real time without requiring a frame memory that has been conventionally required. And

An image data processing apparatus according to the present invention stores address data of a correction target pixel of the image sensor in an image data processing apparatus connected to an output terminal of an image sensor that outputs image data divided for each row of pixel data. A memory; a row counter that indicates a row of current pixel data output from the image sensor; a memory data fetch unit that reads the address data from the memory; and the address data read by the memory data fetch unit An address decoding unit that determines whether a row of pixel data to which the correction target pixel belongs and a row of pixel data designated by the row counter match, and based on the address data stored in the memory And is set according to the determination result in the address decoding unit. A shift register that outputs a positive instruction signal; and an image correction unit that corrects pixel data output from the image sensor based on the correction instruction signal output from the shift register, and sequentially from the image sensor. The shift register operates in synchronization with the output image data, the correction of the image data from the image sensor is controlled, and the shift register is synchronized with the pixel data appearing at the output terminal of the image sensor. Shifting and outputting the correction instruction signal to the image correction unit.
The present invention also provides an image data processing method by the above-described image data processing apparatus, a computer program for causing a computer to execute the image data processing method, and a computer-readable storage medium storing the computer program. Including.

  According to the present invention, a correction instruction can be output in synchronization with input of pixel data corresponding to an address of a specific pixel, for example, a pixel to be corrected, from the image sensor. The defect correction can be performed in real time, and the frame memory which has been conventionally required can be eliminated. Accordingly, the circuit scale can be reduced as compared with the conventional correction circuit, and image data processing with less superimposed noise can be realized by employing a circuit that can be driven at a low clock frequency. In addition, since there is no need to capture the frame memory once, a higher frame rate can be realized.

  Further, the pixel to be corrected can be accurately processed by synchronizing the pixel correction instruction signal and the pixel data fetched from the image sensor.

It is a functional block diagram of the image data processing device in the first embodiment. It is the figure which showed the flow of the initialization process and correction | amendment process of the image data processing apparatus in 1st Embodiment. It is a functional block diagram of the image data processing apparatus in 2nd Embodiment. It is the figure which showed the flow of the initialization process and correction | amendment process of the image data processing apparatus in 2nd Embodiment. It is the figure which showed the flow of the initialization process and correction | amendment process of the image data processing apparatus in 2nd Embodiment. 1 is a block diagram illustrating an example in which an image data processing apparatus according to the present invention is applied to an imaging apparatus.

  Next, embodiments of an image data processing apparatus, an imaging system, an image data processing method, a computer program, and a computer-readable storage medium according to the present invention will be described with reference to the accompanying drawings.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a functional block diagram of the image data processing apparatus 113 in the present embodiment. An image sensor 101 is a data generation source, and is connected to the image data processing device 113.

  In the image data processing device 113, 102 is an input terminal of the image data processing device 113. An image correction unit 103 performs pixel correction processing. The input terminal 104 receives data from the image sensor 101, the input terminal 105 receives a pixel correction instruction signal from the shift register 110, and outputs a pixel correction result. An output terminal 112 is provided.

  An address holding memory unit 106 holds address data to be corrected and stores data in an arbitrary format. A memory fetch unit 107 fetches memory data held in the address holding memory unit 106 in units of predetermined correction target addresses. Reference numeral 108 denotes a row counter.

  Reference numeral 109 denotes an address decoder, which receives information from the row counter 108 and information about the correction target address from the memory fetch unit 107. A 1-bit serial shift register 110 receives the decoding result output from the address decoder 109 and outputs a pixel correction instruction signal from the final stage 111 to the input terminal 105 of the image correction unit 103.

  Next, the operation of this functional block will be described. In the present embodiment, it is assumed that the addresses of the correction target pixels are sorted in ascending order of row numbers as the address arrangement in the address holding memory unit 106.

  First, the shift register 110 is completely initialized. Here, the initial state is “0”, and the correction instruction signal is “1”. During the initialization processing period of the shift register 110, address data is read from the address holding memory unit 106 to the memory fetch unit 107. This address data has information indicating the row and column of the correction target pixel.

  On the other hand, the row counter 108 holds the current row number to be corrected.

  In the address decoder 109, the two row numbers of the row number included in the address data of the memory fetch unit 107 and the row number held in the row counter 108 are compared, and if they match, the current memory fetch unit Assuming that the column number fetched at 107 indicates a pixel to be corrected, a decode signal is sent to the shift register 110. For example, if the column number fetched by the memory fetch unit 107 is No. 10, “1” is written to the tenth of the shift register 110.

  Thereafter, the next address data is fetched, and the address decoding and the shift register 110 initialization process similar to the above are performed. This operation is temporarily stopped when the line numbers do not match.

Next, the pixel correction period (the operation period of the shift register 110) starts.
First, the shift register 110 is operated at the same rate as the data from the image sensor 101. For example, if the data of the 10th column of a certain row is a pixel to be corrected, the pixel correction instruction signal of the shift register 110 is just the initial while the 10 pixel data from the image sensor 101 arrives at the input terminal 104. At the same time as the pixel data of the 10th column is input to the image correction unit 103, the pixel correction instruction signal is input to the image correction unit 103.

  The image correction unit 103 receives a pixel correction instruction signal from the shift register 110, performs some predetermined image correction processing, and outputs the result from the output terminal 112.

Here, the shift register 110 cannot perform the initialization process and the correction process (shift process for outputting a pixel correction signal) at the same time, so scheduling is necessary. The concept will be described with reference to FIG.
FIG. 2 is a diagram showing a flow of initialization processing and correction of the shift register 110 focusing on a predetermined row.

  201 shows the processing operation of the image sensor 101 with respect to the flow of time, and 202 shows the processing operation of the shift register 110 (correction circuit) corresponding thereto. Since the image sensor 101 has a period during which the pixel data is not output, that is, a horizontal blanking period while the line changes, for example, in the horizontal blanking period of the nth row, the correction data of the nth row is decoded and An initialization process of the shift register 110 is performed. After the initialization process, the shift register 110 is operated in synchronization with the pixel data from the image sensor 101 to correct predetermined pixel data.

  Here, the image sensor 101 is, for example, a CMOS sensor, a CCD, or another device. The present invention is applicable regardless of the type of the image sensor 101.

  In the present embodiment, the image sensor 101 is directly connected to the correction device (image data processing device 113). It is not limited here whether the data form during that time is analog data / digital data. For example, analog data from the image sensor 101 may be processed directly by the correction device (image data processing device 113), or data once AD-converted may be processed.

  Here, as a concept of memory fetch / address decoding, it is assumed that the rows are sorted in ascending order, and when the rows match, the position of the column fetched by the memory is decoded, and the shift register 110 Is used, and the process is repeated until the lines do not match, and the memory fetch is stopped there.

  However, the algorithm is not limited to this, and any method may be used as long as an address to be corrected can be found from the scratch address group. For example, the address may be found by scanning the memory in which the address is stored from the beginning to the end as the line advances. In this case, since it takes a long time to scan all the memories, it is possible to remove the premise that the addresses must be sorted.

  Further, the contents of the image correction processing in the image correction unit 103 are not mentioned here, but any device that performs correction in accordance with the pixel correction instruction from the shift register 110 has the effect of the present invention. Can do. For example, the image correction unit 103 may include a delay element, and the value of one pixel or a plurality of pixels before may be output as the corrected pixel output. Alternatively, for example, the image correction unit 103 may have a delay element and a delay output function, and a value after one pixel or a plurality of pixels may be output as a pixel output after correction.

  In the two methods, pixel correction can be performed only by using data in the same row, and the correlation between the correction result of the pixel and the upper and lower peripheral pixels is irrelevant. In order not to make the correlation with the upper and lower peripheral pixels irrelevant, for example, the correction circuit may have several lines of line memory, an arithmetic function, and a delay output function, and may output a correction result obtained by performing adjacent addition. In this case, the output is delayed by one line or several lines from the input.

  The line counter 108 uses the word line, but is not limited to this. When the pixels are divided into groups, the concept of a row is only introduced here for the purpose of identifying the group. For example, a group counter may be called.

  Further, the number of columns and the number of stages of the shift register 110 need to correspond in this embodiment. For example, when the number of columns of the image sensor 101 is 3000, the number of stages of the shift register 110 is also required to be 3000. For example, when only the first n pixels are to be corrected, the circuit scale can be reduced by limiting the number of stages of the shift register 110 to n stages.

  In the circuit manufacturing process, the circuit scale can also be reduced by forming the shift register 110, the image correction unit 103, and the like on the same semiconductor chip.

  In addition, it is necessary to initialize the correction data of a predetermined row in a predetermined horizontal blanking period before pixel reading starts. As a method for responding to this requirement, 1) a specification that does not allow the number of pixels to be corrected per row so that the initialization process cannot be performed in the horizontal blanking period, and 2) as soon as the initialization process is completed, It is conceivable to devise timing generation so as to start reading. Both are design items, and the effect of the present invention is not limited thereby.

  Further, when it is desired to minimize the noise generated by the processing IC, the frequency of the clock used for memory fetching during the initialization process must be as low as possible. In such a case, it is necessary to optimize the usable clock speed and the number of pixels to be corrected. These are also design items.

  In this embodiment, an instruction signal is given to the tenth register to correct the pixels in the tenth column. For example, a shift is required once to correct the pixels in the first column (first). If not, an instruction signal may be given to the ninth register. If several dummy shifts are required to correct the first pixel, an instruction signal may be set at a register position that allows for the shift.

  As described above, with the configuration of the present embodiment, the shift register 110 synchronizes with the pixel data corresponding to the address of the pixel to be corrected being input from the image sensor 101 to the image correction unit 103. Since the pixel correction instruction signal is output to the image correction unit 103, defect correction of data output from the image sensor 101 can be performed in real time, and a conventionally required frame memory can be eliminated. . Accordingly, the circuit scale can be reduced as compared with the conventional correction circuit, and image data processing with less superimposed noise can be realized by employing a circuit that can be driven at a low clock frequency.

  Further, by synchronizing the pixel correction instruction signal from the shift register 110 and the pixel data fetched from the image sensor 101, the correction target pixel can be processed accurately.

  Further, by performing the initialization process of the shift register 110 using a period during which no pixel data is output from the image sensor 101, the time required for the initialization process can be effectively reduced to zero. As a result, a faster frame rate can be realized.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. 3, FIG. 4, and FIG.
FIG. 3 is a functional block diagram of the image data processing apparatus according to this embodiment. In addition, the same code | symbol is attached | subjected to the component demonstrated in the said 1st Embodiment, and it demonstrates centering on difference with the said 1st Embodiment below.

  In the present embodiment, the address decoder 109 sets a plurality of shift registers. In this embodiment, a case where two shift registers, the first shift register 110 and the second shift register 301, are described.

  As shown in FIG. 3, the shift registers 110 and 301 have initialization enable terminals 303 and 304, respectively, and accept an instruction from the address decoder 109 only when an initialization enable instruction is received. Conversely, a shift register that has not received an instruction for initialization processing performs shift processing for outputting a pixel correction instruction signal.

  The final stages 111 and 302 of the first and second shift registers 101 and 301 are connected to the instruction signal input terminal 105 of the image correction unit 103 via the selector 305. Further, the name of the row counter 108 of the first embodiment is changed to the group counter 306 here.

Next, the operation of this functional block will be described.
The operation is basically the same as that of the first embodiment. The difference is the operation related to the first and second shift registers 110 and 301 and the selector 305 configured in parallel. For example, when the first shift register 110 is being initialized, the selector 305 connects the final stage 302 of the second shift register to the instruction signal input terminal 105 of the image correction unit 103, and the second shift register The register 301 sends a pixel correction instruction signal to the image correction unit 103. When the second shift register 301 is initialized, the reverse processing operation is performed.

  Next, the initialization process and the correction process (shift process for outputting a pixel correction signal) of the image data processing apparatus according to the present embodiment will be described with reference to FIG. Here, 401 schematically shows the processing operation of the image sensor 101 with respect to the time axis. For example, the access in the nth row includes a horizontal blanking period 402 and a pixel readout period 403. Here, the n-th row readout period 403 is divided into four parts, which are constituted by a first group readout period 404, a second group readout period 405, a third group readout period 406, and a fourth group readout period 407, respectively. Reference numeral 408 denotes a fourth group readout period in the (n-1) th row that is the previous row.

  In the first shift register 110, during the fourth group reading of the (n-1) th row, a pixel correction processing operation is performed in synchronization with the pixel data from the image sensor 101 (409). In the second shift register 301, the first group data of the nth row to be read next is initialized (410). In this way, each shift register performs an operation of alternately repeating the initialization process and the correction process.

Next, the effect of this embodiment will be described.
In the first embodiment, since the initialization processing of the correction data for the nth row is performed only during the horizontal blank period, it is necessary to set the column for the nth row during that period. For example, when the number of columns of the image sensor 101 is 3000, 3000 stages of shift registers are required.

  On the other hand, in this embodiment, for example, by dividing 3000 columns into four groups of 750 columns and preparing two 750-stage shift registers in parallel, the required shift registers can be reduced. Further, for example, if divided into 300 groups instead of four groups, two 10-stage shift registers need only be provided in parallel, and the circuit scale required for the shift registers can be drastically reduced.

  Here, there are cases where there are a large number of pixels to be corrected, and the initialization processing time as shown in FIG. The image sensor 101 that has become unusable due to insufficient initialization processing time becomes a defective product and causes a decrease in yield. In order to further increase the initialization processing time, the number of the memory fetch unit 107, the address decoder unit 109, and the shift registers arranged in parallel may be increased.

  FIG. 5 is a schedule diagram when the memory fetch unit 107 and the address decoder unit 109 are increased by one and the shift register is further increased by two with respect to the image data processing apparatus shown in FIG. As shown in FIG. 5, the first shift register 501 and the second shift register 502 are in charge of correction processing for the even number group, and a new third shift controlled by the added memory fetch unit and address decoder unit. By configuring the register 503 and the fourth shift register 504 to perform correction processing for the odd-numbered group, a double data initialization processing period can be secured. Furthermore, if it is desired to increase the initialization processing period, a memory fetch unit, an address decoder unit, and a shift register may be added.

  As described above, with the configuration of the present embodiment, a faster frame rate can be realized even in an image sensor having a large number of pixels per row. In addition, a pixel correction instruction signal is sent from one of the shift registers 110 and 301 to the image correction unit 103 in synchronization with the pixel data corresponding to the address of the pixel to be corrected being input from the image sensor 101 to the image correction unit 103. Since the output is made, the frame memory that has been conventionally required can be dispensed with. Thereby, the circuit scale can be reduced as compared with the conventional correction circuit, and an image data processing apparatus with less superimposed noise can be realized by employing a circuit that can be driven at a low clock frequency. .

  Even in an image sensor having a larger number of pixels per row, the pixel to be corrected can be accurately processed by synchronizing the pixel correction instruction signal from the shift register 110 and the pixel data captured from the image sensor 101. .

  In addition, when there is a plurality of shift registers and one shift register is performing a correction operation, the time required for the initialization process is effectively reduced to zero by sequentially initializing the other shift registers. be able to. Thereby, an even faster frame rate can be realized.

(Third embodiment)
Next, an embodiment when the image data processing apparatus according to the present invention is applied to an imaging apparatus (digital camera) will be described.

  FIG. 6 is a block diagram showing an example in which the image data processing apparatus according to the present invention is applied to an imaging apparatus.

  In FIG. 6, reference numeral 11 denotes a barrier that serves as a main switch for protecting the lens 12, 12 denotes a lens that forms an optical image of a subject on the image sensor 14, 13 denotes a diaphragm for changing the amount of light passing through the lens 12, and 14. An image sensor 15 for taking in the subject image formed by the lens 12 as an image signal, 15 is an image data processing apparatus according to the present invention, and an image correction unit 18 for correcting a defect in the image signal output from the image sensor 14. have. Reference numeral 16 denotes an A / D converter that performs analog-digital conversion of the image signal output from the image data processing device 15, and reference numeral 17 denotes various corrections to the image data output from the A / D converter 16, or A signal processing unit for compression. Here, the image data processing device 15 includes a drive circuit that supplies a timing signal to the image sensor 14, the A / D converter 16, the image correction unit 18, the signal processing unit 17, and the like. The drive circuit is formed on the same semiconductor chip. Further, the image sensor processing device 15 may be a subsequent stage of the A / D converter 16.

  19 is an overall control / arithmetic unit for controlling various calculations and the entire imaging apparatus, 20 is an image data memory unit for temporarily storing image data, and 21 is a storage medium for recording or reading out the storage medium. A control interface unit 22 is a detachable storage medium such as a semiconductor memory for recording or reading image data, and 23 is an external interface unit for connecting to an external computer or the like.

Next, an operation at the time of shooting of the imaging apparatus having the above configuration will be described.
First, when the barrier 11 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 16 is turned on.

  Next, the signal output from the image sensor 14 is corrected by the image correction unit 18 and output to the A / D converter 16 if there is a signal of a defective pixel in the image sensor processing device 15, and the A / D After being converted by the converter 16, the signal is input to the signal processing unit 17.

  Then, predetermined processing is performed by the signal processing unit 17, and the output image data is written into the image data memory unit 20 by the overall control / calculation unit 19. Next, the data stored in the image data memory unit 20 is recorded on the storage medium 22 via the storage medium control interface unit 21 under the control of the overall control / calculation unit 19. Further, the image data may be processed by directly inputting to a computer or the like through the external interface unit 23.

  By adopting the configuration of the present embodiment, it is possible to correct a defect in the image signal output from the image sensor 14 and to realize an image pickup apparatus with high image quality.

(Another embodiment of the present invention)
The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device.

  In the above embodiment, the address holding memory unit 106, the memory fetch unit 107, the row counter 108, the group counter 306, the address decoder 109, and the like are configured by functional blocks. However, a general-purpose control device such as a CPU is used. Even if these functions are implemented in software, the same effect can be obtained. That is, various devices are operated so as to realize the functions of the above-described embodiments, and the devices connected to the various devices or the computers in the system are transferred from a storage medium or via a transmission medium such as the Internet. A software program code for realizing the functions of the above-described embodiment is supplied, and the above-mentioned various devices are operated according to a program stored in a computer (CPU or MPU) of the system or apparatus. It is included in the category of the invention.

  In this case, the program code of the software itself realizes the functions of the above-described embodiments, and the program code itself and means for supplying the program code to the computer, for example, the program code are stored. This storage medium constitutes the present invention. As a storage medium for storing the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  Further, by executing the program code supplied by the computer, not only the functions described in the above-described embodiments are realized, but also the OS (operating system) or other operating system in which the program code is running on the computer. Such program code is also included in the embodiment of the present invention even when the functions described in the above-described embodiment are realized in cooperation with application software or the like.

  Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the CPU provided in the function expansion board or function expansion unit based on the instruction of the program code The present invention also includes a case where the functions of the above-described embodiment are realized by performing part or all of the actual processing.

101: Image sensor, 102: Input terminal, 103: Image correction unit, 104: Input terminal, 105: Instruction signal input terminal, 106: Address holding memory unit, 107: Memory fetch unit, 108: Row counter, 109: Address decoder 110: shift register, 111: final stage of the shift register, 112: output terminal, 113: image data processing device

Claims (8)

In the image data processing apparatus connected to the output terminal of the image sensor that outputs the image data separately for each row of pixel data,
A memory for storing address data of correction target pixels of the image sensor;
A row counter that indicates a row of current pixel data output from the image sensor;
A memory data fetch unit for reading the address data from the memory;
An address decoding unit for determining whether or not a row of pixel data to which a correction target pixel of the address data read by the memory data fetch unit coincides with a row of pixel data designated by the row counter; ,
A shift register that is set based on the address data stored in the memory and outputs a correction instruction signal in accordance with a determination result in the address decoding unit;
An image correction unit that corrects pixel data output from the image sensor based on a correction instruction signal output from the shift register;
The shift register operates in synchronization with the image data sequentially output from the image sensor, and correction for the image data from the image sensor is controlled,
The image data processing apparatus, wherein the shift register shifts in synchronization with pixel data appearing at an output terminal of the image sensor and outputs the correction instruction signal to the image correction unit.   The image data processing apparatus according to claim 1, wherein the shift register is initialized based on the address data in a horizontal blanking period of the image sensor.   3. The image data processing apparatus according to claim 1, wherein the pixel data of a certain row and the pixel data of the next row appear at a predetermined interval at an output terminal of the image sensor.   The image data processing apparatus according to claim 1, wherein the shift register and the image correction unit are formed on the same semiconductor chip. at least,
An optical system for forming a subject image;
An image sensor that outputs a subject image formed by the optical system as an image signal;
The image data processing device according to any one of claims 1 to 4,
An image pickup system comprising: signal processing means for processing an image signal from the image data processing device. In the image data processing method by the image data processing device connected to the output terminal of the image sensor that outputs the image data separately for each row of pixel data,
A storage process for storing address data of a correction target pixel of the image sensor in a memory;
An instruction process for indicating a row of current pixel data output from the image sensor;
A read process for reading the address data from the memory;
A determination process for determining whether or not a row of pixel data to which a correction target pixel of the address data read out in the read-out process matches a row of pixel data instructed in the instruction process;
An output process that is set based on the address data stored in the memory, and that outputs a correction instruction signal from a shift register according to the determination result in the determination process;
An image correction process in which an image correction unit corrects pixel data output from the image sensor based on a correction instruction signal output from the shift register, and
The shift register operates in synchronization with the image data sequentially output from the image sensor, and correction for the image data from the image sensor is controlled,
The image data processing method, wherein the shift register shifts in synchronization with pixel data appearing at an output terminal of the image sensor and outputs the correction instruction signal to the image correction unit. In a computer program for causing a computer to execute an image data processing method by an image data processing apparatus connected to an output terminal of an image sensor that outputs image data divided for each row of pixel data,
A storage process for storing address data of a correction target pixel of the image sensor in a memory;
An instruction process for indicating a row of current pixel data output from the image sensor;
A read process for reading the address data from the memory;
A determination process for determining whether or not a row of pixel data to which a correction target pixel of the address data read out in the read-out process matches a row of pixel data instructed in the instruction process;
An output process that is set based on the address data stored in the memory, and that outputs a correction instruction signal from a shift register according to the determination result in the determination process;
Causing the computer to execute an image correction process in which an image correction unit corrects pixel data output from the image sensor based on a correction instruction signal output from the shift register;
The shift register operates in synchronization with the image data sequentially output from the image sensor, and correction for the image data from the image sensor is controlled,
The computer program, wherein the shift register shifts in synchronization with pixel data appearing at an output terminal of the image sensor and outputs the correction instruction signal to the image correction unit.   A computer-readable storage medium storing the computer program according to claim 7.

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