JPH0629149U - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

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Publication number
JPH0629149U
JPH0629149U JP092276U JP9227691U JPH0629149U JP H0629149 U JPH0629149 U JP H0629149U JP 092276 U JP092276 U JP 092276U JP 9227691 U JP9227691 U JP 9227691U JP H0629149 U JPH0629149 U JP H0629149U
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Prior art keywords
lead piece
thickness
resin
semiconductor device
external electrode
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JP092276U
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JP2555522Y2 (ja
Inventor
睦 佐々木
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Publication of JP2555522Y2 publication Critical patent/JP2555522Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005Shape
    • H01L2224/4009Loop shape
    • H01L2224/40091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005Shape
    • H01L2224/4009Loop shape
    • H01L2224/40095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 (修正有) 【目的】 リ−ド片のフォ−ミング加工による薄型化の
困難性、外部電極部からの放熱効果が小なること、加工
ストレスによる信頼性低減を簡単な構造で、かつ製造容
易に解決する面実装構造の樹脂封止型半導体装置を得る
ことを目的とする。 【構成】 リ−ド片の外部電極部の厚さを、少なくと
も、該リ−ド片の半導体素子固着部の厚さより実装面に
向かって厚くしたことを特徴とする。

Description

【考案の詳細な説明】
【0001】
【産業上の利用分野】
本考案は、樹脂封止型半導体装置の構造、特に、表面実装用に適した樹脂封 止型半導体装置に関するものである。
【0002】
【従来の技術】
従来、外部電極を具備する樹脂封止型半導体装置、特に、外部電極を面状と して回路基板等に面実装を容易とする樹脂封止型半導体装置の構造としては 、例えば、図1の構造図のごときものがあり、(a)は断面図、(b)は底 面図である。図1において、1はリ−ド片、2は半導体素子、3は接続子、 4は封止樹脂であり、通常、リ−ドフレ−ムによる複数のリ−ド片1の上に 半導体素子2及び接続子3を所定の位置に半田付けし、それらをエポキシ樹 脂等の封止樹脂4により成型封止している。その後、リ−ドフレ−ムの不要 部分を切断除去し、更に、リ−ド片1の外部導出部分をフォ−ミング加工に より折り曲げ、外部電極を形成していた。
【0003】 しかして、図1の従来構造において、封止樹脂4の厚さt1は、リ−ド片1 (2) のフォ−ミング加工による加圧やその他の製造上又は構造上の都合から、一 定の厚みを必要とし、半導体装置の薄型化の障害の一つであった。又、リ− ド片1の厚さt2は、フォ−ミング加工に適した厚み以上にすることは好ま しくなく、従って、リ−ド片1の放熱容積の増加に制限があり、半導体装置 の大電流容量化に問題があった。更に、フォ−ミング加工のストレスがリ− ド片1の導出部分の封止樹脂4にかかり、導出部分に隙間を生ずる原因とな り、信頼性の面でも問題があった。
【0004】
【考案が解決しようとする課題】
解決しようとする問題点は、リ−ド片のフォ−ミング加工に伴って、リ−ド 片の折曲げ部における封止樹脂を薄型化することが困難であること、リ−ド 片の厚さによる放熱容量の増加に制限があり、大電流容量化が困難であるこ と、及びフォ−ミング加工時のストレスによる封止樹脂のリ−ド片導出部分 における隙間発生の原因となることである。
【0005】
【課題を解決するための手段】
リ−ド片の外部電極部の厚さを、少なくとも該リ−ド片の半導体素子固着部 の厚さより実装面に向かって厚くすることを特徴とし、リ−ド片のフォ−ミ ング加工による製造上の厄介さを解決し、電流容量の増大、小型化及び信頼 性向上を簡単な構造により実現する。
【0006】
【実施例】
図2は本考案装置の一実施例を示す構造図で、(a)は断面図、(b)は底 面図であり、図1と同一符号は同一部分を示す。本考案装置の要部をなすリ −ド片1は、外部電極部A、半導体素子固着部B及び接続子固着部Cの3部 分を含んでおり、外部電極部Aの厚さは、半導体素子固着部B及び接続子固 着部Cの厚さより、実装面、即ち、図2(a)の下方に向かって厚く形成す る。つまり、実装面において、必要とする外部電極部Aの間隔lを保ち、リ (3) −ド片1のA、B及びCの各部により形成される凹部は封止樹脂4の一部に よりみたされる。この実施例では、リ−ドフレ−ムによる複数のリ−ド片1 のA部の厚さの約10〜50%をエッチング法で薄くしてB部及びC部の厚 さを形成した。次いで、各部の所定位置に半導体素子2及び接続子3を半田 付けし、モ−ルド法により封止樹脂4を形成した。その後、不要のリ−ドフ レ−ム部分を所定寸法で切断除去して、個別の半導体装置とした。
【0007】 前記の実施例では、リ−ド片1のB部及びC部をA部に対し、薄くしたが、 外部電極部A間の距離の確保ができれば、接続子固着部Cは必ずしも薄くす る必要はない。又、薄くする手段としては、エッチング加工の他、プレス加 工や切削加工の使用も可能であり、薄くする寸法の程度も設計に応じて任意 に選択できる。
【0008】 図2の実施例では、外部電極部Aを2個とする2端子型であるが、必要に応 じて、3端子型以上にも適用でき、半導体素子、接続子についても、複数個 の封入してもよい。又、ダイオ−ド、トランジスタ、サイリスタ等のいずれ の半導体素子でもよく、更に、他部品との混成装置にも適用できる。なお、 接続子は片状又はワイヤ−状のいずれでもよい。その他、本考案の要旨の範 囲で任意に変形、変換及び付加をなし得るものである。
【0009】 前記の実施例による整流ダイオ−ドの出力電流は従来構造に比し、20%程 度増大することができた。又、図1(a)の厚さt3に比し、図2(a)の 厚さt3の減少分だけ半導体装置の薄型化を達成できた。
【0010】
【考案の効果】
以上説明したように、本考案の樹脂封止型半導体装置は、表面実装用として のリ−ド片のフォ−ミング加工の必要がなく、薄型化、大電流容量化及び高 信頼化を製造容易に、かつ簡単な構造で達成でき、回路基板への面実装構造 (4) による電子機器等に利用して、産業上の効果大なるものである。
【図面の簡単な説明】
【図1】従来装置の構造図であり、(a)は断面図、
(b)は底面図である。
【図2】本考案の実施例を示す構造図であり、(a)は
断面図、(b)は底面図である。
【符号の説明】
1 リ−ド片 2 半導体素子 3 接続子 4 封止樹脂 A 1の外部電極部 B 1の半導体素子固着部 C 1の接続子固着部 t1、t2、t3、l 指定の寸法

Claims (2)

    【実用新案登録請求の範囲】
  1. 【請求項1】 少なくとも、半導体素子、リ−ド片、接
    続子及び封止樹脂から成る樹脂封止型半導体装置におい
    て、リ−ド片の外部電極部の厚さを少なくとも該リ−ド
    片の半導体素子固着部の厚さより実装面に向かって厚く
    したことを特徴とする樹脂封止型半導体装置。
  2. 【請求項2】 リ−ド片の接続子固着部の厚さより該リ
    −ド片の外部電極部のの厚さを実装面に向かって厚くし
    たことを特徴とする請求項1の樹脂封止型半導体装置。
JP1991092276U 1991-10-15 1991-10-15 樹脂封止型半導体装置 Expired - Fee Related JP2555522Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991092276U JP2555522Y2 (ja) 1991-10-15 1991-10-15 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991092276U JP2555522Y2 (ja) 1991-10-15 1991-10-15 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
JPH0629149U true JPH0629149U (ja) 1994-04-15
JP2555522Y2 JP2555522Y2 (ja) 1997-11-26

Family

ID=14049881

Family Applications (1)

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Country Status (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005277434A (ja) * 2005-05-09 2005-10-06 Renesas Technology Corp 半導体装置
JP4731021B2 (ja) * 2001-01-25 2011-07-20 ローム株式会社 半導体装置の製造方法および半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01184836A (ja) * 1988-01-13 1989-07-24 Murata Mfg Co Ltd 半導体装置
JPH0369130A (ja) * 1989-08-08 1991-03-25 Nec Corp 樹脂封止型半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01184836A (ja) * 1988-01-13 1989-07-24 Murata Mfg Co Ltd 半導体装置
JPH0369130A (ja) * 1989-08-08 1991-03-25 Nec Corp 樹脂封止型半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4731021B2 (ja) * 2001-01-25 2011-07-20 ローム株式会社 半導体装置の製造方法および半導体装置
JP2005277434A (ja) * 2005-05-09 2005-10-06 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
JP2555522Y2 (ja) 1997-11-26

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